Department of Technical Education

Andhra Pradesh

Name : P. Srinivasa Rao

Designation : Lecturer
Branch : Electronics & Communication Engg.
Institute : Andhra Polytechnic, Kakinada
Year/Semester : III Semester
Subject : Digital Electronics
Subject Code : CM-305
Topic : Counters& Registers
Duration : 50Mts.
Sub Topic : Ring Counter
Teaching Aids : PPT. Diagrams

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Objectives

On completion of this period, you would be

able to:

• Know the circuit diagram of Ring counter

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Recollect

1. What is Ring counter ?

In this counter , only one flip-flop being set at any
particular time and all other flip-flops are cleared . The
single bit is shifted from one flip-flop to the other to
produce the sequence of timing signals.

2. Why it is called as Ring counter ?

The output can be fed back in to the input to form a
“Ring”.

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Edge triggered flip-flops

In general ,the counters are designed using

edge triggered flip-flops.

• There are two types of edge triggered flip-flops namely

• Positive edge triggered flip-flops.

• Negative edge triggered flip-flops.

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Positive Edge Triggered Flip-Flop

Negative Edge Triggered Flip-Flop

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• Notice that no bubble at the clock input in the case of
Positive edge triggered.

• Negative edge triggered is with a bubble at the clock

input.

• The flip flop can not change the state except on the
triggering edge of a clock pulse.

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SYNCHRONOUS INPUTS

• The inputs J,K are called synchronous inputs

• Data on these inputs are transferred to the flip flop’s

output only on the triggering edge of the clock pulse.

• Data from these inputs are transferred synchronously

with the clock.

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PRESET & CLEAR INPUTS

• These are asynchronous inputs , that affect the state of

the flip flop as independent of the clock.

• These inputs are active low as indicated by bubbles.

• An active level on the preset input will set the flip-flop.

• An active level on the clear input will reset the flip-flop.

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J K Flip Flop with PRESET ,CLEAR Inputs

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Introduction

• A Ring counter is a circular shift register.

• At any time only one flip flop being set and all other flip
flops are cleared.

• Single bit is shifted from one flip flop to other to produce

the sequence of timing signals.

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4 – bit Ring counter
4-Bit Ring Counter

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• J&K: Synchronous inputs which must be high. If
J=K=1,ouput toggles i.e. the output changes alternatively
from 0 to 1 (or) 1 to 0.

• QA,QB, QC &QD: The outputs which are entirely

dependent on the clock pulses and J&K inputs.

• CLK: It is a timing signal given at the input

simultaneously to all the flip flops

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Summary

• The circuit diagram of Ring counter.

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QUIZ

1. A Ring counter is a ------- register.

i) shift left

ii) universal register

iii) shift right

iv) circular shift register

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2. An active level on the preset input will

iv) set the FF

ii) Reset the FF

iii) no change the FF

iv) none

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Questions

1. Draw the block schematic of ring counter.

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