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DEPARTMENT OF TECHNICAL

EDUCATION,A.P.
Name : B.RAJARAO.
Designation : Lecturer.
Branch : Electronics & communication Engg.
Institute : Govt. Polytechnic, Visakhapatnam.
Year/Semester : III Semester.
Subject : Electronics –I.
Subject Code : EE-305.
Topic : Special devices.
Duration : 50Mts.
Sub Topic : Working principle of JFET.
Teaching Aids : Diagrams.

EE-305.46
Recap

• Already we discussed about the constructional


details of FET.

• Formation of channels.

• Types of FET.

EE-305.46 2
Objectives

• Upon completion of this period the student will be able to


know

• The terminals of FET.

• The channel of FET.

• Effect of the channel width on operation of


FET.

• Working principle of FET.

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Do you know

• The working principle of Bipolar junction


transistor.

• The factors effecting the output current of


BJT.

• The differences between majority carriers


and minority carriers.

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Junction field effect transistor

DEVICE CIRCUIT SYMBOL

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WORKING OF JFET

• SOURCE :It is the


terminal from which the
majority carriers enter the
bar.

• DRAIN : It is the terminal


from which the majority
carriers leave the bar.

• GATE: The two sides of a


N-type bar contains
heavily doped P-region
called gate. EE-305.46 6
WORKING OF JFET

• The gate and channel


form a P-N junction.

• CIRCUIT SYMBOLS:
Arrow indicates direction
of current flowing.

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WORKING OF JFET

Id

• For proper functioning of


the JFET, biasing
voltages are to be applied Vdd
between Drain and
S
Source (Vdd) and
between Gate and Vg
g
Source (Vgg).

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WORKING OF JFET

Id
• The polarities of drain
supply should be such
that majority carriers flow
from Source to Drain V ds
through the channel when
the bias is applied. V gg

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WORKING OF JFET

Id

• The gate supply is


commonly used to
provide reverse bias for
the P-N junctions formed Vdd
between the gate (P+) s
and Channel (N). The fig. Vgg
shows the FET with bias
voltages.

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WORKING OF JFET

• Let Vgs = 0 and a small


voltage be applied to Vds.
• The two P-N junctions are
reverse biased and Vds
depletion layers are
formed across the
junction.

Vgg
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• Due to the supply Vds,
the electrons in the N-
type bar flow from source
to drain constituting drain
current Id.

• When Vds is increased,


drain current Id also
increases initially.

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WORKING OF JFET

• When a small voltage is


applied to the gate by
increasing Vgs, the Depletion region

reverse bias on the P-N Vds


junctions is increased.

• So the depletion width


also increases.

Vgg
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WORKING OF JFET

• Since the N-type bar is


lightly doped compared to
the P-region, the
depletion region width
increases .
Depletion region

Vds
• The increased depletion
region causes the
reduction in the
conductive portion of the
channel thereby
increasing the resistance
of the channel.
Vgg
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WORKING OF JFET

• As a result, the drain


current is reduced. In this
way the drain current is
controlled by the gate
voltage.

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WORKING OF JFET

• Since N-material is
resistive, the drain current
causes a voltage drop
along the channel.

• This voltage drop reverse


biases the P-N junctions
between gate and channel.
When Vds is increased
drain current is increased.

EE-305.46 16
WORKING OF JFET

• Increased Id causes more


voltage drop which
provide more reverse
bias for the junction.

• As a result the width of
the depletion region is
increased.

• Due to this the current Id


is reduced.”.

EE-305.46 17
WORKING OF JFET

• So, when the voltage Vds


is increased from zero the
drain current increases Depletion region

initially. Vds

• But at one instant the


drain current adjusts itself
to a constant value.

Vgg
EE-305.46 18
WORKING OF JFET

• when the increase in


current (due to increase
in Vds) is compensated
by the decrease in
Depletion region
current (due to the Vds
increased depletion
region).

• This voltage is known as


“pinch off voltage.

Vgg
EE-305.46 19
WORKING OF JFET

• It is to be noted that the width of depletion is not uniform


along the P-N junctions.

• When the drain current flows, the channel works as a


resistor and the potential drop is different at different
points of the channel.

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WORKING PRINCIPLE OF JFET USING
SIMULATION
• The reverse voltages for the junction is also different at
different points.

• Therefore, the reverse bias is maximum at the point


nearer to the drain.

• The reverse bias is minimum at the point nearer to the


source.

• That is why the width of the depletion region is more at


Drain and less at source.

EE-305.46 21
WORKING PRINCIPLE OF JFET USING
SIMULATION

EE-305.46 22
WORKING PRINCIPLE OF JFET USING
SIMULATION

EE-305.46 23
WORKING PRINCIPLE OF JFET USING
SIMULATION

EE-305.46 24
Summary

• FET is semiconductor device in which the current.

• Is controlled by electric field.

• Is carried by only majority carriers.

• Pinch off voltage is the value of v ds at which all the


free charges from the channel get removed.

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Quiz
• 1 ) In The Junction field effect transistor the
conduction carriers are

(a) Holes

(b) Electrons

(c) Either electrons or holes

(d) None.

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Quiz

• 2) The Junction field effect transistor is

(a) Unipolar device

(b) Bipolar device

(c) passive device

(d) None

EE-305.46 27
Frequently asked questions

• Explain the working principle of Junction field


effect transistor ?

2. Define Pinch-off voltage ?

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