Beruflich Dokumente
Kultur Dokumente
STRUCTURAL MODELING
TOPICS TO BE COVERED
• Parts Library
• Wiring of primitives
• Wiring of iterative networks
• Top-Down wiring
• Modeling Test Benches
Parts Library
• library – holds all predefined cells
x
y carry
enable
result
• VHDL mechanisms to incorporate design
objects
– Using direct instantiation (not available prior to
VHDL-93)
– Using component declarations and instantiations
• Create idealized local components (i.e. declarations)
and connect them to local signals (i.e. instantiations)
• Component instantiations are then bound to VHDL
design objects either :
– Locally -- within the architecture declaring the component
– At higher levels of design hierarchy, via configurations
Structure Example
bit0
d_latch
d0 q0
d q
clk
bit1
d_latch
d1 q1
d q
clk
bit2
d_latch
d2 q2
d q
clk
bit3
d_latch
d3 q3
d q
gate clk
and2
en int_clk
a y
clk
b
Structure Example
• First declare D-latch and and-gate entities
and architectures
entity d_latch is entity and2 is
port ( d, clk : in bit; q : out bit ); port ( a, b : in bit; y : out bit );
end entity d_latch; end entity and2;