FET Biasing

Fixed Biased Configuration

Group Members
Hafiz Aamir Hafeez BCE-FA10-010 Yasir Jameel BCE-FA10-051 Farooq Hassan BCE-FA10-045 M.Awais Sattar BCE-FA10-031 Muazzam Ali BCE-FA10-025

Introduction

For the JFET, the relationship between input and output quantities is nonlinear due to the squared term in Shockleys equation. Nonlinear functions results in curves as obtained for transfer characteristic of a JFET. Graphical approach will be used to examine the dc analysis for FET because it is most popularly used rather than mathematical approach The input of BJT and FET controlling variables are the current and the voltage levels respectively

Introduction
JFETs differ from BJTs:

Nonlinear relationship between input (VGS) and output (ID) JFETs are voltage controlled devices, whereas BJTs are current controlled

Introduction
Common FET Biasing Circuits JFET Fixed Bias Self Bias Voltage Divider Bias

Depletion-Type MOSFET Self Bias Voltage Divider Bias Enhancement-Type MOSFET Feedback Configuration Voltage Divider Bias
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General Relationships

For all FETs:

IG 0A ID IS

For JFETs and Depletion-Type MOSFETs:

VGS 2 ID IDSS(1 ) VP

For Enhancement-Type MOSFETs:

I D k (VGS VT ) 2

Fixed-Bias Configuration
The configuration includes the ac levels Vi and Vo and the coupling capacitors. The resistor is present to ensure that Vi appears at the input to the FET amplifier for the AC analysis.

Fixed-Bias Configuration

For the DC analysis, Capacitors are open circuits IG 0 A andV RG I G RG (0 A) RG 0V The zero-volt drop across RG permits replacing RG by a shortcircuit

Fixed-Bias Configuration
Investigating the input loop IG=0A, therefore VRG=IGRG=0V

Applying KVL for the input loop, -VGG-VGS=0 VGG= -VGS

It is called fixed-bias configuration due to VGG is a fixed power supply so VGS is fixed The resulting current,
ID IDSS(1 VGS 2 ) VP

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Investigating the graphical approach. Using below tables, we can draw the graph
VGS 0 0.3VP 0.5VP VP ID IDSS IDSS/2 IDSS/4 0mA

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In graph the fixed level of VGS has been superimposed as a vertical line at VGS =-VGG. At any point on the vertical line, the level of VGS is -VGG the level of ID must simply be determined on this vertical line. The point where the two curves intersect is the common solution to the configuration commonly referred to as the quiescent or operating point. The subscript Q will be applied to drain current and gate-to-source voltage to identify their levels at the Qpoint.

Output loop
VDS VDD I D RD
VS 0V VDS VD VS
VD VDS VS

VS 0

V D V DS
VGS VG VS VG VGS VS

VS 0

VG VGS

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EXAMPLE

Determine the following for the network of FIG (a) VGSQ (b) IDQ (c) VDS (d) VD (e) VG (f) VS
Solution : (a) VGSQ= -VGG = - 2 V (b) IDQ=IDSS(1-VGS/vP )2 = 10 mA(1 - 0.25)2 = 10 mA(0.75)2 =10 mA(0.5625) = 5.625 mA (c) VDS=VDD - IDRD = 16 V - (5.625mA)(2k) =16 V - 11.25 V = 4.75 V (d) VD = VDS =4.75 V (e) VG = VGS =2 V (f) VS = 0 V

Graphical Approach

Advantages of FET The main advantage of the FET is its high input resistance, on the order of 100M ohms or more. Thus, it is a voltage-controlled device, and shows a high degree of isolation between input and output. It is a unipolar device, depending only upon majority current flow. It is less noisy and is thus found in FM tuners for quiet reception. It is relatively immune to radiation. It exhibits no offset voltage at zero drain current and hence makes an excellent signal chopper. It typically has better thermal stability than a BJT. Disadvantages of FET It has relatively low gain-bandwidth product compared to a BJT. The MOSFET has a drawback of being very susceptible to overload voltages, thus requiring special handling during

Uses IGBTs see application in switching internal combustion engine ignition coils, where fast switching and voltage blocking capabilities are important. The most commonly used FET is the MOSFET. The CMOS (complementary metal oxide semiconductor) process technology is the basis for modern digital integrated circuits. This process technology uses an arrangement where the (usually "enhancementmode") p-channel MOSFET and n-channel MOSFET are connected in series such that when one is on, the other is off. The fragile insulating layer of the MOSFET between the gate and channel makes it vulnerable to electrostatic damage during handling. This is not usually a problem after the device has been installed in a properly designed circuit. In FETs electrons can flow in either direction through the channel when operated in the linear mode, and the naming convention of drain terminal and source terminal is somewhat arbitrary, as the devices are typically (but not always) built symmetrically from source to drain. This makes FETs suitable for switching analog signals between paths (multiplexing). With this concept, one can construct a solid-state mixing board, for example. A common use of the FET is as an amplifier. For example, due to its