Introduction To 8085 Architecture and Programming: Ifetce/It/Ii Year/ Iv Sem/IT141402/MPMC/ Ver 1.0 1

Introduction to 8085 Architecture and Programming
IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0
Contents 1. 8085 pin description 2. 8085 system bus 3. Internal architecture of 8085 microprocessor 4. 8085 functional description. 5. Interrupts of 8085 microprocessor 6. Instruction set classification. 7. Instruction format. 8. Addressing modes. 9. Instructions of 8085 9. Sample programs.
IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0 2
8085 microprocessor..
It is a program controlled semiconductor device (IC}, which fetches, decode and executes instructions.
Introduction of 8085
It is a 8 bit processor It is a single chip N-Mos Device with 40 Pins It has multiplexed address and Data lines(AD0 to AD) It works on 5 Volt power supply The Max clock frequency is 3 MHz and the Min is 500KHz It Provides 74 instruction with 5 different addressing Modes
Introduction Of 8085
It provides 16 address lines so it can access 2 ^ 16 =64K bytes of memory. It generates 8 bit I/O address so it can access 2 ^8=256 input ports. It provides 5 hardware interrupts: TRAP, RST 5.5, RST 6.5, RST 7.5,INTR. It provides Acc ,one flag register ,6 general purpose registers and two special purpose registers(SP,PC). It provides serial lines SID ,SOD.So serial peripherals can be interfaced with 8085 directly.
PIN DIAGRAM
8085
IFETCE/IT/II Year/ IV Signals and I/O Pins Sem/IT141402/MPMC/ Ver 1.0
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The 8085 Microprocessor Architecture
Intel 8085 CPU (Architecture)Block Diagram
10 10
16-bit Registers
Ge ne ral Purpose
AH AL
Inde x BP SP
AX
BH
BL
BX
SI
CH CL
CX
DI
DH
DL
DX
Segme nt CS Status and Control Flags IP SS DS ES
11
Flag Register of 8085
12
Control Unit Generates signals within uP to carry out the instruction, which has been decoded. In reality causes certain connections between blocks of the uP to be opened or closed, so that data goes where it is required, and so that ALU operations occur. Arithmetic Logic Unit The ALU performs the actual numerical and logic operation such as add, subtract, AND, OR, etc. Uses data from memory and from Accumulator to perform arithmetic. Always stores result of operation in Accumulator. Registers The 8085/8080A-programming model includes six registers, one accumulator, and one flag register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer and the program counter. They are described briefly as follows. The 8085/8080A has six general-purpose registers to store 8-bit data; these are identified as B,C,D,E,H, and L as shown in the figure. They can be combined as register pairs - BC, DE, and HL - to perform some 16-bit operations. The programmer can use these registers to store or copy data into the registers by using data copy instructions.
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Accumulator The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator. The accumulator is also identified as register A. Flags The ALU includes five flip-flops, which are set or reset after an operation according to data conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; they are listed in the Table and their bit positions in the flag register are shown in the Figure below. The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data conditions. For example, after an addition of two numbers, if the sum in the accumulator id larger than eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) is set to one. When an arithmetic operation results in zero, the flip-flop called the Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag register, adjacent to the accumulator. However, it is not used as a register; five bit positions out of eight are used to store the outputs of the five flip-flops. The flags are stored in the 8-bit register so that the programmer can examine these flags (data conditions) by accessing the register through an instruction.
Signal Flow in 8085
15 IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0
Now, Let us see how the different units and bus systems stay connected:
A15- A10
Chip Selection Circuit
8085
A15-A8
ALE
CS
A9- A0
AD7-AD0 Latch
A7- A0
1K Byte Memory Chip
WR
RD
IO/M
D7- D0
RD
WR
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Types of Interrupts:
8085 supports two types of interrupts.

Hardware interrupts Software interrupts
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Software interrupts:
The software interrupts are program instructions. These instructions are inserted at desired locations in a program. The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for these interrupts can be calculated as follows. Interrupt number * 8 = vector address For RST 5,5 * 8 = 40 = 28H Vector address for interrupt RST 5 is 0028H
The Table shows the vector addresses of all interrupts.
19
Hardware interrupts:
External device initiates the hardware interrupts and placing an appropriate signal at the interrupt pin of the processor. If the interrupt is accepted then the processor executes an interrupt service routine.
Hardware interrupts Cont..

The 8085 has five hardware interrupts (1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR
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8085 Interrupts
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How SIM Interprets the Accumulator

7 6 5 4 3 2 1 0
M6.5
SDO
SDE
XXX
M7.5
Serial Data Out
M5.5
MSE
R7.5
RST5.5 Mask
RST6.5 Mask 0 - Available 1 - Masked RST7.5 Mask Mask Set Enable 0 - Ignore bits 0-2 1 - Set the masks according to bits 0-2 Force RST7.5 Flip Flop to reset
Enable Serial Data 0 - Ignore bit 7 1 - Send bit 7 to SOD pin

Not Used
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RIM sets the Accumulators different bits
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TRAP:
This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable. TRAP bas the highest priority and vectored interrupt. TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and remain high until it is acknowledged. In sudden power failure, it executes a ISR and send the data from main memory to backup memory. The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is recognized). There are two ways to clear TRAP interrupt. 1.By resetting microprocessor (External signal) 2.By giving a high TRAP ACKNOWLEDGE (Internal signal)
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RST 7.5:
The RST 7.5 interrupt is a maskable interrupt. It has the second highest priority. It is edge sensitive. ie. Input goes to high and no need to maintain high state until it recognized.
Maskable interrupt. It is disabled by, 1.DI instruction 2.System or processor reset. 3.After reorganization of interrupt.
Enabled by EI instruction.
RST 6.5 and 5.5:

The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay high until it recognized. Maskable interrupt. It is disabled by,
1.DI, SIM instruction 2.System or processor reset. 3.After reorganization of interrupt.

Enabled by EI instruction. The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
INTR:
INTR is a maskable interrupt. It is disabled by, 1.DI, SIM instruction 2.System or processor reset. 3.After reorganization of interrupt. Enabled by EI instruction. Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the address of ISR. It has lowest priority. It is a level sensitive interrupts. ie. Input goes to high and it is necessary to maintain high state until it recognized. The following sequence of events occurs when INTR signal goes high.
Interrupt table
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1.3 INSTRUCTION SET

BASED ON FUNCTIONS
Data Transfer Instructions

Arithmetic Instructions Logical Instructions Branch Instructions
Machine Control
BASED ON LENGTH One-word or 1-byte instructions Two-word or 2-byte instructions
Three-word or 3-byte instructions
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8085 Instruction Set

The 8085 instructions can be classified as follows:
Data transfer operations
Between Registers Between Memory location and a Registers Direct write to a Register/Memory Between I/O device and Accumulator
Arithmetic operations (ADD, SUB, INR, DCR) Logic operations (AND, OR, NOT) Branching operations (JMP, CALL, RET)
Stack, Machine, I/O Control Operations
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8085 Instruction Types
32
33
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ADDRESSING MODES
Direct Addressing: Jump instructions include a 16-bit address as part of the instruction. For example,
JMP 1000H
the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value 1000H. Instructions that include a direct address require three bytes of storage: one for the instruction code, and two for the 16-bit address
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ADDRESSING MODES
Indirect Addressing: Register indirect instructions reference memory via a register pair. Thus,
MOV M,C
the instruction MOV M,C moves the contents of the C register into the memory address stored in the H and L register pair. The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair.
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ADDRESSING MODES
Register Addressing: Quite a large set of instructions call for register addressing. With these instructions, specify one of the registers A through E, H or L as well as the operation code. With these instructions, the accumulator is implied as a second operand. For example, the instruction
CMP E
may be interpreted as 'compare the contents of the E register with the contents of the accumulator. Most of the instructions that use register addressing deal with 8-bit values. However, a few of these instructions deal with 16-bit register pairs. For example, the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers.
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ADDRESSING MODES
Immediate Addressing: Instructions that use immediate addressing have data assembled as a part of the instruction itself. For example, the instruction
CPI C, 08
may be interpreted as compare the contents of the accumulator with the letter C. When assembled, this instruction has the hexadecimal value FE43. Hexadecimal 43 is the internal representation for the letter C. When this instruction is executed, the processor fetches the first instruction byte and determines that it must fetch one more byte. The processor fetches the next byte into one of its internal registers and then performs the compare operation.
ADDRESSING MODES
Implied Addressing: The addressing mode of certain instructions is implied by the instructions function. For example, the
STC
(set carry flag)
instruction deals only with the carry flag, the DAA (decimal adjust accumulator) instruction deals with the accumulator.
39
Instruction Set of 8085

An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions that a microprocessor supports is called Instruction Set.
8085 has 246 instructions.

Each instruction is represented by an 8-bit binary value. These 8-bits of binary value is called Op-Code or Instruction Byte.
Classification of Instruction Set

Data Transfer Instruction Arithmetic Instructions
Logical Instructions
Branching Instructions Control Instructions
Data Transfer Instructions
These instructions move data between registers, or between memory and registers.
These instructions copy data from source to destination. While copying, the contents of source are not modified.
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Opcode 1 MOV
Operand Rd, Rs M, Rs Rd, M
Description Copy from source to destination.
This instruction copies the contents of the source register into the destination register.
The contents of the source register are not altered.

If one of the operands is a memory location, its location is specified by the contents of the HL registers.
Example: MOV B, C or MOV B, M

Opcode Operand 2 MVI Rd, Data M, Data
Description Move immediate 8-bit
The 8-bit data is stored in the destination register or memory.
If the operand is a memory location, its location is specified by the contents of the H-L registers. Example: MVI B, 57H or MVI M, 57H
44
Opcode 3 LDA
Operand 16- bit address
Description Load Accumulator
The contents of a memory location, specified by a 16bit address in the operand, are copied to the accumulator. The contents of the source are not altered. Example: LDA 2034H
Opcode Operand 4 LXI Reg. pair, 16-bit data Description Load register pair immediate
This instruction loads 16-bit data in the register pair . Example: LXI H, 2034 H
Opcode 5. LDAX
Description Load Accumulator Indirect The contents of the designated register pair point to a memory location.
This instruction copies the contents of that memory location into the accumulator. The contents of either the register pair or the memory location are not altered. Example: LDAX B
Operand B/D Register Pair
Opcode 6 LHLD
Description Load H-L register Direct
This instruction copies the contents of memory location pointed out by 16-bit address into register L.
It copies the contents of next memory location into register H. Example: LHLD 2040 H
47
Opcode 7 STA
Description Store accumulator Direct The contents of accumulator are copied into the memory location specified by the operand. Example: STA 2500 H Opcode 8 STAX Operand Reg. Pair Description Store accumulator Indirect
The contents of accumulator are copied into the memory location specified by the contents of the register pair. Example: STAX B
Opcode 9 SHLD
Description STORE H-L register Direct The contents of register L are stored into memory location specified by the 16-bit address. The contents of register H are stored into the next memory location. Example: SHLD 2550
Opcode Operand Description 10 XCHG NONE EXCHANGE H-L with D-E The contents of register H are exchanged with the contents of register D. The contents of register L are exchanged with the contents of register E. Example: XCHG
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Arithmetic Instructions
These instructions perform the operations like: Addition
Subtract
Increment Decrement
Addition
Any 8-bit number, or the contents of register, or the contents of memory location can be added to the contents of accumulator. The result (sum) is stored in the accumulator. No two other 8-bit registers can be added directly. Example: The contents of register B cannot be added directly to the contents of register C.
Subtraction
Any 8-bit number, or the contents of register, or the contents of memory location can be subtracted from the contents of accumulator. The result is stored in the accumulator. Subtraction is performed in 2s complement form. If the result is negative, it is stored in 2s complement form. No two other 8-bit registers can be subtracted directly.
Increment / Decrement
The 8-bit contents of a register or a memory location can be incremented or decremented by 1.
The 16-bit contents of a register pair can be incremented or decremented by 1. Increment or decrement can be performed on any register or a memory location
Opcode ADD
Operand R M
Description Add register or memory to accumulator
The contents of register or memory are added to the contents of accumulator. The result is stored in accumulator. If the operand is memory location, its address is specified by H-L pair. All flags are modified to reflect the result of the addition. Example: ADD B or ADD M 2 Opcode ADC Operand Description R Add register or memory to accumulator with carry M
The contents of register or memory and Carry Flag (CY) are added to the contents of accumulator. The result is stored in accumulator. If the operand is memory location, its address is specified by H-L pair. All flags are modified to reflect the result of the addition. Example: ADC B or ADC M
Opcode Operand Description ADI 8-bit data Add immediate to accumulator The 8-bit data is added to the contents of accumulator. The result is stored in accumulator. All flags are modified to reflect the result of the addition. Example: ADI 45 H Opcode Operand Description ACI 8-bit data Add immediate to accumulator with carry The 8-bit data and the Carry Flag (CY) are added to the contents of accumulator. The result is stored in accumulator. All flags are modified to reflect the result of the addition. Example: ACI 45 H
Opcode Operand Description DAD Reg. pair Add register pair to H-L pair. The 16-bit contents of the register pair are added to the contents of H-L pair. The result is stored in H-L pair. If the result is larger than 16 bits, then CY is set. No other flags are changed. Example: DAD B
Opcode 6 SUB Operand Description R Subtract register or memory to accumulator M The contents of the register or memory location are subtracted from the contents of the accumulator. The result is stored in accumulator. If the operand is memory location, its address is specified by H-L pair. All flags are modified to reflect the result of subtraction. Example: SUB B or SUB M
Opcode 7 SBB
Operand Description R Subtract register or memory from M accumulator with borrow The contents of the register or memory location and Borrow Flag (i.e.CY) are subtracted from the contents of the accumulator. The result is stored in accumulator. If the operand is memory location, its address is specified by H-L pair. All flags are modified to reflect the result of subtraction. Example: SBB B or SBB M
Opcode 8 SUI Operand 8-bit data Description Subtract immediate from accumulator
The 8-bit data is subtracted from the contents of the accumulator. The result is stored in accumulator. All flags are modified to reflect the result of subtraction. Example: SUI 45 H
Opcode 9 SBI
Operand 8-bit data
Description Subtract immediate from accumulator with borrow
The 8-bit data and the Borrow Flag (i.e. CY) is subtracted from the contents of the accumulator. The result is stored in accumulator. All flags are modified to reflect the result of subtraction. Example: SBI 45 H
Opcode 10 INR
Operand Description R Increment register or memory by 1 M The contents of register or memory location are incremented by 1. The result is stored in the same place. If the operand is a memory location, its address is specified by the contents of H-L pair. Example: INR B or INR M
11
Opcode INX
Operand R
Description Increment register pair by 1
The contents of register pair are incremented by 1. The result is stored in the same place. Example: INX H Operand Description 12 R Decrement register or memory by 1 M The contents of register or memory location are decremented by 1. The result is stored in the same place. If the operand is a memory location, its address is specified by the contents of H-L pair. Example: DCR B or DCR M Opcode DCR
Opcode Operand Description 13 DCX R Decrement register pair by 1 The contents of register pair are decremented by 1. The result is stored in the same place. IFETCE/IT/II Year/ IV Example: DCX H
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Logical Instructions
These instructions perform logical operations on data stored in registers, memory and status flags. The logical operations are: AND OR XOR Rotate Compare Complement
AND, OR, XOR

Any 8-bit data, or the contents of register, or memory location can logically have AND operation OR operation XOR operation with the contents of accumulator. The result is stored in accumulator Rotate Each bit in the accumulator can be shifted either left or right to the next position.
Compare
Any 8-bit data, or the contents of register, or memory location can be compares for: Equality Greater Than Less Than with the contents of accumulator. The result is reflected in status flags.
Complement
The contents of accumulator can be complemented. Each 0 is replaced by 1 and each 1 is replaced by 0
Opcode CMP
Operand Description R Compare register or memory M with accumulator The contents of the operand (register or memory) are compared with the contents of the accumulator. Both contents are preserved . The result of the comparison is shown by setting the flags of the PSW as follows:
if (A) < (reg/mem): carry flag is set if (A) = (reg/mem): zero flag is set if (A) > (reg/mem): carry and zero flags are reset. Example: CMP B or CMP M Opcode Operand Description 2 CPI 8-bit data Compare immediate with accumulator The 8-bit data is compared with the contents of accumulator.
The values being compared remain unchanged. The result of the comparison is shown by setting the flags of the PSW as follows: if (A) < data: carry flag is set if (A) = data: zero flag is set if (A) > data: carry and zero flags are reset Example: CPI 89H Opcode ANA Operand R M Description Logical AND register or memory with accumulator
The contents of the accumulator are logically ANDed with the contents of register or memory. The result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of H-L pair. S, Z, P are modified to reflect the result of the operation. CY is reset and AC is set. 64 Example: ANA B or ANAIFETCE/IT/II Year/ IV M.
Opcode 4 ANI
Operand Description 8-bit data logical AND immediate with accumulator
The contents of the accumulator are logically ANDed with the 8-bit data. The result is placed in the accumulator. S, Z, P are modified to reflect the result. CY is reset, AC is set. Example: ANI 86H Opcode 5 ORA Operand Description R Logical OR register or memory M with accumulator The contents of the accumulator are logically ORed with the contents of the register or memory. The result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of H-L pair. S, Z, P are modified to reflect the result. CY and AC are reset. Example: ORA B or ORA M. IFETCE/IT/II Year/ IV 65
Opcode 6 ORI
Operand 8-bit data
Description logical OR immediate with accumulator
The contents of the accumulator are logically ORed with the 8-bit data. The result is placed in the accumulator. S, Z, P are modified to reflect the result. CY and AC are reset. Example: ORI 86H. Opcode 7 XRA Operand Description R Logical XOR register or memory M with accumulator The contents of the accumulator are XORed with the contents of the register or memory. The result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of H-L pair. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. IFETCE/IT/II 66 Example: XRA B or XRA M. Year/ IV
Opcode Operand Description 8 XRI 8-bit data XOR immediate with accumulator The contents of the accumulator are XORed with the 8-bit data. The result is placed in the accumulator. S, Z, P are modified to reflect the result. CY and AC are reset. Example: XRI 86H. Opcode 9 RLC Operand NONE Description Rotate accumulator Left
Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the position of D0 as well as in the Carry flag. CY is modified according to bit D7. S, Z, P, AC are not affected. Example: RLC.
10
Opcode RRC
Operand NONE
Description Rotate accumulator Right
Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the position of D7 as well as in the Carry flag. CY is modified according to bit D0. S, Z, P, AC are not affected. Example: RRC. Opcode Operand Description 11 RAL NONE Rotate accumulator Left through Carry Each binary bit of the accumulator is rotated left by one position through the Carry flag. Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least significant position D0. CY is modified according to bit D7. S, Z, P, AC are not affected. Example: RAL.
Opcode Operand Description 12 RAR NONE Rotate accumulator Right through Carry Each binary bit of the accumulator is rotated right by one position through the Carry flag. Bit D0 is placed in the Carry flag, and the Carry flag is placed in the most significant position D7. CY is modified according to bit D0. S, Z, P, AC are not affected. Example: RAR. Opcode Operand Description 13 CMA NONE Complement accumulator
The contents of the accumulator are complemented. No flags are affected. Example: CMA.
14
Opcode CMC
Operand NONE
Description Complement Carry
The Carry flag is complemented. No other flags are affected. Example: CMC. Opcode STC Operand NONE Description Set Carry
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The Carry flag is set to 1. No other flags are affected. Example: STC.
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Branching Instructions
The branching instruction alter the normal sequential flow. These instructions alter either unconditionally or conditionally
1 Opcode JMP Operand 16-bit Address Description Jump Unconditionally
The program sequence is transferred to the memory location specified by the 16-bit address given in the operand. Example: JMP 2034IFETCE/IT/II Year/ IV H.
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Jump conditionally
JNZ JZ JNC JC JPO JPE JP JM Not Zero (Z = Zero (Z = 1) No Carry (C = Carry (C = 1) Parity Odd (P Parity Even (P Plus (S = 0) Minus (S = 1) 0) 0)
= 0) = 1)
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Stack I/O, and Machine Control Instructions:

The following instructions affect the Stack and/or Stack Pointer: PUSH POP XTHL SPHL Push Two bytes of Data onto the Stack Pop Two Bytes of Data off the Stack Exchange Top of Stack with H & L Move content of H & L to Stack Pointer
73
The I/0 instructions are as follows:

IN OUT Initiate Input Operation Initiate Output Operation
74
The Machine Control instructions are as follows: EI Enable Interrupt System DI Disable Interrupt System HLT Halt NOP No Operation SIM Set Interrupt Mask RIM Read Interrupt Mask
75
SIM instruction Format
76
RIM instruction Format
77
8085 Programming Model
Programming Registers
Flow Chart 8085 Mnemonics
Manual Lookup Hex Code
Monitor Program Binary Code
To memory for Storage
79
Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in a graphical format. The execution time is represented in T-states.
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Instruction Cycle: The time required to execute an instruction is called instruction cycle.
Machine Cycle: The time required to access the memory or input/output devices is called machine cycle.
T-State: The machine cycle and instruction cycle takes multiple clock periods. A portion of an operation carried out in one system clock period is called as T-state.
MACHINE CYCLES OF 8085:

The 8085 microprocessor has 5 (seven) basic machine cycles. They are
Opcode fetch cycle (4T) Memory read cycle (3 T) Memory write cycle (3 T) I/O read cycle (3 T) I/O write cycle (3 T)
Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when the 8085 processor executes an instruction, it will execute some of the machine cycles in a specific order.
Timing diagram for STA 526AH.
84
Timing diagram for IN C0H
85
Timing diagram for MVI B, 43H.
86
Sample Program
Add two 8-bit numbers Sample problem
(4000H) = 14H (4001H) = 89H Result = 14H + 89H = 9DH

Source program LXI H 4000H MOV A, M INX H ADD M INX H MOV M, A HLT : HL points 4000H : Get first operand : HL points 4001H : Add second operand : HL points 4002H : Store result at 4002H :Terminate program execution
87
Add two 16-bit numbers

Sample problem: (4000H) = 15H (4001H) = 1CH (4002H) = B7H (4003H) = 5AH Result = 1C15 + 5AB7H = 76CCH (4004H) = CCH (4005H) = 76H
Sample Program
Source Program 1: LHLD 4000H : Get first I6-bit number in HL XCHG : Save first I6-bit number in DE LHLD 4002H : Get second I6-bit number in HL MOV A, E : Get lower byte of the first number ADD L : Add lower byte of the second number MOV L, A : Store result in L register MOV A, D : Get higher byte of the first number ADC H : Add higher byte of the second number with carry MOV H, A : Store result in H register SHLD 4004H : Store I6-bit result in memory locations 4004H and 4005H. HLT : Terminate program execution
88
Multiply two 8-bit numbers

Sample problem 1: (2200H) = 03H (2201H) = B2H Result = B2H + B2H + B2H = 216H (2300H) = 16H (2301H) = 02H
Source program : LDA 2200H MOV E, A MVI D, 00 : Get the first number in DE register pair LDA 2201H MOV C, A : Initialize counter LX I H, 0000 H : Result = 0 DAD D : Result = result + first number DCR C : Decrement count JNZ BACK : If count 0 repeat SHLD 2300H : Store result HLT : Terminate program
Sample Program
BACK:
89 IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

Introduction To 8085 Architecture and Programming: Ifetce/It/Ii Year/ Iv Sem/IT141402/MPMC/ Ver 1.0 1

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Introduction To 8085 Architecture and Programming: Ifetce/It/Ii Year/ Iv Sem/IT141402/MPMC/ Ver 1.0 1

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Introduction to 8085 Architecture and Programming

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

IFETCE/IT/II Year/ IV Signals and I/O Pins Sem/IT141402/MPMC/ Ver 1.0

The 8085 Microprocessor Architecture

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

Intel 8085 CPU (Architecture)Block Diagram

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

Segme nt CS Status and Control Flags IP SS DS ES

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

Flag Register of 8085

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

Signal Flow in 8085

15 IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

1K Byte Memory Chip

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

8085 supports two types of interrupts.

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

The Table shows the vector addresses of all interrupts.

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

Hardware interrupts Cont..

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

How SIM Interprets the Accumulator

Serial Data Out

Enable Serial Data 0 - Ignore bit 7 1 - Send bit 7 to SOD pin

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

RIM sets the Accumulators different bits

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

RST 6.5 and 5.5:

1.DI, SIM instruction 2.System or processor reset. 3.After reorganization of interrupt.

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

1.3 INSTRUCTION SET

Data Transfer Instructions

Three-word or 3-byte instructions

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

8085 Instruction Set

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

8085 Instruction Types

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

8085 Instruction Types

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

8085 Instruction Types

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

(set carry flag)

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

Instruction Set of 8085

8085 has 246 instructions.

Classification of Instruction Set

Data Transfer Instructions

IFETCE/IT/II Year/ IV Sem/IT141402/MPMC/ Ver 1.0

Operand Rd, Rs M, Rs Rd, M

Description Copy from source to destination.

The contents of the source register are not altered.