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Digital Integrated Circuits

A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic

Designing Sequential Logic Circuits


November 2002
Digital Integrated Circuits2nd Sequential Circuits

Sequential Logic
Inputs COMBINATIONAL LOGIC Current State Registers Q D Next state Outputs

CLK

2 storage mechanisms positive feedback charge-based


Digital Integrated Circuits2nd Sequential Circuits

Naming Conventions
In our text:
 a latch is level sensitive  a register is edge-triggered

There are many different naming conventions


 For instance, many books call edgetriggered elements flip-flops  This leads to confusion however

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Sequential Circuits

Latch versus Register


Latch stores data when clock is low
D Q Clk Clk D Q
Digital Integrated Circuits2nd

Register stores data when clock rises


D Q Clk Clk D Q
Sequential Circuits

Latches
Positive Latch In D G CLK clk In Out Out stable Out follows In clk In Out Out stable Out follows In Q Out In Negative Latch D G CLK Q Out

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Sequential Circuits

LatchLatch-Based Design
N latch is transparent when J = 0
J

P latch is transparent when J = 1

N Latch

Logic

P Latch

Logic
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Sequential Circuits

Timing Definitions

CLK t tsu D thold Register D Q

DATA STABLE tc 2
q

CLK t

DATA STABLE

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Sequential Circuits

Characterizing Timing
tD 2 D Q D
Q

Clk

Clk

tC 2

tC 2

Register
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Latch
Sequential Circuits

Maximum Clock Frequency


J FFs LOGIC tp,comb

Also: tcdreg + tcdlogic > thold tcd: contamination delay = minimum delay

tclk-Q + tp,comb + tsetup = T

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Sequential Circuits

Positive Feedback: Bi-Stability BiVi 1 V o1 = V i 2 V o2

V o1

1 o V

Vi2

1 o V 5 2 i V
V o2

V o2 = V i 1

V i1 A V i 2 = V o1 1

o V 5 2 i V

B V i 1 = V o2

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Sequential Circuits

MetaMeta-Stability
V i 2 5 V o1 V i 2 5 V o1 C A A

V i 1 5 V o2

V i 1 5 V o2

Gain should be larger than 1 in the transition region

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Sequential Circuits

Writing into a Static Latch


Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
CLK

CLK
Q CLK

D CLK

CLK

Converting into a MUX

Forcing the state (can implement as NMOS-only)

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Sequential Circuits

MuxMux-Based Latches
Negative latch Positive latch (transparent when CLK= 0) (transparent when CLK= 1)

1 D 0

Q D

0 1

CLK

CLK

Q ! Clk Q  Clk In
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Q ! Clk Q  Clk In
Sequential Circuits

MuxMux-Based Latch
CLK

Q CLK D

CLK

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Sequential Circuits

MuxMux-Based Latch

CLK QM QM CLK CLK

CLK

NMOS only
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Non-overlapping clocks
Sequential Circuits

MasterMaster-Slave (Edge-Triggered) (EdgeRegister


Slave Master 0 1 D 0 QM 1 CLK Q D QM Q CLK CLK

Two opposite latches trigger on edge Also called master-slave latch pair
Digital Integrated Circuits2nd Sequential Circuits

MasterMaster-Slave Register
Multiplexer-based latch pair

I2

T2

I3 QM

I5

T4

I6

I1

T1

I4

T3

CLK

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Sequential Circuits

ClkClk-Q Delay
2.5

CLK
Volts 1.5 D

tc 2

q(lh)

0.5

tc 2

q(hl)

2 0.5 0

0.5

1 1.5 time, nsec

2.5

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Sequential Circuits

Setup Time
3.0 2.5 2.0 Volts 1.5 D 1.0 0.5 0.0 2 0.5 0 0.2 0.4 0.6 time (nsec) 0.8 1 I 2 2 T2 CLK Q QM Volts 3.0 2.5 2.0 1.5 D 1.0 QM 0.5 0.0 2 0.5 0 0.2 0.4 0.6 time (nsec) 0.8 1 CLK I 2 2 T2 Q

(a) Tsetup 5 0.21 nsec

(b) T setup 5 0.20 nsec

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Sequential Circuits

Reduced Clock Load MasterMaster-Slave Register


CLK CLK

T1 CLK

I1 I2

T2 CLK

I3 I4

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Sequential Circuits

Avoiding Clock Overlap


CLK A B X CLK Q D

CLK (a) Schematic diagram

CLK

CLK

CLK (b) Overlapping clock pairs

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Sequential Circuits

Overpowering the Feedback Loop CrossCross-Coupled Pairs


NOR-based set-reset
S S Q S R R Q Q Q 0 1 0 1 Forbidden State 0 0 1 1 Q 1 0 0 Q 0 1 0 R Q Q

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Sequential Circuits

CrossCross-Coupled NAND
Cross-coupled NANDs
S

Added clock
VDD M2 Q M4 Q

CLK

M6

M1

M3

M8

CLK

M5

M7

This is not used in datapaths any more, but is a basic building memory cell
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Sizing Issues
2.0 3 Q 1.5 Q (Volts) 2 1.0 Volts S W = 0.5 Q m W = 0.6 Q m W = 0.7 Q m 1 0.5 W = 1Q m 0.0 2.0 2.5 3.0 W/L 5 and 6 (a) 3.5 4.0 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time (ns) (b) W = 0.8 Q m W = 0.9 Q m

Output voltage dependence on transistor width


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Transient response

Sequential Circuits

Storage Mechanisms
Static Dynamic (charge-based)
CLK
CLK

Q CLK

CLK
D

CLK

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Sequential Circuits

Making a Dynamic Latch Pseudo-Static PseudoCLK

CLK

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Sequential Circuits

More Precise Setup Time


Clk t D t Q t (a)

1.05tC 2

tC 2

tSu tH (b)

tD 2

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Sequential Circuits

Setup/Hold Time Illustrations


Circuit before clock arrival (Setup-1 case)
CN
TG1 Inv2

D
Inv1

D1

SM

QM

Clk-Q Delay

CP
TClk-Q TSetup-1

Time

Data TSetup-1
t=0

Clock

Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations


Circuit before clock arrival (Setup-1 case)
CN
TG1 Inv2

D
Inv1

D1

SM

QM

Clk-Q Delay

CP

TClk-Q

TSetup-1

Time

Data TSetup-1
t=0

Clock

Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations


Circuit before clock arrival (Setup-1 case)
CN
TG1 Inv2

D
Inv1

D1

SM

QM

Clk-Q Delay

CP
TClk-Q TSetup-1

Time

Data TSetup-1
t=0

Clock

Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations


Circuit before clock arrival (Setup-1 case)
CN
TG1 Inv2

D
Inv1

D1

SM

QM

Clk-Q Delay

TClk-Q

CP

TSetup-1

Time

Data TSetup-1
t=0

Clock

Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations


Circuit before clock arrival (Setup-1 case)
CN
TG1 Inv2

D
Inv1

D1

SM

QM

Clk-Q Delay TClk-Q

CP

TSetup-1

Time

Data

Clock TSetup-1
t=0 Time

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Sequential Circuits

Setup/Hold Time Illustrations


Hold-1 case
CN
TG1 Inv2
Clk-Q Delay

D
Inv1

D1

SM

QM

CP

0
TClk-Q THold-1

Time

Clock THold-1
t=0

Data

Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations


Hold-1 case
CN
TG1 Inv2
Clk-Q Delay

D
Inv1

D1

SM

QM

CP

0
TClk-Q THold-1

Time

Clock THold-1
t=0

Data

Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations


Hold-1 case
CN
TG1 Inv2
Clk-Q Delay

D
Inv1

D1

SM

QM

CP

0
TClk-Q

THold-1

Time

Clock

Data THold-1
t=0 Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations


Hold-1 case
CN
TG1 Inv2
Clk-Q Delay

D
Inv1

D1

SM

QM

TClk-Q

CP

THold-1

Time

Clock THold-1
t=0

Data

Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations


Hold-1 case
CN
TG1 Inv2
Clk-Q Delay

D
Inv1

D1

SM

QM

TClk-Q

CP

THold-1

Time

Clock

Data THold-1
t=0 Time

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Sequential Circuits

Other Latches/Registers:
VDD M2 VDD M6

2MOS C

CLK D CLK

M4 X M3 CL1

CLK

M8 Q CL2

CLK

M7

M1

M5

Master Stage

Slave Stage

Keepers can be added to make circuit pseudo-static


Digital Integrated Circuits2nd Sequential Circuits

Insensitive to Clock-Overlap ClockVDD M2 0 D M4 X Q D 1 M1 M5 M3 M1 1 M7 M5 0 VDD M6 M8 X Q VDD M2 VDD M6

(a) (0-0) overlap

(b) (1-1) overlap

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Sequential Circuits

Pipelining
REG a
a REG REG REG

REG

REG CLK

CLK REG b

log

Out
b

CLK REG

log

Out

CLK

CLK

CLK

CLK

CLK

Reference

Pipelined

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Sequential Circuits

Other Latches/Registers: TSPC


VDD VDD VDD VDD

Out In CLK CLK In CLK CLK Out

Positive latch Negative latch (transparent when CLK= 1) (transparent when CLK= 0)
Digital Integrated Circuits2nd Sequential Circuits

Including Logic in TSPC


VDD PUN Q In CLK CLK CLK CLK VDD In1 VDD In2 Q VDD

PDN

In1

In2

Example: logic inside the latch


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AND latch
Sequential Circuits

TSPC Register
VDD CLK VDD VDD Q Q CLK M8

M3

M6 Y

M9

CLK

M2

M5

M1

CLK

M4

M7

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Sequential Circuits

PulsePulse-Triggered Latches An Alternative Approach


Ways to design an edge-triggered sequential cell:
Master-Slave Latches L1
Data D Q Clk Clk

Pulse-Triggered Latch L2
D Q Clk Data Clk

L
D Q Clk

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Sequential Circuits

Pulsed Latches
VDD VDD M3 M6 CLK Q D CLKG M2 CLKG M5 MP X CLKG VDD

M1

M4

MN

(a) register

(b) glitch generation

CLK CLKG (c) glitch clock

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Sequential Circuits

Pulsed Latches
Hybrid Latch Flip-flop (HLFF), AMD K-6 and K-7 :
CLK P1 P3 M6 P2 M5 M4

M3 D M2 M1

CLKD

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Sequential Circuits

Hybrid Latch-FF Timing Latch3.0 2.5 2.0 Volts 1.5 1.0 0.5 0.0 20.5 0.0
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CLK

CLKD

0.2

0.4 0.6 time (ns)

0.8

1.0
Sequential Circuits

LatchLatch-Based Pipeline
CLK CLK CLK

In C1

F C2

G C3

Out

CLK CLK

Compute F

compute G

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Sequential Circuits

NonNon-Bistable Sequential Circuits Schmitt Trigger


V ou t
In Ou t

V OH

VTC with hysteresis Restores signal slopes

V OL

VM
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VM +

Vi n

Sequential Circuits

Noise Suppression using Schmitt Trigger


Vin VM Vout

VM

t0

t0 + tp

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Sequential Circuits

CMOS Schmitt Trigger


VDD

M2 Vin X

M4 Vout

M1

M3

Moves switching threshold of the first inverter Digital Integrated Circuits2nd Sequential Circuits

Schmitt Trigger Simulated VTC


2.5 2.0 1.5 VM1 2.5 2.0 1.5

(V) 1.0 X V
0.5 0.0 0.0

VM2

(V) x1.0 V
0.5 0.0 0.0

k=1 k=3 k=2 k=4 0.5 1.0 1.5 Vin (V) 2.0 2.5

0.5

1.0 1.5 Vin (V)

2.0

2.5

Voltage-transfer characteristics with hysteresis.

The effect of varying the ratio of the PMOS device M4. The width is k* 0.5M m.

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Sequential Circuits

CMOS Schmitt Trigger (2)


VDD M4 M6 M3 In M2 X M1 M5 VDD Out

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Sequential Circuits

Multivibrator Circuits
R S Bistable Multivibrator flip-flop, Schmitt Trigger

T Monostable Multivibrator one-shot

Astable Multivibrator oscillator

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Sequential Circuits

TransitionTransition-Triggered Monostable

In

DELAY td

Out td

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Sequential Circuits

Monostable Trigger (RC-based) (RCVD D In R A C B Out (a) Trigger circuit.

In

VM

(b) Waveforms.

Out t1 t2

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Sequential Circuits

Astable Multivibrators (Oscillators)


0 1 2 N-1

Ring Oscillator
3.0 2.5 2.0 Volts 1.5 1.0 0.5 0.0 20.5 0.0 0.5 time (ns) 1.0 1.5 V1 V3 V5

simulated response of 5-stage oscillator

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Sequential Circuits

Relaxation Oscillator
Out1 I1 I2 Out2

R Int

T = 2 (log3) RC
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Sequential Circuits

Voltage Controller Oscillator (VCO)


VD D
M6

VDD
M4

Schmitt Trigger restores signal slopes

M2

In
M1

Iref Vcontr
M3 M5

Iref

Current starved inverter

6 t pH L (nsec) 4 2

0.0 0.5

1.5 V co ntr (V)

2.5

propagation delay as a function of control voltage

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Sequential Circuits

Differential Delay Element and VCO


V o2 in 1 V o1 in 2 v1 v2 v
4

v3

V ctrl

delay cell
3.0 2.5 2.0 1.5 1.0 0.5 0.0 2 0.5 0.5 1.5 time (ns) 2.5 3.5 V1 V2 V3 V4

two stage VCO

simulated waveforms of 2-stage VCO

Digital Integrated Circuits2nd

Sequential Circuits