Sequential Logic Circuits

The timing or sequencing history of the input signals plays a role in determining in the output for sequential logic devices Sequential logic system must have some form of memory The outputs of a sequential logic system must have some form of memory

Examples of sequential logic devices include flip-flops, registers, counters and latches. Flip-Flops  A flip-flop is basically a sequential circuit with a memory where the output is function not only of the present inputs but also of the past circuit states.


The fundamental, most important characteristic of a flip-flop is that it has a memory

S. Kal, IIT-Kharagpur
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FLIP-FLOPS


It has two stable states which are called 1 (High) or 0 (Low). It has two complementary level outputs called Q and Q. When Q is at state 1, Q is at state 0 and vice versa. Enabled / Disabled inputs : For an AND or NAND gate, if one input is 0, the output will be 0 or 1 independent on other inputs, since F = A.B.C F = A.B.C for for AND NAND
Q

One selected input takes control of the gate and the gate is disabled ( inhibit) with respect to any other input. Alternatively, if the selected input is at logic 1, it does not take control, and the gate is enabled to respond to other inputs. Similarly in OR or NOR gate, a selected input takes control and disabled for other inputs, when selected input goes to logic 1.
S. Kal, IIT-Kharagpur 3

SR Flip-Flop Flip-

1. As long as the inputs S and R are both 0, the outputs of the flip-flop remain unchanged 2. When S = 1 and R = 0, the flip-flop is set to Q = 1 and Q = 0. 3. When S = 0 and R = 1, the flip is reset to Q = 0 and Q = 1. 4. It is not used to place S = 1 and R = 1 simultaneously since the output will be unpredictable.
S. Kal, IIT-Kharagpur
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SR Flip-Flop using NOR and NAND gate Flip1. For the input condition, S = 0, R = 0, the output of NOR gates A and B depends on the other inputs. If we assume that initially Q = 0 and Q = 1, then, NOR A will be disabled and its output, Q = 0. Since the output Q is feed to input of NOR B, the output of NOR B(Q) will be 1. Thus, this input condition does not change the state of the flip-flops and the output will remain the same as earlier. 2. When S = 1, R = 0, the output of NOR B is disabled and its output is always 0, i.e. Q = 0 and thus Q = 1 as the inputs of NOR A are both 0 3. When S = 0, R = 1, the output of NOR A will be disabled and its output is always 0, i.e. Q = 0 and thus Q = 1 since the inputs of NOR B are both 0 4. The last input condition in, S = 1 and R = 1, is not used as it forces the output of the NOR gates to the low state, I.e. both Q = Q = 0
S. Kal, IIT-Kharagpur
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Clocked SR Flip-Flop
Edges of positive and negative pulse Symbol of a SR Flipflop, (b)positive edge-triggered and (c) negative edge-triggered
The exact times at which any output can change state is determined by a signal termed clock signal. The clock signal can be periodic square wave or an aperiodic collection of pulses. Flip Flops can be level triggered ( latch) or edge triggered (positive or negative)
S. Kal, IIT-Kharagpur
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Need for clocked FF

Assume R = 0, S = 0 for A = 1, B = 0 Simultaneous change of A, B should not change Q, DQ
  

A change before B change No problem B change before A change, for a moment, A = 1, B = 1, S = 1, @ unintentional change of the output If B changes at a time (t before A changes, S will be in error for only this time (t

Solution:  S and R inputs determine the eventual state of the FF but the exact moment of the response of the FF to these inputs is determined by an auxiliary signal


State transitions can be deferred until all input logic levels established
S. Kal, IIT-Kharagpur
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A Clocked SR Flip-Flop using NAND gates

1. If S = 0 and R = 0, the output state remains unchanged 2. If S = 1 and R = 0, the flip-flop output is set to 1 3. If S = 0 and R = 1, the flip-flop output is reset to 0 4. S and R should never be 1. The words not allowed in the last row indicate that the input condition for that row is not allowed.
S. Kal, IIT-Kharagpur
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RC Clock Edge-triggered Flip-Flop using Preset and Clear Inputs

When Pr = Cr = 1, the output gates are enabled, i.e. neither of these inputs affects the operation of the flip-flop. In case power is switched on initially S = R = 0, the output states may be decided by the preset and clear inputs. If Pr = 0, Cr = 1, then Q = 1. Since the output of N1 connects as input of N2, all the inputs of N2 are 1(R = 0) and the output Q = 0. The flip-flop is in set state. Similarly, Pr = 1, Cr = 0 gives Q = 0, Q = 1, and the flip-flop is in reset state. The flip-flop will be disabled when both Pr and Cr inputs are 0,
S. Kal, IIT-Kharagpur
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Master-Slave SR Flip-Flop
Difficulties of positive Edge-Triggering Digital system generally uses common clock wave from for all the flip-flops in the system. The data inputs of flip-flops may be derived entirely or in part from the outputs of other flip-flops. Because of the finite time clock stay at the enabling level (Ck=1), the flip-flops connected in cascade would response after each successive flip-flop propagation delay so long as Ck remained at Ck=1 Solution: Use of narrow train of positive pulses; (i) The pulse duration will be very short in comparison with the interval between pulses p generating and handling appropriately narrow pulses might well represent the state of the art circuitry. p (ii) Use of too narrow pulses to avoid the timing difficulty described above, cause the problem of triggering the flip-flop reliably
S. Kal, IIT-Kharagpur
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Master-Slave SR Flip-Flop
A better solution would be to use of flip-flops designed so that the triggering transition is from the enabling to the disabling level of the clock, I.e., negative edge-triggered transition

S. Kal, IIT-Kharagpur

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Master-Slave SR Flip-Flop
Master-slave flip-flop is a kind of flip-flop, which responds when the clock makes a transition to the disable level. It uses two individual clocked SR flip-flop one flip-flop is called the master and the other the slave. The Ck is applied to the input gates of the master, but the clock complement DC is applied to the input gates of the slave When Ck goes high, the data at S and R are registered in the master but restrained from passing on to the slave. When the Ck goes low, at which time the input gates (N1, N2) are disabled, the data in the master (QM) are transferred to the slave flip-flop and appear at the output QS and D QS
S. Kal, IIT-Kharagpur

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JK Flip-Flop Flip-

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S. Kal, IIT-Kharagpur

J K Flip Flop


Let J=K=0, both the input gates are disabled and the clock will not change the FF state. Hence Qn+1 = Qn. J=0, K=1, (i) initially FF reset state ie Q = 0, then gate A disabled because J=0, gate B disabled as Q=0. Hence Ck will not move the FF out of the reset state. (ii) J=0, K=1, initially FF in set state, ie Q=1. Then gate A disabled as J=0, but B enabled as Q=1, Ck will cause a transfer of FF to the reset state with Q=0. Thus, J=0, K=1, the Ck will set the FF in the reset state if it is not already in the reset state. Similarly, J=1, K=0, the Ck will set the FF in set state if it is not already in the set state. J=1, K=1, which of the gates A or B is enabled depends entirely on Qn and Qn ie on the state of the FF. If Qn=0, the Ck will set the FF to Qn+1=1. If Qn=1. The Ck will set the FF to Qn+1=0. Thus each cycle of the Ck will change the state of the FF. This is known as toggle mode operation of the FF.
S. Kal, IIT-Kharagpur
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J K Flip Flop
Race Around Problem of J-K Flip-Flop
In a J-K flip flop, when clock = 0, both the input gates are disabled, so the flip-flop does not respond to the J-K inputs and remains in the earlier state. Let, when J = 1, K = 1, Ck = 0, then Q = 0, Q = 1. Now if Ck changes 0 p 1, the gate A is enabled which results in Q = 0 p 1 and hence Q = 1 p 0 Thereafter the gate B is enabled and hence Q = 0p1 and Q = 1p0. Thus the output toggles between the two states continuously so long as Ck =1. This is called race around phenomena
S. Kal, IIT-Kharagpur

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Master Slave JK flip-flop

If the feedback lines A, B are disconnected, it becomes a master-slave S-R with J = S, K = R. When Ck goes 0p1, master is enabled and slave is disabled. Thus the input at J, K is transferred to the output of master, QM and QM, but it cannot be further transmitted, since slave is disabled. When Ck goes back 1p0, master is disabled and the slave is enabled. Slave transfers data from QM, QM to Q, Q. In this case, race around problem is avoided, since as Ck goes 0 p1 with J = K = 1, master toggles, but slave remains inoperative.
S. Kal, IIT-Kharagpur

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MasterMaster-Slave JK Flip-Flop Flip-

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S. Kal, IIT-Kharagpur

D Flip Flop

The The

D flip-flop, also called a data flip-flop, uses a SR flip-flop

logical signal, i.e., the data, is applied to S terminal of an SR flip-flop or J terminal of a JK flip-flop. The complement of the data is then applied to the R or K terminal
In

this type of flip-flop, there is no possibilities of ambiguous state

S. Kal, IIT-Kharagpur
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D Flip Flop
If D=J=0, then K =DD = 1 and the output Q = 0, so the flipflop goes to the reset state. If D=J=1, then K =DD = 0 and the output Q = 1, so the flipflop goes to the set state. truth table of this flip-flop indicates that the input is transferred to the output at the end of the clock pulse. Thus the output after clock pulse equals the input at D before clock pulse
The The

transfer of data from input to output is delayed and this flip-flop is also called delayed flip-flop

the bit on D input is transferred to the output at the next clock pulse, these unit function as a 1-bit delay device and is used as a temporary storage latch
S. Kal, IIT-Kharagpur

As

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Shift Registers


A flip-flop can store or remember or register a single bit and is therefore referred to as a one bit register. If we require that N bits be remembered or registered, N flip-flops are required. When an array of flip-flops has a number of bits in storage, it becomes necessary on occasion to shift bits from one flipflop to another. An array of flip-flops which permits this shifting is called a shift register. There are two methods for shifting binary information into a register. The first involves shifting the information into the register one bit at a time in series fashion and leads to the development of a serial shift register.
S. Kal, IIT-Kharagpur

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Shift Registers


The second method involves shifting all the bits into the register at the same time and leads to the development of a parallel shift register. The size of a register is determined by the size of the number to be stored. In a serial shift register it requires n clock pulses to shift an n-bit number into the register. Two other useful operations which can be performed with the basic shift register are shift right and shift left. A bit shifted out of the last flip-flop is lost. When it is necessary to preserve the bits stored in the register, this can be achieved by coupling the output of the last flip-flop back to the data input of the first flip-flop. In such a register, the bits will circulate around the register, shifting one flip-flop at each clocking. A register so connected is called an end-aroundcarry shift register or ring counter.
S. Kal, IIT-Kharagpur
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Shift Registers

(a) 4-bit serial shift register; (b) D flip-flop from JK flip-flop

S. Kal, IIT-Kharagpur
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Timing Diagram of a 4-bit Shift Registers

S. Kal, IIT-Kharagpur

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Counters


A counter is probably one of the most useful and versatile subsystem in a digital system. It can be used as an instrument for measuring time (and therefore period of frequency) A flip-flop has two states. So an array of N flip-flops has 2N possible states. If the array is interconnected in such a way that the state of the array advances after each cycle of the input waveform (clock), then if after k cycles, the array returns to its initial state, the array is called a counter of modulo k or mod-k counter. Let the states of 3 flip-flops change in the following manner with input clock cycles:

It is a mod - 5 counter.

S. Kal, IIT-Kharagpur
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Counters


If the counter counts all possible states of the array of N flipflops, it is a mod-2N counter.

When the output of one flip-flop drives another, we call the counter a ripple counter: A flip-flop has to change states before it can trigger the B flip-flop; B has to change before it can trigger C; and so forth. The triggers move through the flipflops like a ripple in water. Because of this, the overall propagation delay time is sum of the individual delays and It has a speed limitation. Such type of counters are called serial or asynchronous counter(ripple).
S. Kal, IIT-Kharagpur
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Counters


The ripple counter is simple and straightforward in operation and construction and usually requires a minimum hardware.

Four-bit ( mod-16 ) Ripple Counter

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Counters


The speed limitation of ripple counter can be overcome by the use of a synchronous or parallel counter. The difference here is that every flip-flop is triggered by the common clock. Thus, they all make their transitions simultaneously.

A mode 16 Synchronous Counter

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Ripple Counter (Mod 8)

Active-high decoder circuit for mod-8 counter. All flip-flops are cleared initially, so that Q0 = Q1 = Q2 = 0
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Decoder Truth Table

S. Kal, IIT-Kharagpur

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Propagation Delay of a Logic Gate

S. Kal, IIT-Kharagpur

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