Fundamentals of State Machines

Satish kashyap. B

www.satishkashyap.com

Every finite-state machine, therefore, contains a finite number of memory devices, which store the information regarding the past input history.

General Model for Mealy Circuit Using Clocked D Flip-Flops

General Model for Moore Circuit Using Clocked D Flip-Flops

Mealy vs. Moore Machines

MEALY MACHINE
Outputs depend on current state and present inputs Outputs have immediate reaction to inputs As inputs change, so does next state, doesnt commit until clocking event Tend to have less states Less hardware May not be safer, when interconnecting state machines in asynchronous manner. Delay is less

MOORE MACHINE
Outputs depend on current state only Outputs have no immediate reaction to inputs , they always change one cycle later As inputs change, so does next state, doesnt commit until clocking event

Tend to have more states More logic (hardware) may be necessary to decode state into outputs Moore Machines are safer to use, when two machines are interconnected asynchronous feedback Delay is more

 Recognize Mealy or Moore ?

A D B clock Q Q out

Q Q

out

B clock

Q Q

out A D Q Q B D clock Q
out

Q
A D Q Q B D Q Q clock D D Q Q Q Q

 Recognize Mealy or Moore ?

the output value of the serial adder cannot be specified merely in terms of the external input values

Let A designate the state of the adder at ti if a carry 0 is generated at ti1, and let B designate the state of the adder at ti if a carry 1 is generated at ti1.

Each row of the state table corresponds to a state of the adder, and each column to a particular combination of the external input values x1 and x2. Each entry of the table denotes the state to which a transition is made and the output value associated with this transition.

state diagram (or state graph) alternate to the state table.

Clearly, both the state diagram and state table provide the same information regarding the operation of the adder, and one can be obtained directly from the other.

The state of the delay element is specified by the value of its output y, which may assume either of two values, namely, y = 0 or y = 1. Since the current input value Y of the delay is equal to its next output value, the input value is referred to as the next state of the delay, i.e, Y (t ) = y(t + 1).

y = 0 is assigned to A and y = 1 to B, the value of y at ti will correspond to the value of the carry generated at ti1.

The process of assigning the states of a physical device to the states of the serial adder is known as state assignment. The output value y is referred to as the state variable , to distinguish it from the external primary input variables.

A transition table is derived from a state table by the replacement of each next-state entry with the corresponding state of memory elements.

Design a one-input one-output sequence detector that produces an output value 1 every time the sequence 0101 is detected and an output value 0 at all other times.

State diagram for a sequence (0101) detector.

State diagram for a sequence (0101) detector.

Output and excitation K-maps.

Logic diagram of a sequence detector.

The state assignment employed in Table 9.8 is not the only possible one.

CIRCUIT DIAGRAM .. ?

Schematic diagram of a modulo-8 binary counter with T flip-flops.

Some more Examples

Parity bit generator from ( kohavi ) Parity checker ( Roth ) Analyze different state machine block diagrams to draw their state table or state diagram ( Roth )