Centre for Computer Technology

ICT123 Computer Architecture

Week 12
Router Architecture

Content at a Glance
Review Components of a Router Input / Output ports Switching Fabric Buffer Management HOL blocking

March 20, 2012

Router Components

March 20, 2012

Cisco Networking Academy

Hardware Components of a Router

Input ports terminates an incoming link, performs datalink processing and lookup/forwarding functions Switching fabric a network inside a router, connects input ports to output ports Output ports stores and then transmits datagrams on the outgoing link Routing processor executes routing protocols, maintains routing tables, and performs network management functions
March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Hardware Components of a Router

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Input ports

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Input ports
Line termination and data link processing implement physical and data link layer functions Lookup/forwarding module central to the forwarding function of the router Router determines the output port to which a packet is forwarded

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Input ports
Forwarding table is computed by the routing processor Shadow copy of the table is stored at the input port that allows forwarding decisions to be made locally at each port decentralized forwarding avoids a bottleneck

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Switching Fabric
Heart of the router Packets are switched from input ports to output ports Three techniques

Switching via memory Switching via a bus Switching via an interconnection network

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Switching Fabric - Memory

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Switching Fabric - Memory

An interrupt signals the arrival of a packet on a port Packet is then copied from input port to processor memory Processor extracts the destination address from the header Finds output port in the forwarding table and places packet in the output port buffer

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Switching Fabric - Memory

Modern computers act as shared memory multi-processors Lookup of destination and the storing of the packet in the appropriate memory location is performed by the processors on input line cards

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Switching Fabric - Bus

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Switching Fabric - Bus

Input port transfers a packet directly to the output port over a shared bus, without intervention by a routing processor Only one packet at a time can be transferred as the bus is shared Packets are queued at the input port if they arrive when the bus is busy Bandwidth of router is limited by bus speed
March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Switching Fabric - Crossbar

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Switching Fabric - Crossbar

Switching via an interconnection scheme Network consists of 2n buses to connect n input ports to n output ports Packets arriving at an input port travel along the horizontal bus until it intersects with the vertical bus that leads to the desired output port Packets are queued at the input port when the output port is busy
March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Output ports

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Output ports

Datagram's stored in output port's memory are transmitted over the outgoing link Data link processing and Line termination implement data link and physical layer functions that interact with the input port on the other end of the outgoing link Queuing (Buffer Management) function is needed when packets are delivered to the output port at a higher rate than the output link rate
March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Queuing (Buffer Management)

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Queuing (Buffer Management)

There will be no queuing at the input ports if the switching fabric speed is at least n times as fast as the input line speed At the output port, in the worst case, the packets arriving at each of the n input ports will be destined to the same output port

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Queuing (Buffer Management)

Output port can only send one packet at a time, so n arriving packets have to queue (wait) for transmission over the outgoing link When the buffer (memory) is full at the output ports, packets are dropped

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Queuing (Buffer Management)

A packet scheduler at the output port, selects one packet from the queue for transmission Selection is done based on first-comefirst-served (FCFS) scheduling, or weighted fair queuing (WFQ) Packet scheduling provides quality of service guarantees

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

HOL blocking

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

HOL blocking
Head-of-the-line (HOL) blocking - a queued packet in an input queue must wait for transfer through the fabric (even though its output port is free) due to the blocking of another packet at the head-of-the-line Leads to significant packet loss when the input links reach 58% of capacity

March 20, 2012

http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapter4/4-6.htm

Summary

March 20, 2012

The main components of a router include input/output ports, switching fabric and the routing processor Buffer Management is needed when packets reach the output port at a higher rate than the link rate HOL blocking causes a queued packet to wait for transfer due to the blocking of another packet at the head-of-the-line

References

Cisco Router Architecture, Session 601, Cisco Systems http://www3.gdin.edu.cn/jpkc/dzxnw/jsjkj/chapt er4/4-6.htm

March 20, 2012