8086/8088 Microprocessor

Introduction to the processor and its pin configuration

Topics
Basic Features Pinout Diagram Minimum and Maximum modes Description of the pins

Basic Features
8086 announced in 1978; 8086 is a 16 bit microprocessor with a 16 bit data bus 8088 announced in 1979; 8088 is a 16 bit microprocessor with an 8 bit data bus Both manufactured using High-performance Metal Oxide Semiconductor (HMOS) technology Both contain about 29000 transistors Both are packaged in 40 pin dual-in-line package (DIP)

8086/8088 Pinout Diagrams

GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

8086

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET

GND A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

8088

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

VCC A15 A16/S3 A17/S4 A18/S5 A19/S6 SS0 MN/MX RD HOLD HLDA WR IO/M DT/R DEN ALE INTA TEST READY RESET

BHE has no meaning on the 8088 and has been eliminated

Multiplex of Data and Address Lines in 8088

Address lines A0-A7 and Data lines D0-D7 are multiplexed in 8088. These lines are labelled as AD0-AD7.
By multiplexed we mean that the same pysical pin carries an address bit at one time and the data bit another time
GND A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC A15 A16/S3 A17/S4 A18/S5 A19/S6 SS0 MN/MX RD HOLD HLDA WR IO/M DT/R DEN ALE INTA TEST READY RESET

8088

Multiplex of Data and Address Lines in 8086

Address lines A0-A15 and Data lines D0-D15 are multiplexed in 8086. These lines are labelled as AD0-AD15.
GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET

8086

Minimum-mode and Maximum-mode Systems

8088 and 8086 microprocessors can be configured to work in either of the two modes: the minimum mode and the maximum mode Minimum mode:
Pull MN/MX to logic 1 Typically smaller systems and contains a single microprocessor Cheaper since all control signals for memory and I/O are generated by the microprocessor.
GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET

8086

Maximum mode
Pull MN/MX logic 0 Larger systems with more than one processor (designed to be used when a coprocessor (8087) exists in the system)

Lost Signals in Max Mode

Minimum-mode and Maximum-mode Signals

GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD RQ/GT0 RQ/GT1 LOCK S2 S1 S0 QS0 QS1 TEST READY RESET

8086

Vcc

8086

GND

Min Mode

Max Mode

8086 System Minimum mode

PCLK

+5V RES
Clock generator
AEN2 AEN1 F/C

CLK READY RESET

M/IO INTA RD WR MN/MX +5V

Control Bus

Wait-State Generator

ALE

STB OE

A0 - A19 Address Bus

8086 CPU

AD0-AD15 A16-A19 BHE

8282 Latch

BHE

D0 - D15 8286 DT/R DEN T OE 16

8086 System Maximum Mode

+5V
CLK Clock generator MN/MX S0 S1 S2 Gnd S0 S1 S2 CLK MRDC MWTC AMWC IORC IOWC AIOWC INTA

RESET DEN DT/R

Wait-State Generator

ALE

8086 CPU

STB OE

8288 Bus Controller

RES

READY

A0 - A19 Address Bus BHE

AD0-AD15 A16-A19

8282 Latch

T OE
8286 Transceiver

DATA

Description of the Pins

GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

8086

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET

Vcc

GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

8086

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD RQ/GT0 RQ/GT1 LOCK S2 S1 S0 QS0 QS1 TEST READY RESET

GND

Min Mode

Max Mode

RESET Operation results

CPU component Contents

Flags Instruction Pointer CS DS, SS and ES Queue

Cleared 0000H FFFFH 0000H Empty

AD0 - AD15: Address Data Bus

Data AD0 AD15 Address

A17/S4, A16/S3 Address/Status

A17/S4 A16/S3

Function
Extra segment access
Stack segment access Code segment access

0
0 1

0
1 0

Data segment access

A19/S6, A18/S5 Address/Status

A18/S5: The status of the
interrupt enable flag bit is updated at the beginning of each cycle. The status of the flag is indicated through this pin

A19/S6: When Low, it indicates that 8086 is in

control of the bus. During a "Hold acknowledge" clock period, the 8086 tri-states the S6 pin and thus allows another bus master to take control of the status bus.

S0, S1 and S2 Signals

S2 S1 S0

0
0 0

0
0 1

0
1 0

Characteristics Interrupt acknowledge Read I/O port Write I/O port

0
1 1 1 1

1
0 0 1 1

1
0 1 0 1

Halt
Code access Read memory Write memory Passive State

QS1 and QS2 Signals

QS1 0 0 1 1

QS1 0 1 0 1

Characteristics No operation First byte of opcode from queue Empty the queue Subsequent byte from queue

Read Write Control Signals

IO/M DT/R SSO 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CHARACTERISTICS Code Access Read Memory Write Memory Passive Interrupt Acknowledge Read I/O port Write I/O port Halt

8086 Memory Addressing

Data can be accessed from the memory in four different ways:

8 - bit data from Lower (Even) address Bank.

8 - bit data from Higher (Odd) address Bank. 16 - bit data starting from Even Address. 16 - bit data starting from Odd Address.

Treating Even and Odd Addresses

Higher Address Bank (512K x 8) ODD A1-A19 Address Bus Data Bus (D0 - D15)

BHE

Lower Address Bank (512K x 8) EVEN D0-D7

A0

D8-D15

8-bit data from Even address Bank

Odd Bank Even Bank

x+1 x+3 x+5

x x+2 x+4

BHE = 1 A1-A19 D8-D15 D0-D7

A0 = 0

D0-D15

MOV SI,4000H MOV AL,[SI]

8-bit Data from Odd Address Bank

Odd Bank Even Bank

x+1 x+3

x x+2

BHE =0 A1-A19 D0-D7 D8-D15 D0-D15

A0 = 1

MOV SI,4001H MOV AL,[SI]

16-bit Data Access starting from Even Address

Odd Bank Even Bank

x+1 x+3

x x+2

A1-A19

D8-D15

BHE =0 D0-D7

A0 = 0

D0-D15

MOV SI,4000H MOV AX,[SI]

16-bit Data Access starting from Odd Address

Odd Bank Even Bank Odd Bank Even Bank

0005 0007 0009

0004 0006 0008

0005 0007 0009

0004 0006 0008

A1-A19 A1-A9 D0-D7 D8-D15

A1-A19 A1-A9 D8-D15 D0-D7

(a) First Access from Odd Address

(b) Next Access from Even Address

MOV SI,4001H MOV AX,[SI]

Read Timing Diagram

T1 CLK T2 T3 Twait T4 AD0-AD15 BHE

ALE

S2-S0

M/IO RD

READY DT/R DEN WR

Write Machine Cycle

INTR (input)
Hardware Interrupt Request Pin
INTR is used to request a hardware interrupt. It is recognized by the processor only when IF = 1, otherwise it is ignored (STI instruction sets this flag bit). The request on this line can be disabled (or masked) by making IF = 0 (use instruction CLI) If INTR becomes high and IF = 1, the 8086 enters an interrupt acknowledge cycle (INTA becomes active) after the current instruction has completed execution.

For Discussion
If I/O peripheral wants to interrupt the processor, the interrupt controller will send high pulse to the 8086 INTR pin.

What about if a simple system to be built and hardware interrupts are not needed; What to do with INTR and INTA?

NMI (input) Non-Maskable Interrupt line

The Non Maskable Interrupt input is similar to INTR except that the NMI interrupt does not check to see if the IF flag bit is at logic 1. This interrupt cannot be masked (or disabled) and no acknowledgment is required. It should be reserved for catastrophic events such as power failure or memory errors.

8086 External Interrupt Connections

NMI - Non-Maskable Interrupt INTR - Interrupt Request

NMI Requesting Device

Programmable Interrupt Controller (part of chipset)

NMI

8086 CPU
INTR

Intel 8259A PIC

Interrupt Logic

int

into

Divide Error

Single Step

Software

Traps

TEST (input)
The TEST pin is an input that is tested by the WAIT instruction. If TEST is at logic 0, the WAIT instruction functions as a NOP. If TEST is at logic 1, then the WAIT instruction causes the 8086 to idle, until TEST input becomes a logic 0. This pin is normally driven by the 8087 coprocessor (numeric coprocessor) . This prevents the CPU from accessing a memory result before the NDP has finished its calculation

Ready (input)
This input is used to insert wait states into processor Bus Cycle. If the READY pin is placed at a logic 0 level, the microprocessor enters into wait states and remains idle. If the READY pin is placed at a logic 1 level, it has no effect on the operation of the processor. It is sampled at the end of the T2 clock pulse Usually driven by a slow memory device

8284 Connected to 8086 Mp

X1 X2 F/C RDY1 RDY2 +5V RESET KEY R AEN1 AEN2 Ready 8086 Microprocessor CLK

8284
Reset

RES C

HOLD (input)
The HOLD input is used by DMA controller to request a Direct Memory Access (DMA) operation. If the HOLD signal is at logic 1, the microprocessor places its address, data and control bus at the high impedance state. If the HOLD pin is at logic 0, the microprocessor works normally.

HLDA (output) Hold Acknowledge Output

Hold acknowledge is made high to indicate to the DMA controller that the processor has entered hold state and it can take control over the system bus for DMA operation.

DMA Operation