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Khurram Kazi* Lecture 10 Thanks to Automation press THE button outcomes the Chip !!! Reality or Myth
(*Mostly extracted from Synopsys PrimeTime manuals) Kazi ECE 6811
Features of Primetime
PrimeTime is a full-chip, gate-level static timing analysis tool targeted for complex, multimillion-gate designs. It is used for Static timing analysis for the pre and post layout gate level netlist. During the pre-layout, it uses the wire load models specified in the library to estimate the net delays. Any violations found during the pre-layout static timing analysis should be fixed (either resynthesizing or RTL recoding) prior to moving ahead for placement and routing. Place and route produces a chip layout database from which accurate delay information or detailed parasitic information can be extracted. This data, when back-annotated on the design in PrimeTime, results in a layout-accurate timing analysis. A successful validation of the circuit timing at this point leads to signoff of the completed design.
The diagram only shows the steps related to timing analysis in the physical synthesis flow. It does not include unrelated steps such as formal verification, scan synthesis, and logic simulation.
Command Interface
PrimeTime offers two command environments for timing analysis: pt_shell Graphical user interface (GUI).
pt_shell window
pt_shell interface
The pt_shell interface is the command environment used most often by experienced PrimeTime users. It is a text-only environment in which you enter commands at a prompt (pt_shell> ) and view responses and reports in text form. The pt_shell interface is based on the Tcl scripting language, which means that you can use Tcl features such as procedures, lists, and array processing functions. Routine tasks are typically done by executing scripts or procedures prepared beforehand.
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GUI window
GUI
The GUI offers some visual analysis capabilities that are not available in pt_shell. For example, you can view schematics of the design, display clock waveforms, and generate histograms of analysis results such as path slack, net capacitance, and bottleneck cost. The console window within the top-level window lets you enter commands and view the text response, just like pt_shell.
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Timing paths
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PrimeTime uses the longest path to calculate a maximum delay or the shortest path to calculate a minimum delay.
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Delay calculations
Once the paths are identifies, PT, calculates the delays. The total delay of a path is the sum of all cell and net delays in the path. It estimates delays if the analysis is being performed prior to layout using wire load models After layout, an external tool can accurately determine the delays and write them to a Standard Delay Format (SDF) file. PrimeTime can read the SDF file and back-annotate the design with the delay information for layout-accurate timing analysis. PrimeTime can also accept a detailed description of parasitic capacitors and resistors in the interconnection network, and then accurately calculate net delays based on that information.
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Constraints Checking
Once the path delays are calculated, PT, checks the delays against the constraints provided to it. For example it check the setup or hold timing violations. The amount of time by which a violation is avoided is called the slack. For example, for a setup constraint, if a signal must reach a cell input at no later than 8 ns and is determined to arrive at 5 ns, the slack is 3 ns. A slack of 0 means that the constraint is just barely satisfied. A negative slack indicates a timing violation.
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To run PT
To run in GUI mode type:
(you may want to set an alias for this locally)
/opt/synopsys/pt_vT-2002.09/sparc64/syn/bin/primetime
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A Sample PT script
set search_path {~kkazi/synopsys_examples/db} set link_path {*/opt/synopsys/syn/libraries/syn/lsi_10k.db} read_db ~kkazi/synopsys_examples/db/REG_FILE.db #link design check_timing set_operating_conditions WCCOM create_clock -name "Clk" -period 10 -waveform { { "Clk" } "0" "5" }\ report_clock skew report_port -input_delay
report_port -output_delay
check_timing set_wire_load_model -name 20x20 # Writing timing reports with different options to #different files report_timing -to [all_registers -data_pins] > pt1.rpt report_timing -to [all_outputs] > pt2.rpt #Writing the SDF file write_sdf REG_FILE.sdf
# The clock latency value of 2.5 ns specifies that the clock delay
# from the input port Clk to all the endpoints is fixed at 2.5 ns set_clock_latency 2.5 [get_clocks Clk] set_clock_transition 0.2 [get_clocks Clk] # Clock skew is approximated with 1.2 ns specified for set-up time set_clock_uncertainty 1.2 -setup [get_clocks Clk] # Clock skew is approximated with 0.5 ns specified for hold time set_clock_uncertainty 0.5 -hold [get_clocks Clk] #set_input_delay 2.0 -clock CLK [all_inputs] #set_output_delay 1.0 -clock CLK [all_outputs] set_load 50.0 [all_outputs]
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Mini Assignment
Choose the final synthesis results of the FIFO and perform PrimeTime analysis. Write a small paragraph about the similarities or differences in the two results (i.e. DC analysis and PrimeTime analysis).
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