ONCE AROUND THE 8051 PINS

ONCE AROUND THE 8051 PINS

Salient Features
Compatible with MCS-51 Products 4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-level Program Memory Lock 128 x 8-bit Internal RAM 32 Programmable I/O Lines Two 16-bit Timer/Counters Six Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down Modes

THE I/0 PORTS

Port 0: Dual-purpose port on pins 32-39. With internal
memory, it is used as a general purpose I/O port. With external memory, it serves as the multiplexed address (low byte) and data bus. Port 0 also receives the code bytes during programming the internal code memory, and outputs the code during program verification.

Port 1: Dedicated I/O port on pins 1-8. No alternate

functions are assigned for port 1 pins. Pins are available for interfacing to external devices as required. Port 1 also receives
the low-order address byte during programming and program verification of the internal code memory.

THE I/0 PORTS

Port 2: Dual purpose port on pins 21-28. With internal memory
it acts as a general purpose I/O port. With external memory, it serves as the high byte of the address bus. Port 2 also receives the high-order address byte during programming and program verification of the internal code memory.

Port 3: Dual purpose port on pins 10-17. As well as general

purpose I/O, all pins are assigned alternate functions related to special features of the 51 microcontroller.

ALTERNATE FUNCTIONS OF PORT 3 PINS

BIT P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 NAME RXD TXD INT0 INT1 T0 T1 ALTERNATE FUNCTION Receive data (serial port) Transmit data (serial port) External interrupt 0 External interrupt 1 Timer/counter 0 external input Timer/counter 1 external input

P3.6
P3.7

WR
RD

External data memory write strobe

External data memory read strobe

CONTROL PINS
PSEN (Program Store Enable): An output signal on pin 29.
When working with external code memory it works as the memory read signal. It generally connects to the Output Enable (OE) pin of the external code memory. When working with internal code memory, this pin remains high.

EA (External Access): An input signal on pin 31. If tied high, the

microcontroller executes program from internal code memory. If tied low, programs are executed from external code memory only (and PSEN pulses low accordingly). This pin also receives the programming supply voltage (VPP) during programming of the internal code memory.

CONTROL PINS
ALE (Address Latch Enable): An output signal on pin 30. While
working with external memory ALE is used to de-multiplex the address and data bus (alternate mode of port 0). The ALE latches the low byte of address on an external octal latch during the 1st half of a memory read/write cycle. During the 2nd half of the memory read/write cycle, port 0 pins are available for data I/O.
The ALE signal pulses at 1/6th the on-chip oscillator frequency. So in every machine cycle (= 12 oscillator periods), 2 ALE pulses are available. Only exception is during each access to external data memory, when one ALE pulse is missed. This pin also receives the PROG pulse input during programming of the internal code memory.

CONTROL PINS
RST (Reset): An input signal on pin that acts as the master reset
for the processor. A high on this pin for at least two machine cycles while the oscillator is running, resets the internal registers for an orderly start up. Register values after reset are as follows: Program Counter: 0000H, Accumulator: 00H, B register: 00H, DPTR: 0000H, PSW: 00H, SP: 07H, Ports 0-3: FFH, SCON: 00H, SBUF: 00H, IP: XXX00000B, IE: 0XX00000B, TCON: 00H, TMOD: 00H, PCON: 0XXX0000B.

ON-CHIP OSCILLATOR
As shown in fig. 1(a) , the 51 microcontroller features an on-chip oscillator that is typically driven by a crystal connected between pin 19 (XTAL1-input to the oscillator amplifier) and pin 18 (XTAL2-output from the oscillator amplifier). Stabilizing capacitors are also required as shown. Fig. 1(b) gives the external clock drive configuration.

POWER CONNECTIONS
The 51 microcontroller operates from a single +5 volts supply. The VCC connection is on pin 40 and the VSS connection is on pin 20.

I/O PORT STRUCTURE

I/O PORT STRUCTURE

I/O PORT STRUCTURE

I/O PORT STRUCTURE

Writing to a port pins latches data to the port latch that drives a FET connected to the port pin. The drive capability is 4 LS TTL loads for ports 1-3 and 8 LS TTL loads for port 0. Internal pull-up resistors are absent for port 0 pins (except when functioning as external address/data bus). External pull-up resistors are necessary while configured as output pins.

There is both read latch and read pin facilities. A readmodify-write instruction (like CPL (complement) a port bit) reads the port pin latch to avoid misinterpreting the logic level in case the pin is heavily loaded.

I/O PORT STRUCTURE

Instructions that input a port bit read the pin through the read pin latch. However, every read operation should be preceded by a write 1 to the port pin latch. This ensures that the FET is turned off and the pin is pulled high. A system reset sets all the port latches and hence all port pins can be used as inputs without explicitly setting the port latches. Thus, if a port pin is cleared it cannot be used subsequently as an input unless the latch is set first.

MEMORY ORGANIZATION

MEMORY ORGANIZATION
The 51 microcontroller implements a Harvard architecture for its memory: a separate program space for code and data. Both code and data could be internal or external. External memory can be expanded up to a maximum of 64K code memory and 64K data memory.

The internal memory consists of 4K 8-bit wide EPROM/Flash and 128 bytes on-chip RAM along with 21 8-bit wide special function registers. The 128 bytes of RAM contains four register banks each containing 8 registers, 16 byte of bit-addressable memory locations and 80-bytes of general purpose storage. All RAM locations (including the SFRs) are memory mapped.

MEMORY ORGANIZATION

GENERAL PURPOSE RAM

BIT ADDRESSABLE RAM: The 51 microcontroller contains 210 bit-addressable memory locations. 128 bytes are at address locations 20H to 2FH (bit address = 00H to 7FH). The rest of the bitaddressable locations are mapped onto the SFRs.
Standard operations permitted are SETB, CLR, CPL and MOV to carry bit. REGISTER BANKS: The lower 32 bytes of internal RAM constitute the register banks four blocks each containing eight bytes, one block active at a time. The 51 instruction set supports eight registers R0 to R7 for the active block. After every system reset, the default setup maps these registers at locations 00H to 07H.

GENERAL PURPOSE RAM

Instructions using R0-R7 are shorter and faster than equivalent instructions. Data values used frequently should use one of these registers. Thus,
MOV R0,A moves the content of accumulator into location 00H. The active register bank can be set by changing the register bank select bits in the program status word (PSW). The idea of register bank permits fast and effective context switching, allowing separate section of software use a private set of registers independent of other sections of software.

SPECIAL FUNCTION REGISTER

SPECIAL FUNCTION REGISTERS: The SFRs of 51 microcontroller are memory mapped and are contained at locations in the top 128 bytes of internal RAM (80H to FFH). For the 51 microcontroller, not all the address locations on the top half of the internal RAM are defined , only 21 SFR addresses are defined. Most of the SFRs are both byte-addressable and bit-addressable. The addressing trick is as follows:
The accumulator (A) is having an address of E0H. So though the byte-address is E0H, the bit addresses are E0H (for bit 0) to E7H (for bit 7). Thus the instruction SETB 0E7H sets the accumulator most significant bit.

SPECIAL FUNCTION REGISTER

PROGRAM STATUS WORD (PSW): The PSW is mapped at DOH contain the following status bits: BIT PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 D0H SYMBOL CY AC F0 RS1 RS0 OV D1H Parity flag ADDRESS BIT DESCRIPTION

D7H Carry flag D6H Auxiliary Carry flag D5H Flag 0 D4H Register Bank Select 1 D3H Register Bank Select 0 D2H Overflow flag PSW.1 Reserved PSW.0 P

EXTERNAL MEMORY

EXTERNAL MEMORY
The 51 family of microcontrollers can address 64K external code memory and 64K external data memory. Part or whole of the external data memory can be used to interface peripheral ICs as memory-mapped I/O. When external code memory is used EA is tied low and PSEN pulses low to read the code from external memory (fig-2(a)). P0 becomes a multiplexed address (A0-A7) and data (D0-D7) bus. P2 becomes the high byte (A8-A15) of the address bus. When external data memory is used (fig-2(b)) P3.6 and P3.7 function as the external data memory WR and RD pins.

EXTERNAL MEMORY

EXTERNAL MEMORY

EXTERNAL MEMORY

EXTERNAL MEMORY

INSTRUCTION SET

INSTRUCTION SET
Introduction: The 8051 instruction set is optimized for 8-bit
control applications.The instruction set provides a variety of fast, compact addressing modes for accessing the internal RAM to facilitate operations on small data structures. It also provides extensive support for 1-bit variables, allowing direct bit manipulation in control and logic systems that require Boolean processing. 8051 instructions have 8-bit opcodes. Out of the possible 256 opcodes, 255 are implemented and 1 is undefined. Some instructions have 1 or 2 additional bytes (operands) for data or addresses. In all, there are 139 1-byte instructions, 92 2-byte instructions and 24 3byte instructions.

INSTRUCTION SET
Addressing Modes: For instructions operating on data,
addressing modes specifies the source and destination of the data. The 8051 microcontrollers implements 8 different addressing modes. This section examines all the possible addressing modes with examples.

Register Addressing: The register banks, containing

registers R0 through R7, can be accessed by certain instructions which carry a 3-bit register specification within the opcode of the instruction. Instructions that access the registers this way are code efficient, since this mode eliminates an address byte. When the instruction is executed, one of the eight registers in the selected bank is accessed. One of four banks is selected at execution time by the two bank select bits in the PSW.

INSTRUCTION SET
For example, to add the content of R7 to the accumulator, the following instruction is used ADD A,R7 and the opcode is 00101111B. The upper 5 bits, 00101, implement the instruction. The lower 3 bits, 111, indicates the register R7.

Some instructions are register-specific, such as those that operate on the accumulator or data-pointer and do not require explicit address bits. The opcode itself indicates the register. For example, INC DPTR
is a 1-byte instruction that increments the data-pointer by 1.

INSTRUCTION SET
Direct Addressing: In direct addressing the operand is
specified by an 8-bit address field in the instruction. Only internal Data RAM and SFRs can be directly addressed. For example, the 2 byte instruction MOV P1,A

moves the content of the accumulator to port 1. The direct address of port 1 (90H) is determined by the assembler and inserted as byte 2 of the instruction. The source of the data, the accumulator, is specified implicitly in the opcode. MOV 30H,40H is a 3 byte instruction using the direct addressing mode. Here bytes 2 and 3 contain the addresses of the source and destination of the data to be transferred.

INSTRUCTION SET
Indirect Addressing: In indirect addressing the instruction
specifies a register which contains the address of the operand. Both internal and external RAM can be indirectly addressed. The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer. The address register for 16-bit addresses can only be the 16-bit data pointer register, DPTR.
For example, supposing the register R0 contains 40H, the instruction MOV A,@R0

moves the data at memory location 40H to the accumulator.

INSTRUCTION SET
Immediate Addressing: In immediate addressing the opcode
is followed by the data itself, instead of the location of the data. For example,
MOV A, #10H loads the accumulator with data 10H. All instructions using immediate addressing mode uses 8-bit data constant for the immediate data. The only exception is loading the DPTR with an immediate data. The instruction

MOV DPTR, #1200H

is a 3-byte instruction that loads the DPTR with the 16-bit constant 1200H.

INSTRUCTION SET
Relative Addressing: Relative addressing is used with certain
jump instructions. A relative address is an 8-bit signed value (-128 to 127), which is added to the program counter to determine the address location of the next instruction executed.
The programmer needs to assign a label for the 8-bit signed value. The assembler determines the relative offset accordingly. If the 2byte instruction SJMP LOCATION is located at program memory locations 1000H and 1001H and the label LOCATION refers to an instruction location at 1040H, the assembler will assign a relative offset of 3EH to the label LOCATION.

INSTRUCTION SET
Absolute Addressing: Absolute addressing is used only with
the ACALL and AJMP instructions. These 2-byte instructions allow branching within the current 2K page of code memory. The first 5 bits of the opcode implements the instruction and the last 3 bits along with the 2nd byte provides the branching address.

Long Addressing: Long addressing is used only with the LCALL

and LJMP instructions. These 3-byte instructions include a full 16-bit address as bytes 2 and 3 of the instruction. The advantage is that full 64K of program space may be used.

INSTRUCTION SET
Indexed Addressing: Indexed addressing uses a base register
(either the PC or the DPTR) and an offset (the accumulator) in forming the effective address of for a JMP or MOVC instruction. These instructions are used to create jump tables or look-up tables.
For example, the instruction

MOVC A, @A+PC
adds the content of the accumulator with that of the program counter to generate an address location in the program memory. Data from that location is then moved to the accumulator.

TIMER OPERATION

TIMER OPERATION
The 51 microcontroller implements two 16-bit timers each of which can be configured to work in one of four possible modes. Following are the SFRs associated with the 51 timer module: TCON (88H): Bit-addressable timer control register.

TMOD (89H): Upper nibble sets timer 1 mode, lower nibble sets timer 0 mode.
TL0 (8AH): Timer 0 low-byte. TL1 (8BH): Timer 1 low-byte. TH0 (8CH): Timer 0 high-byte. TH1 (8DH): Timer 1 high-byte.

TIMER OPERATION
Timer Mode Register (TMOD) Bit 7 6 5 4 3 2 1 0 Name Timer GATE C/T M1 M0 GATE C/T M1 M0 1 1 1 1 0 0 0 0 Description When set, timer runs only if INT1 is high Counter(1) / timer(0) select bit Mode bit 1 Mode bit 0 When set, timer runs only if INT0 is high Counter(1) / timer(0) select bit Mode bit 1 Mode bit 0

TIMER OPERATION
Timer Modes M1 0 0 M0 0 1 MODE 0 1 DESCRIPTION 13-bit timer mode 16-bit timer mode

1
1

0
1

2
3

8-bit auto-reload mode

Split timer mode. Timer 0: TL0 is an 8-bit timer controlled by timer 0 mode setting bits. TH0 is an 8-bit timer controlled by timer 1 mode setting bits. Timer 1: Stopped.

TIMER OPERATION
Timer Control Register (TCON) Bit TCON.7 Symbol TF1 Bit-address 8FH Description Timer 1 overflow flag. Set by h/w whenever counter overflows. Reset by s/w, or by h/w when processor vectors to an ISR. Timer 1 run control bit. Set or reset by s/w to start/stop counter. Timer 0 overflow flag.

TCON.6 TCON.5

TR1 TF0

8EH 8DH

TCON.4

TR0

8CH

Timer 0 run control bit.

TIMER OPERATION
Timer Control Register .. continued Bit TCON.3 Symbol IE1 Bit-address 8BH Description External interrupt 1 edge flag.Set by h/w when a falling edge is detected on INT1. Cleared by s/w, or by h/w when processor vectors to an ISR. External interrupt 1 type flag. Set/cleared by s/w for fallingedge/low-level activated external interrupt. External interrupt 0 edge flag. External interrupt 0 type flag.

TCON.2

IT1

8AH

TCON.1 TCON.0

IE0 IT0

89H 88H

INTERRUPTS
Interrupt is an event that causes a temporary suspension of a program and fires another program to service the same.

Interrupts allow the system to respond asynchronously to event(s) while executing another program. Interrupts do not occur by the execution of an instruction. It is the response of the system to an event that occurs asynchronously with the main program.
The CPU, on occurrence of an interrupt, suspends execution of the main program, executes another program to service the interrupt condition, and then returns to the execution of the main program. An interruptdriven system thus gives the illusion of executing many programs simultaneously. The program that deals with an interrupt is called the Interrupt Service Routine (ISR) or Interrupt Handler.

INTERRUPTS
Time

Main Program
Program execution without interrupts.

Interrupt-level
execution ISR

Base-level Main execution

Main

Time
Program execution without interrupts.

INTERRUPTS
8051 Interrupt Organization The 51 family of micro-controllers has five interrupt sources: two external interrupts, two timer interrupts and a serial port interrupt. All interrupts are disabled by default after a system reset and are enabled individually by software. In the event of two or more interrupts occurring simultaneously or an interrupt occurring while another interrupt is being serviced, there is both a fixed polling sequence and a programmable two-level priority scheme for scheduling the interrupts. The 51 family implements the following SFRs to enable/disable and prioritize interrupts: IE (A8H): The Interrupt Enable Register (bit-addressable) IP (B8H): The Interrupt Priority Register (bit-addressable)

INTERRUPTS
Interrupt Enable Register
Bit IE.7 Symbol EA Bit-Address AFH Description (1 = Enable) Global enable/disable

IE.6
IE.5 IE.4

ES

AEH
ADH ACH

Undefined
Undefined Enable serial port interrupt

IE.3
IE.2 IE.1

ET1
EX1 ET0

ABH
AAH A9H

Enable timer 1 interrupt

Enable external 1 interrupt Enable timer 0 interrupt

IE.0

EX0

A8H

Enable external 0 interrupt

INTERRUPTS
Enabling/Disabling Interrupts Each of the interrupt sources can be individually enabled/disabled by setting/clearing the corresponding bit in the IE SFR at location A8H. All interrupts can be globally disabled by clearing the global enable bit at AFH. To enable an interrupt source two bits must be set. The individual enable bit and the global enable bit. For example the serial port interrupt is enabled as follows: SETB ES SETB EA ; Enable serial interrupt ; Set global enable bit

An alternative coding runs as follows: MOV IE,#10010000B

INTERRUPTS
Interrupt Priority Register Bit IP.7 IP.6 IP.5 IP.4 IP.3 Symbol PS PT1 Bit-Address BFH BEH BDH BCH BBH Description (1 = Higher Priority) Undefined Undefined Undefined Priority for serial port interrupt Priority for timer 1 interrupt

IP.2
IP.1 IP.0

PX1
PT0 PX0

BAH
B9H B8H

Priority for external 1 interrupt

Priority for timer 0 interrupt Priority for external 0 interrupt

INTERRUPTS
Interrupt Priority Each interrupt source can be programmed to one of two priority levels through IP - the bit-addressable SFR at location B8H. IP is cleared by a system reset to place interrupts at low priority level by default. Priority of an interrupt source is set to high by setting the corresponding bit in the IP register. Whenever a high priority interrupt occurs when a low priority ISR is running, the ISR is interrupted. However, a high priority ISR cannot be interrupted.

The main program, operating at base level, can always be interrupted. If two interrupts occur simultaneously, the higher priority one is serviced first.

The 8051 Serial Port

Serial Port
One of the 8051s many powerful features is its integrated UART, otherwise known as a serial port. It can operate in several modes over a wide range of frequencies. Hardware access to the serial port is through the TxD and RxD pins. These are the alternate functions of P3.1 (pin 11) and P3.0 (pin 10) respectively. The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. (However, if the first byte still hasn't been read by the time reception of the second byte is complete, the first byte received will be lost). The next slide illustrates the functional block diagram of the serial port.

Serial Port

Serial Port
The serial port receive and transmit registers are both accessed through a Special Function Register SBUF at address 99H. Actually, SBUF represents two separate buffers, a transmit buffer and a receive buffer. Writing to SBUF loads the write-only transmit register, and reading SBUF accesses a physically separate read-only receive register. The serial port control register, SCON, is a bit-addressable register at address 98H, containing the status bits and control bits. The control bits set the mode of operation of the serial port. The status bits indicate the end of a character transmission or reception. The status bits can be tested in software or can be programmed to generate an interrupt.

Serial Port
Serial Port Mode setting The 8051 serial port has four modes of operation that can be set by writing 1s and 0s to the SCON.7 (SM0) and SCON.6 (SM1) bits. The first mode implements a simple shift register and the other three modes enables asynchronous serial communication. Serial Port Modes: SM0 0 SM1 0 MODE 0 DESCRIPTION Shift Register BAUD RATE Fixed (Osc. Fq. / 12)

0
1 1

1
0 1

1
2 3

8-bit UART
9-bit UART 9-bit UART

Variable (set by T1)

Fixed (Osc. Fq./32 or/64) Variable (set by T1)

Serial Port
Mode 0: Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits (LSB first) are transmitted/received.The baud rate is fixed at 1/12 the oscillator frequency. Mode 1: 10 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable. Mode 2: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). While transmitting, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. On reception, the 9th data bit goes into RB8 in SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. Mode 3: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit (1). The baud rate is variable.

Serial Port
SCON Register Summery BIT
SCON.7
SCON.6 SCON.5 SCON.4 SCON.3 SCON.2 SCON.1

SYMBOL ADDRESS
SMO
SM1 SM3 REN TB8 RB8 TI

DESCRIPTION
Serial port mode bit 0
Serial port mode bit 1 Serial port mode bit 2 Receiver Enable Transmit bit 8 (9-bit UART) Receive bit 8 (9-bit UART) Transmit interrupt flag. Set at end of character transmission. Cleared by S/W.

9FH
9EH 9DH 9CH 9BH 9AH 99H

SCON.0

RI

98H

Receive interrupt flag. Set at end of character reception. Cleared by S/W.

Serial Port
Other important bits in SCON register The 5th bit in SCON, SM2, enables multiprocessor communication in modes 2 and 3. RI will not be activated if received 9th bit is 0. The 4th bit in SCON, REN, enables the receiver and must be set to receive characters. The 3rd bit in SCON, TB8, is the 9th bit transmitted in modes 2 and 3. TB8 is set/cleared by software. The 2nd bit in SCON, RB8, is the 9th bit received in modes 2 and 3. The 1st bit in SCON, TI, is the transmit interrupt flag. If set indicates that the transmission of the last byte written on SBUF is over. Must be cleared by software. The 0th bit in SCON, RI, is the receive interrupt flag. If set indicates that the reception of the character is over. Must be cleared by software.

Serial Port
Serial Port Baud Rate Setting

Mode 0 (Fixed clock) Baud rate clock = On chip oscillator clock / 12.

Modes 1 and 3 (Variable clock)

Baud rate clock = Timer 1 overflow rate /n (n = 32 if PCON.7 (SMOD) is clear,; = 16 if PCON.7 (SMOD) is set.)

Mode 2 (Fixed clock)

Baud rate clock = On chip oscillator clock /n (n = 64 if PCON.7 (SMOD) is clear; = 32 if PCON.7 (SMOD) is set.)

Serial Port
Mode 1 & 3 Baud Rate Calculation
Baud rate clock (BR) = Timer 1 overflow rate (TOR) /n (n = 32 if PCON.7 (SMOD) is clear,; = 16 if PCON.7 (SMOD) is set.) = (TOR*2SMOD) / 32; Timer clock period (TCP) = 12/ oscillator frequency (OF); TOR = 1/ (TCP*COUNT) = OF / (12*COUNT); Therefore,

BR = (OF * 2SMOD) / (32*12*COUNT);

or, COUNT = (OF* 2SMOD) / (32* 12 *BR);