EVOLUTION OF COMPUTER-AIDED DIGITAL DESIGN

Digital Circuit design has evolved rapidly over last 25 years Earlier circuits were designed using vacuum tubes and transistors Integrated circuits were then invented where logic gates were placed on a single chip SSI MSI LSI VLSI As complexity increased, then it was not possible to verify circuits on breadboard Computer-aided programs became critical for verification and design of VLSI digital circuits Computer programs does automatic placement and routing of circuit layouts

 Designers built gate-level digital circuits manually on graphic terminals

Initially small building blocks were built & then higher-level blocks were formed
Process will be continued until a top level block is achieved Logic simulators also helped in verification of these circuits

EMERGENCE OF HDLs

Initially FORTRAN, Pascal & C/C++ were being used

Then HDL came into existence HDLs allowed designers to model the concurrency of processes found in hardware elements

HDL has two flavors:

1. Verilog HDL (formed in 1983) 2. VHDL HDLs also began to be used for system level design

1. System boards 2. FPGAs 3. PALs

Today, Verilog HDL is an accepted IEEE standard

In 1995, original standard IEEE 1364-1995 was adopted IEEE 1364-2001 is the latest Verilog HDL standard

Design Specification TYPICAL DESIGN FLOW Behavioral Description RTL Description (HDL)
Functional Verification & Testing

Logic Synthesis/ Timing Verification

Gate-Level Netlist
Logical Verification & Testing
Floor Planning; Automatic Place & Route

Physical Layout Implementation Layout Verification

 Specifications describe abstractly the functionality, interface and overall architecture of the digital circuit to be designed At this point, the architects do not need to think about how they will implement this circuit? Behavioral description is then created to analyze the design in terms of functionality, performance, compliance to standards and other high-level issues Behavioral is then converted to RTL description Designer describes data flow that will implement the desired digital circuit From this point onwards, the design process is done with the assistance of EDA tools Gate-level netlist is a description of circuit in terms of gates and their interconnections Logic synthesis ensures that the gate-level netlist meets timing, area and power specifications Gate-level netlist is put to an Automatic place and route tool, which creates a layout Layout is verified and then fabricated on a chip

IMPORTANCE OF HDLs
Design can be described at a very abstract level by use of HDLs Functional verification of the design can be done very easily & early in the design cycle

Analogous to computer programming

DESIGN METHODOLOGIES

Top-level Block

Sub-block 1

Sub-block 2

Sub-block 3

Sub-block 4

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

In Top-down design we define the top-level block and identify the sub-blocks necessary to build the top-level blocks We further subdivide the sub-blocks until we come to leaf cells, which are the cells that cannot further be divided.

Top-level Block

Sub-block 1

Sub-block 2

Sub-block 3

Sub-block 4

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

In bottom-up design we identify the building blocks that are available to us We build bigger cells/blocks and ultimately we build the top-level block in the design

MODULE Verilog provides the concept of module A module is basic building block; can be an element or a collection of lowerlevel design blocks Typically elements are grouped into modules to provide common functionality that is used at many places in the design A module provides the necessary functionality to the higher-level block through its port interface (input/output), but hides the internal implementation This allows the designer to modify internals without affecting the rest of the design module <module_name> ... <module internals> endmodule

Specifically, the D-flip flop could be defined as a module as follows:

module T_FF . . (q,clock,reset)

<functionality of T-flip flop>

. . endmodule

 Verilog is both a behavioral and a structural language Internals of each module can be defined at four levels of abstraction, depending on the needs of the design Module behaves identically with the external environment irrespective of the level of abstraction at which the module is described The internals of the module are hidden from the environment

Thus, level of abstraction to describe a module can be changed without any change in the environment

BEHAVIORAL OR ALGORITHMIC LEVEL This is the highest level of abstraction provided by Verilog HDL A module can be implemented in terms of the desired design algorithm without concern for the hardware implementation details Designing at this level is very similar to C programming

DATAFLOW LEVEL Module is designed by specifying data flow

The designer is aware of how data flows between hardware registers and how the data is processed in the design

GATE LEVEL

Module is implemented in terms of logic gates and interconnections between these logic gates
Design at this level is similar to describing a design in terms of a gate-level logic diagram

SWITCH LEVEL The lowest level of abstraction provided by Verilog A module can be implemented in terms of switches, storage nodes and the interconnections between them Design at this level requires knowledge of switch-level implementation details

Verilog allows the designer to mix and match all four levels of abstraction in a design Normally, the higher the level of abstraction, the more flexible and technology-independent the design As one goes lower toward switch-level design, the design becomes technology-dependent and inflexible

INSTANCES
The process of creating objects from a module template is called instantiation A module provides a template from which you can create actual objects

When a module is invoked, Verilog creates a unique object from the template
Each object has its own name, variables, parameters and I/O interfaces

COMPONENTS OF SIMULATION Once a design is completed, it must be tested The functionality of the design block can be tested by applying stimulus and checking results. This block is called stimulus Stimulus block is also called test bench

LEXICAL CONVENTIONS
The basic lexical conventions used by Verilog HDL are similar to those in the C programming. Whitespace

Comments
Operators Number Specification (Sized Numbers; Unsized Numbers; X or Z values; Negative Numbers, Underscore characters and question marks) Strings Identifiers and keywords

Escaped Identifiers
Data types (Value Set; Nets; Registers; Vectors; Arrays; Memories; Parameters)

A module definition always begins with the keyword module

The module name, port list, port declaration and optional parameters must come first in a module definition
Port list and port declarations are present only if the module has any ports to interact with the external environment

The five components within a module are:

1. Variable declaration 2. Dataflow statement 3. Instantiation of lower modules 4. behavioral blocks 5. tasks/functions These components can be in any order in module definition

The endmodule statement must always come last in the module definition
All components except module, module name and endmodule are optional and can be mixed and matched as per design needs Multiple modules can be defined in a single file

SR LATCH

FULL ADDER

PORT DECLARATION
All ports in the list of ports must be declared in the module Ports can be declared as follows:

Verilog Keyword input output inout

Type of Port Input port Output port Bidirectional port