Beruflich Dokumente
Kultur Dokumente
Overview
Gray Code Background Delegated Duties Method of Design Target Specifications Simulation Results Block Diagram Schematics, Symbols, Layouts, and Simulations Design References Conclusion
2
1 1
1 0
0 1
0 0
(GC)
MSB does not change as a result of conversion Start with MSB of binary number and add it to neighboring binary bit to get the next Gray code bit Repeat for subsequent Gray coded bits
4
+
(BC)
+
1 0
+
0
MSB does not change as a result of conversion Start with MSB of binary number and add it to the second MSB of the Gray code to get the next binary bit Repeat for subsequent binary coded bits
5
Delegated Duties
Martin Binary to Gray Conversion, Gray to Binary Conversion (XOR gates) Dang Binary/Gray Output Selection (MUXs) Khoa Binary Code Counter, Parallel-to-Parallel Shift Register (D flip-flops)
6
Method of Design
Decided on an initial load capacitance (Cin) Partitioned the circuit into different propagation delay times according to gate/device requirements, and divided propagation delay times amongst the individual gates and devices Created the symbol and layout for out each type of gate (XOR, MUX, NAND) Connected gate symbols to create device symbols Connected gate layouts to create device layouts Connected device symbols to create circuit schematics, and connected device layouts to create circuit layouts
7
Target Specifications
Conversion:
Binary Code to Gray Code Gray Code to Binary Code
Propagation delay times: XOR (each): 0.4 nS MUX (each): 0.3 nS D flip-flop (each): 0.63 nS (worst-case fall time) Technology specs (size): Minimum Channel Width = 1.5 m Minimum Channel Length = 0.6 m Power < Watt Clock Speed = 200 MHz Total area as small as possible
8
Simulation Results
Successfully converts binary and Gray codes Propagation Delay
XOR (each): 0.338 nS (worst-case) MUX (each): 0.35 nS (worst-case) D flip-flop (each): 1.14 nS (worst-case fall time)
Simulation Results
Power (using the power meter)
39.94 mW
Clock Speed
200 MHz
Total Area
Gray code converter: 6.03E-4 cm2 Counter: 10.2E-4 cm2
10
Block Diagram
11
XOR Schematic
12
XOR Symbol
13
XOR Layout
14
XOR Extracted
15
16
17
18
XOR Threshold
19
MUX Schematic
20
MUX Symbol
21
MUX Layout
22
MUX Extracted
23
24
25
26
27
NAND3 Schematic
28
NAND3 Symbol
29
NAND3 Layout
30
NAND3 Extracted
31
32
33
34
D Flip-Flop Schematic
35
D Flip-Flop Symbol
36
D Flip-Flop Layout
37
D Flip-Flop Extracted
38
39
40
41
Counter Schematic
42
Counter Symbol
43
Counter Layout
44
Counter Extracted
45
46
47
48
49
50
51
52
53
54
55
Power
56
Design References
CMOS Integrated Circuits
By Kang
Digital Fundamentals
Thomas Floyd
57
Conclusion
We designed and simulated a Gray code converter that converts binary coded numbers to Gray coded numbers and vice versa The nmos and pmos transistor widths were greater than 1.5 m The power specifications were well below Watt and a code conversion took place within 5 nS Our target specifications were met
58