Memory Hierarchy for Microblaze and PowerPC based Systems

Under the guidance of:

Department of Computer Science and Engineering IIT DELHI
Dr. Kolin Paul

Presented by
Nikunj Shroff 2005JCA2435
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Agenda

Objective. Project Overview. Core Block Diagram of MicroBlaze. SystemC. Block Diagram of system (PowerPC). Image Processing application. Observation. References.
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Objective

Analyze the possibility of constructing a hierarchy of memories

Different Capacities Different access times

Develop Memory containing

hierarchy

for

embedded

system

Microblaze (and / or) PowerPC processor Embedded RAM

BRAM Distributed Ram

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Project Overview

MicroBlaze

Configuration of cache in Microblaze. Modeling of Microblaze

SystemC

PowerPC

Configuration of cache in PowerPC.

Processors

MicroBlaze

SoftCore Runs at 100 MHz HardCore Runs at 400 MHz

PowerPC

Microblaze Core Block diagram

MicroBlaze (www.xilinx.com)

Cache link interface

The MicroBlaze CacheLink interface

Connect to an Fast Simplex Link (FSL) interfaced memory controller via an explicitly instantiated FSL master/slave pair. Connect directly to a memory controller with integrated FSL buffers, e.g. the MCH_OPB_SDRAM), which results in less latency and fewer instantiations.

Data Cache

All cacheable data addresses are further split into two segments:

Cache word address segment Tag address segment.

The size of the two segments can be configured by the user. The size of the cache word address can be between 11 to 14 bits. This results in a cache sizes ranging from 8 kB to 64 kB. The tag address should be sized so that it matches the complete range of cacheable memory in the design.

Data Cache Operation

If MicroBlaze executes a store instruction,

If the address is not within the cacheable address segment

Operation is performed as normal but Data cache is updated with the new data,

If the address is within the cacheable address segment,

Cache is not updated on a write miss. If MicroBlaze executes a load instruction,

If the address is within the cacheable area,

Whether the address is currently cached.

Data is retrieved from the cache.

If the address is not within the cacheable area

Normal operation is performed

Example

E.g. assuming a configuration of C_DCACHE_BASEADDR= 0x00400000, C_DCACHE_HIGHADDR=0x00403fff,

(All addresses within this range correspond to the cacheable address space segment. All other addresses are non-cacheable)

The cacheable byte address range is 14 bits.

C_DCACHE_BYTE_SIZE=2048; Cache byte address range is 11 bits (i.e. a 9 bit cache word address), Thus the required address tag is 14-11=3 bits.
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System View (when cache is not enabled)

DLMB DOPB IOPB

BRAM

ILMB

Microblaze

Timer UART Controller To External Memory Memory Controller

SOPB

To UART

Hardware Debug Module Controller OPB

To XMD Debug Module

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System View (when cache enabled on OPB Bus)

DLMB

DOPB IOPB

BRAM

ILMB

Microblaze

Microblaze Trace IP (My Ip)

Timer UART Controller To External Memory Memory Controller

SOPB

To UART

Hardware Debug Module Controller OPB

To XMD Debug Module

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System View (when cache is enabled using Xilinx cache link)

DLMB

DOPB IOPB

BRAM

ILMB

Microblaze
IXCL
MCH 0

Microblaze Trace IP (My Ip) To UART

DXCL
MCH 1

UART Controller Hardware Debug Module Controller

To External Memory

Memory Controller
SOPB

To XMD Debug Module

Timer OPB

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System View (when cache is enabled using FSL link)

DLMB

BRAM
ILMB

DOPB IOPB

Microblaze
1 2
FSL 0,1,2,3

3 4

Microblaze Trace IP (My Ip)

UART Controller To External Memory

1. Fsl Data Cache In 2. Fsl Data Cache Out 3. Fsl Instruction Cache In 4. Fsl Instruction Cache Out

To UART

Memory Controller
SOPB

Hardware Debug Module Controller

To XMD Debug Module

Timer
14

OPB

SystemC

To create a system-level model. Quick simulation in order to validate and optimize the design.

Provide the hardware and software development with an executable specification of the system.
The SystemC Class Library provides the necessary constructs to model system architecture including

Hardware timing, Concurrency, and Reactive behavior

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Top Level Design

Stored from a External File Inst.txt

Stored to and from local user defined Array 16

Internal Architecture

MicroBlaze

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Microblaze
instr From IBRAM i_ready D_ready From DBRAM Data_read Microblaze i_en i_address i_fetch i_as en Read_strobe Write_strobe i_address Byte_enable address Data_write To IBRAM

To

DBRAM

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Cache Memory Mapping

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Direct and Associative Mapping

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SYSTEM VIEW
FPGA PLB OPB BRAM ILMB

DLMB PowerPC
Application BRAM Timer IP (My IP) PLB2OPB Bridge

MicroBlaze USB Connection UART RS-232

Memory Controller Sys ACE Controller OPB2DCR Bridge DCR Video Controller

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Logical portioning of memory

2 MB 2 MB 2 MB First Image

Second Image
Third Image

256 MB External Memory

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Memory Hierarchy of the System

Registers (Internal to PowerPC / MicroBlaze) BRAM Cache for PowerPC (fixed 16KB) Cache for MicroBlaze ( variable size)

Main Memory 256 MB External DDR Memory

Flash Drive 256 MB

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Bitwise colors stored in memory location

Memory Location [00000000] [00000001] [00000002] [00000003] [00000004] [00000005] [00000006] [00000007] [00000008] [00000009] [0000000A] [0000000B] [0000000C] [0000000D] [0000000E] [0000000F] Blue Green Red Unused 84 252 84 252 84 252 0 168 0 168 0 168 0 168 84 252 252 84 252 84 84 252 84 252 252 252 252 252 0 0 0 0 168 0 168 0 0 168 0 168 168 168 168 168 84 84 84 84 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Blue

Green Red Unused

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Image Processing

Normal image

Revert Color

Mirror Image

Mirror & Revert

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Observation
Matrix size Both I & D cache
(clock cycles)

No cache
(clock cycles)

Instruction cache
(clock cycles)

(clock cycles)

Data cache

Data read hits 8 29

5x5 10x10

2003 12463

37490 265035

7469 55231

33345 230168

15x10
20x20 25x25 30x30

38915
89003 170156 289866

859133
1996113 3852207 6603814

165728
430827 840119 1444898

739001
1708599 3286614 5623507

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103 158 228

35x35
40x40 45x45 50x50

455635
675048 955379 1687005

10427222
15498712 21994753 30091400

2278266
3402303 4836551 6620709

8864491
13162708 18660692 25875386

308
405 508 11784
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Overall Comparison

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Observation (PowerPC)
No. of Images Both Cache off I-cache ON (Clocks)

(Clocks)
1 1809998 1500337

Gain Ratio I-Cache

D-Cache ON (Clocks)

Gain Ratio D-cache

Both I and D ON (Clocks)

Gain Ratio I & D cache

1.2

1197707

1.51

836977

2.16

3729994

2834520

1.31

2391502

1.55

1669324

2.24

5594344

4249072

1.31

3584422

1.56

2501056

2.23

7213484

6175721

1.17

4778200

1.51

3333481

2.16

9016292

7718060

1.16

5971158

1.50

4165239

2.16

6 7

10820264 12623647

8928029 10804383

1.21 1.16

7165016 8358387

1.51 1.51

4997595 5829637

2.16 2.16

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Overall Comparison (PowerPC)

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Conclusion

In case of small program used in Microblaze

Instructions are fetched frequently so caching of instructions gives high performance gain. In above mentioned memory models xilinx cache link is the best one which has less latency for instruction and data access. The size of Data is more so caching of data in this case gives more performance gain.
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In case of large program used in PowerPC

References

Embedded Development Kit, Getting Started with EDK, 1-800-255-7778 EDK 7.1i February 15, 2005 http://www.xilinx.com. MicroBlaze Processor Reference Guide,1-800-255-7778 UG081 (v5.0) January 20, 2005 http://www.xilinx.com. FPGA Field Programmable Gate Array, http://www.andraka.com/whatisan.htm VHDL Very High Speed Integrated Circuit Hardware Description Language http://ghdl.free.fr/ghdl/index.html Fast Simplex Link FSL, DS449 December 1, 2005 www.xilinx.com MCH controllerMulti-CHannel (MCH) On-chip Peripheral Bus controller. DS496 July 1, 2005 www.xilinx.com PowerPC Processor. EDK 6.1 September 2, 2003 www.xilinx.com Relocating Data and code for embedded systems, XAAP642 (v1.0) October 21, 2002 www.xilinx.com. Platform studio User guide for EDK 6.2i UG113 (v1.0) March 12, 2004 Device Driver Programmer Guide. v1.2 - July 31, 2002 www.xilinx.com. XUP Virtex-II Pro Development System Hardware Reference Manual, Document Version: 0.00Document Date: August 2004

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