Beruflich Dokumente
Kultur Dokumente
06/30/09
Mohit Gupta
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AGENDA
Oops
class, object, static vs global variables, this operator, access to objects properties, modification of objects, copying objects, Public, private, local and const members, inheritance, virtual methods, virtual class, polymorphism, callbacks
randomization
what to randomize, random variables, constraint blocks, inside and dist operators, conditional constraint, variable ordering, constraint_mode, rand_mode, in-line constraint, pre_randomize and post_randomize, tips and techniques, iterative contraints, rand_sequence, random stability.
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Class
What does a class contains?
Class encapsulates the data together with the routines , which manipulate the data.
Why Class?
The goal of the testbench is to apply stimulus and check result. The data that flows into and out of the design is grouped together into transactions. In Oops transaction is an object of a class.
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Constructing an object
Objects are created by calling a new() method.
How does SystemVerilog know which new function to call? It looks at the type of the handle on the left side of the assignment. e.g.
Avoid declaring a handle and calling the constructor, new, all in one statement. You may want to initialize objects in a certain order, but if you call new in the declaration, you wont have this control.
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The variable id is not static, so every BusTran has its own copy.
Just make sure that static variable is initialized before the first object is constructed.
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What is this
When you use a variable name, SystemVerilog looks in the current scope for it, and then in the parent scopes until the variable is found. But what if you are deep inside a class and want to unambiguously refer to a classlevel object? The this keyword is used to unambiguously refer to class properties or methods of the current instance. e.g.
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This can cause subtle bugs if two parts of the code are unintentionally sharing the same variable, perhaps because you forgot to declare it in the innermost scope.
e.g
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object.
If you dont want an object modified in a routine, pass a copy of it so that the
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Even though create_packet modified the argument bt, the handle b remains null.
You need to declare the argument bt as ref.
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A very common mistake is forgetting to create a new object for each transaction in the testbench. The solution is to to create a new BusTran during each pass through the loop as given below.
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Both BusTran objects point to the same Statistics object and both have the same id Why? Objects and handles before copy with new
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e.g.
The downside of making your own copy function is that you need to keep it up to date as you add new variables forget one and you could spend hours debugging to find the missing value.
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Class members can be identified as either local or protected and class properties can be further defined as const, and methods can be defined as virtual.
class properties allow two forms of read-only variables: global constants and instance constants. Global constant class properties are those that include an initial value as part of their declaration. Instance constants do not include an initial value in their declaration, only the const qualifier. This type of constant can be assigned a value at run-time, but the assignment can only be done once in the corresponding class constructor.
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Inheritance
Inheritance in SV is more or the less similar to vera. Inheritance is the process of creating a new subclass that inherits the members of the parent class by extending the parent class. The mechanism provided by SystemVerilog is called Single-Inheritance, that is, each class is derived from a single parent class. The super keyword is used from within a derived class to refer to members of the parent.
When you start extending classes, there is one rule about constructors (new function) to keep in mind. If your base class constructor has any arguments, the extend constructor must have a constructor and must call the bases constructor on its first line.
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Inheritance
Always declare routines inside a class as virtual so that they can be redefined in an extended class.
This applies to all tasks and functions, except the new function, which is called when
the object is constructed, so there is no way to extend it.
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If you assign an extended handle to a base handle, nothing special is needed as all the members of base class exists in the extended class.
But what if you are copying a base object into an extended handle, it fails. e.g.
It is not always illegal to assign a base handle to an extended handle. It is allowed when the base handle actually points to an extended object. $cast routine checks the type of object, not just the handle.
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You can eliminate this error by using $cast as a function and checking the result 0 for incompatible types, and non-0 for compatible types.
e.g.
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Virtual methods :
For virtual methods, SystemVerilog uses the type of the object, not the handle to decide which routine to call.
If the routines were not defined as virtual, SV would use the type of the handle (Transaction), not the object. That last statement would call Transaction::calc_crc probably not what you wanted.
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Abstract classes
Virtual class & methods are a way of creating a template, From such a template, real classes are derived.
A base class sets out the prototype for the subclasses. Since the base class is not intended to be instantiated, it can be made abstract by specifying the class to be virtual.
virtual class BasePacket; Abstract classes can also have virtual methods, which should be overwritten by derived class. A virtual method overrides a method in all the base classes. An abstract class can contain methods for which there is only a prototype and no implementation (pure virtual). An abstract class cannot be instantiated, it can only be derived. Methods of normal classes can also be declared virtual. In this case, the method must have a body. If the method does have a body, then the class can be instantiated, as can its subclasses.
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Polymorphism Example
.
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Struct Vs Classes
class differs from struct in following ways: 1) SystemVerilog struct are strictly static objects and SystemVerilog objects (i.e.,
class instances) are exclusively dynamic, their declaration doesnt create the
object; that is done by calling new. 2) SystemVerilog structs are type compatible so long as their bit sizes are the same, thus copying structs of different composition but equal sizes is allowed. In contrast,
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Callbacks
A verification environment should be usable by all tests with no changes. The key requirement is that this testbench must provide a hook where the test program can inject new code without modifying the original classes. e.g. driver may want to do the following: Inject errors Drop the transaction Delay the transaction Synchronize this transaction with others Put the transaction in the scoreboard Gather functional coverage data.
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Creating a callbacks
A callback task is created in the top-level test and called from the driver,the lowest level of the environment.
The driver does not have to have any knowledge of the test it just has to use a generic class that the test can extend.
e.g.
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Randomization
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What to Randomize
When you think of randomizing the stimulus to a design, the first thing you may think of are the data fields. You need to think broadly about all design input such as the following. Device configuration Environment configuration Primary input data Encapsulated input data Protocol exceptions Delays
Transaction status
Errors and violations
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Random variables
SV provides two types of random variables : rand , randc. Variables declared with the rand keyword are standard random variables. Their values are uniformly distributed over their range. For example: rand bit [3:0] y; Variables declared with the randc keyword are random-cyclic variables that cycle through all the values in a random permutation of their declared range. Random-cyclic variables can only be of type bit or enumerated types. The basic idea is that randc randomly iterates over all the values in the range and that no value is repeated within an iteration. When the iteration finishes, a new iteration automatically starts. E.g randc bit [1:0] y;
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Constraint blocks
Constraints blocks are very similar to vera. Following class shows the example of a constraint block with simple expression :
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An instance of class A constrains x to be less than zero whereas an instance of class B constrains x to be greater than zero. The extended class B overrides the definition of constraint c.
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The weights are not percentages and do not have to add up to 100.
The := operator specifies that the weight is the same for every specified value in the range, while the :/ operator specifies that the weight is to be equally divided between all the values.
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Conditional constraint
All constraint expressions are active in a block. What if you want to have an expression active only some of the time?
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Variable Ordering
Sometimes it is desirable to force certain combinations to occur more frequently. E.g. consider the following example : class B; rand bit s; rand bit [31:0] d; constraint c { s -> d == 0; } endclass What is the problem with the above example? The Probability of s being true is 33 , which is practically zero. The solutions is : force the variable ordering class B;
rand bit s;
rand bit [31:0] d; constraint c { s -> d == 0; } constraint order { solve s before d; }
endclass
Variable ordering can be used to force selected corner cases to occur more frequently than they would otherwise.
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In-line constraints
SV allows you to add an extra constraint using randomize() with. This is equivalent to adding an extra constraint to any existing ones in effect.
Note that inside the with{} statement, SystemVerilog uses the scope of the class. That is why Above example used just addr, not t.addr.
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}
2. Use non random values to hit particular corner cases. Define the variables to be random. Use rand_mode to enable and disable randomness as per the requirement.
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p = new();
// Randomize all variables assert (p.randomize()); $display("Simple randomize"); // Make length nonrandom then randomize packet p.length.rand_mode(0); p.length = 42; assert (p.randomize()); $display("Randomize with rand_mode");
end
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endclass
program test;
constraint Packet::c_external {length == 1;} ...
endprogram
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Iterative constraint
Iterative constraints allow arrayed variables to be constrained in a parameterized manner using loop variables and indexing expressions.
Using the foreach constraint creates many constraints and slow down simulation.
The easiest array constraint to understand is the size function. You are specifying the number of elements in a dynamic array or queue.
class dyn_size; rand reg [31:0] d[];
Always remember to specify upper bound while using size function with inside. You can send a random array of data into a design, but you can also use it to control the flow.
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Iterative constraint
parameter MAX_TRANSFER_LEN = 10; class StrobePat; rand bit strobe[MAX_TRANSFER_LEN]; constraint c_set_four { strobe.sum == 3h4; } endclass
initial begin
StrobePat sp;
int count = 0; // Index into data array sp = new(); assert (sp.randomize); foreach (sp.strobe[i]) begin
bus.cb.strobe = sp.strobe[i];
// If strobe is enabled, drive out next data word if (sp.strobe[i]) bus.cb.data = data[count++]; end end
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end Above example generates a sequence stream, which can be either cfg_read, io_read or mem_read. The random sequence engine randomly picks one.
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randsequence
SV allows following inside randsequence items : If-else in production items.
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endclass
CA a = new; a.randomize(); // random variables: x, y state variables: v, w a.randomize( x ); // random variables: x state variables: y, v, w a.randomize( v, w ); // random variables: v, w state variables: x, y
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Random Stability
What is random stability ? To understand let us discuss about PRNG (Pseudorandom number generators).
Verilog has a single PRNG that is used for the entire simulation.
Testbenches often have several stimulus generators running in parallel, creating data for the design under test. If two streams share the same PRNG, they each get a subset of the random values.
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Random Stability
This approach changes the values used not only by Gen1, but also by Gen2.
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THANK YOU
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