INTER-INTEGRATED CIRCUIT

Basic Characteristics

The name stands for Inter - Integrated Circuit Bus Two wire: serial data (SDA) and clock (SCL) lines Originally to interact within small num. of devs (Microcontroller, EEPROM, Real-Timer, interface chips, LCD driver, A/D converter) Data transfer between ICs and systems at relatively low rates

100 kbps (standard mode) 400 kbps (fast mode) 3.4 Mbps (high-speed mode)

Data transfers: serial, 8-bit oriented, bi-directional Master/Slave relationships with multi-master option Master can operate as transmitter or receiver Slave selection protocol uses a 7-Bit slave address The bus specification allows an extension to 10 bits

Characteristics Contd

Unique start and stop condition Acknowledgement after each transferred byte No fixed length of transfer Max. line capacitance 400 pF (4 meter long) True multi-master capability Clock synchronization Arbitration procedure Compatible with different IC technologies

Wired-AND connection

I2C devices are wire ANDed together.

If any single node writes a zero, the entire line is zero

States

Master:

Initiates a transfer by generating start and stop conditions Generates the clock Transmits the slave address Determines data transfer direction
Responds only when addressed Timing is controlled by the clock line

Slave:

Transmitter/Receiver

Master or slave Master-transmitter sends data to slave-receiver Master-receiver requires data from slave-transmitter

Standard Mode

In normal data transfer, the data line only changes state when the clock is low
Bus is free SDA and SCL are high (by pull-up resistors) SCL = 1 SDA = valid data

one clock pulse per data bit stable data during high clocks data change during low clocks

Standard Mode Contd

A transition of the data line while the clock line is high is defined as either a start or a stop condition. Both start and stop conditions are generated by the bus master The bus is considered busy after a start condition, until a stop condition occurs

Standard Mode Contd

SCL must be always 1 during transmission Start condition (S)

SDA 10 transition SDA 01 transition start is generated instead of stop Busy .. after S and before next P Free .. after P and before next S

Stop condition (P)

Repeated start (Sr)

Bus state

Frame Format

Data bits are transferred after start condition Transmission is byte oriented Byte = 8 bits + one acknowledge bit Most significant bit (MSB) first Slave address is also datum
First byte transferred During the first byte transfer:

Master is transmitter Addressed slave is receiver

Next bytes: depends on the last bit in address byte

Data Transfer - SCL

Master sets SCL = 0 and generates pulse for each data bit 8 pulses for data bits are followed by one pulse for Ack bit After Ack (Clock Stretching)

Master tries to generate next bytes first pulse Slave can hold SCL low, master switches to wait state

Data Transfer - SDA

Data bits are generated by transmitter as SCL pulses 9-th pulse:

Transmitter releases SDA Receiver must hold SDA low in order to ack. received data Slave must release SDA after ack. bit (allows master to end frame)

Multiple Masters

More bus controllers can be connected Several masters can start frame at once Synchronization needed on SCL Arbitration needed on SDA Using wired-AND connection to SCL/SDA

Synchronization of SCL

All masters generate their own clock on the SCL line to transfer messages on the I2C-bus. Clock synchronization is performed using the wiredAND connection of I2C interfaces to the SCL line. A synchronized SCL clock is generated with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period.

Arbitration

Two or more masters may generate a START condition within the minimum hold time of the START condition which results in a defined START condition to the bus. Arbitration takes place on the SDA line, while the SCL line is at the HIGH level, in such a way that the master which transmits a HIGH level, while another master is transmitting a LOW level will switch off its DATA output stage because the level on the bus doesnt correspond to its own level. Arbitration isnt allowed between:

A repeated START condition and a data bit

A STOP condition and a data bit

A repeated START condition and a STOP condition.

Addressing by 7 bits

The first byte transmitted by master:

7 bits: address 1 bit: direction (R/W)

0 master writes data (W), becomes transmitter 1 master reads data (R), becomes receiver

Data transfer terminated by stop condition Master may generate repeated start and address another device Each device listens to address

Address matches its own device switches state according to R/W bit Fixed part assigned by I2C committee

Address = fixed part + programmable part

Special Addresses

General call 0000 000 | 0 Start byte 0000 000 | 1 CBUS address 0000 001 | *
Used

for cooperation of I2C and CBUS

High-speed mode master code 0000 1** | * 10-bit slave addressing 1111 0** | *

General call

Addresses all devices Device ignores call not acknowledges address Device accepts call acknowledges address R/W = 0 (W) master-transmitter, slave-receiver Command in the second byte LSB = 0 (least significant bit)

Programmable part of devices address manipulation Resetting devices

LSB = 1

Master (e.g. keyboard scanner) doesnt know where to send data Remaining 7 bits contain masters address