Sandeepani Verilog

Sandeepani
www.sandeepani-vlsi.com
Verilog HDL Coding for Simulation & Synthesis
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Whats Coming
Objectives
Introduce Verilog language concepts Use of language features to capture hardware design specification and Verify Explore gate level modeling capabilities Understand PLI capability
Format
Morning Presentations Afternoon Lab Exercises
Timing
Coffee..10.30 to 10.45 & 3.30 to 3..45 Lunch1.00 to 2.00
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Part-I
Designing using Verilog ( RTL Coding )
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SCHEDULE
- Session I
Introduction to Verilog-HDL, Data Types, Operators. Verilog Language Concept, Hierarchy, Concurrency, Timing Continuos and Procedural Assignments
- Session II
Lab 1- Use of Simulation and synthesis Tools Multiplexer, Comparator ,Decoder Using Hierarchy Assignments
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SCHEDULE
- Session I
Verilog Coding styles RTL , Behavioural. Sequential statements - if else, case, for loop, while loop, statements Blocking and Non-blocking statements,Simulation cycle
- Session II
Lab 2 Sequential Logic exercises- Registered logic, timing logic, Counting logic.. Assignments
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SCHEDULE
- Session I
Synthesis Process Structural RTL coding
- Session II
Lab 3 Coding for Finite State Machines Assignments
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SCHEDULE
- Session I
Sample complete design RTL coding Guidelines
- Session II
Lab 4 Use of External IP in design Structural coding Assignments
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Part-II
Verification using Verilog ( Behavioral Coding )
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SCHEDULE
- Session I
Verification Overview, Writing Simple Test benches System Tasks & Compiler directives Use of input and output files Creating self checking test benches
- Session II
Lab 1- Use of Simulation and synthesis Tools Writing Simple Test benches for Multiplexer, comparator,Decoder.. Writing Test bench for Clocked logic
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SCHEDULE
- Session I
Tasks & Functions PLI Overview Creating PLI applications
- Session II
Lab 2 Writing test benches using Tasks Writing test benches for FSMs
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SCHEDULE
- Session I
Sum up
- Session II
Lab 3 Writing structured test benches using I/O files Complete verification of structured model Design Debugging
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Verilog Application
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Verilog Application
Objectives
Identify the advantages of designing with an HDL. Applications of Verilog Define what is meant by levels of abstraction with respect to:
Verilog modeling
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What is Verilog
Verilog is not a software language Verilog is a Hardware Description Language (HDL)
Programming language with special constructs for modeling hardware
Structure
Verilog Supports: Structure

Physical (netlist & hierarchy) Software (subprogram)
Hardware behavior
Serial (sequential) Concurrent (parallel)
b
c
Tpd D Q
s
r Behavior
Tsetup Thold Tclk-q
Timing Abstraction levels

clk
Tnet
Timing
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Levels of Abstraction
Behavioral algorithmic
Register Transfer Level Verilog Gate level -structural -netlist Logic synthesis
Physical -silicon -Switch
Layout / place & Route
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Abstraction Level Example:Divide by 2

Behavioral
data always @ (data) op <= data/2; RTL op
2
4 data 4 op
always @ (posedge clk) op <= data >> 1; Gate Level Netlist
4
clk
SLI
D Q
FD1 opreg2 ( .D(data[3]), .CP(clk), .Q(op[2] ) ); FD1 opreg1 (.D(data[2]), .CP(clk), .Q(op[1] ) ); FD1 opreg0 (.D(data[1]), .CP(clk), .Q(op[0] ) ); FD1 opreg3 ( .D(1b0), .CP(clk), .Q(op[3] ) );
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Benefits of Using an HDL

Design at a higher level. Find problems earlier in the design cycle Explore design alternatives Description is implementation independent. Functional and technology changes are easier to make Decisions on implementation can be delayed longer Flexibility Re-use of design Choice of tools,vendors Text language based Faster design capture Easier to manage
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Applications
Verilog language is used by:
ASIC and FPGA designers writing RTL code for synthesis System architects doing high level system simulations Verification engineers writing advanced tests for all level of simulation Model developers describing ASIC or FPGA cells, or higher level components
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Verilog Based Simulation

waveforms
Testbench behavioral
Design RTL
Compare
High level testbench in Verilog Interacts with design Portable Possibility of automatic checking of function Testbench written in behavioral style Design written in RTL style
Results
Expected results
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Verilog Language Introduction
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Aims and Topics

Objective
Examine fundamental language objects Introduce the main language concepts
Contents
Verilog objects Verilog connection model Hierarchy Rules and regulations
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module
Describes interface and behavior Modules communicate through ports Port names listed in parentheses after the module name. Ports can be defined as input, or inout (bidirectional) îs the exclusive or operator & is an logical and operator module halfadd (a, b, sum, carry); output sum, carry; input a, b; assign sum assign carry endmodule = a^b = a&b
halfadd
a
Important to Remember : Verilog is case sensitive for identifiers keywords must be in lowercase
sum
+
carry
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Representing Hierarchy
Create hierarchy by fulladd Instantiating module n_sum Connecting module ports to a local ports or nets sum U1 U2 Local nets need to be n_carry2 b declared halfadd halfadd The or construct is a built cin carry in gate primitive n_carry1 module fulladd (a, b, cin, sum, carry); Local nets of type input a, b, cin; wire output sum, carry; wire n_sum, n_carry1, n_carry2; halfadd U1 (.a(a), .b(b), .sum(n_sum), .carry(n_carry1) ); halfadd U2 (.a(n_sum), .b(cin), .sum(sum), .carry(in_carry2) ); or U3 (carry1, n_carry2, n_carry1) ; endmodule
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Connecting Hierarchy-Named Port Connection instantiation

Explicitly specifies which
module port is mapped to which local port/wire
module a sum b carry
a b
U1
n_sum n_carry1
module fulladd (a, b, cin, sum, carry); halfadd input a, b, cin; mapped to output sum, carry ; wire n_carry1 wire n_sum, n_carry1, n_carry2 ; of fulladd module .. halfadd U1 (.a(a), .b(b), .sum(n_sum), .carry(n_carry1) ); .. module halfadd (a, b, sum, carry); output sum, carry; input a, b; Output carry of halfadd module endmodule
Tip
Use named port connection For linking hierarchy
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Connecting Hierarchy-Ordered Port Connection Port mapping in order:1st instantiation instantiation port a st module port mapped to 1 2nd instantiation port mapped b to 2nd module port etc
module fulladd (a, b, cin, sum, carry) ; input a, b, cin; output sum, carry; wire n_sum, n_carry1, n_carry2; .. halfadd U1 (a, b, n_sum, n_carry1) ; ..
module
n_sum n_carry1 U1
a sum b carry
halfadd
input a of fulladd mapped to input a of halfadd input b of fulladd mapped to input b of halfadd
module halfadd (a, b, sum, carry) ; output sum, carry ; input a, b ; endmodule
Caution
Less readable and more error-prone than named port connection
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Procedural Blocks (Procedures)

Section containing procedural statements Multiple procedures interact concurrently always procedure Executes when any variable in event list changes value Runs throughout simulation always @ (a or b or sel) if (sel = = 1) y=a; event list else y=b;
1 y
b
sel
0
initial begin a = 1; b = 0; end
initial procedure Executes once at start of simulation Used for initialisation, testbenches
Synthesis
initial blocks are not synthesisable
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Event List
always procedure executes when one or more variables in the event list change value An event is a change in logic value
or is a keyword used in event lists always @ (a or b or sel) begin if (sel = = 1) event list y=a; else y=b; end
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The Verilog Connectivity Model

Multiple procedures interacting concurrently
Executing statements in sequence, like conventional software Communicating concurrently through variables
Procedure
Procedures contained in a module

Or separated into several modules for a hierarchical design
Procedure Procedure
Procedure
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Compilation Library
Some Verilog tools use compilation libraries: A collection of compiled modules or primitives Physical exists as a directory Referred to by library name Simulator startup file specifies mapping
Library name ->directory name
a_clk.v
WORK
PRIMS MY_WORK PROJ
Compile into WORK

WORK mapped to specific library name
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Design Compilation compiled from a list Design

tb_one
testbench of Verilog files Normally compile the testbench first Usually contains compiler directives Provides additional information for the compiler/simulator Order of other files generally not important Hierarchical connections are automatically made Verilog allows different levels of abstraction anywhere in the hierarchy
design
structural
cpu
pnet_read
pnet_write
behavioral RTL/structural behavioral
read_frame
netlist
write_frame
primitives
Comments and Spacing

// This is a line comment. Each line must begin with // // Comments end with a new line module halfadd (a, b, sum, carry) ; output sum, carry ; input a, b ; // End of line comment /* This is a block comment. Text in a block comment can span many lines.*/ // Verilog is a free-format language // Additional spaces can be used to enhance readability assign sum =a ^ b; assign carry = a & b; // use indentation to aid readability and debugging always @ (a or b or sel) if (sel = =1) y = a; else y = b;
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Identifier Naming Rules

Names may consist of any alphnumeric character, including dollar sign ($) and underscore(_) Names must start with a letter or an underscore Verilog identifiers are case sensitive
Keywords must be lowercase
unit_32 structural bus_16_bite a$b unit@32 unit - 32 16_bit_bus
These names do not refer to the same object ABC,Abc,abc Names can be of any length
Tool or methodology may restrict name lengths.
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Verilog Logic System and Data Types
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Aims and Topics

Aims
To introduce the Verilog logic value system and to understand the different data types and the rules covering their use.
Topics
Logic value system Data type classes Vectors and literal values Net data types and their use Choosing the correct data type Parameters Memory arrays
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4-Value Logic System in Verilog

buf
0
buf buf
Zero, Low,False, Logic Low, Ground, VSS, Negative Assertion One,High,True,Logic High, Power, VDD, VCC, Positive Assertion X,Unknown (bus contention), Uninitialized
X
bufifI
Hiz, High Impedance, Tri-State, Undriven, Unconnected, Disabled Driver (Unknown)
Important The unknown logic value x is not the same as dont care.
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Data Types
Verilog objects communicate using variables All variables have a type There are three different classes of data type
Nets
Represent physical connection between structures and objects e.g. wire
Registers
Represent abstract storage elements e.g.reg
Parameters
Run-time constants
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Net Types like a wire driven by a logic gate A Net type behaves
Various net types are available
Wire is the most commonly used Nets not explicitly declared default to type wire
Net values changed with assign in continuous assignments and by modules or primitives in the design
wire sel; wire [31:0] w1, w2 ; wand c; tri [15:0] busa ; // // // // Scalar wire Two 32-bit wires with msb = bit 31 Scalar wired-AND net A 16-bit tri-state bus, msb = bit 15
module halfadd (a, b, sum, carry) ; input a, b; // default to wire output sum, carry ; // default to wire // change with assign assign sum = a ^ b; assign carry= a & b; endmodule
Net types:wire, tri supply1, supply0 wor, trior wand, triand trireg, tri0, tri1
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Wire and assign

a nsela nsel out sel
b
selb Nets module mux (a, sel, b, out); input sel, b, a; output out ; wire nsela, selb, nsel ; assign nsel = ~sel; assign selb = sel & b ; assign nsela = nsel & a; assign out = nsela | selb ; endmodule
wire declaration and assignment can be merged. Remember ports default to wire types Note:~ is an inversion operator
module mux (a, sel, b, out ); input sel, b, a ; output out ; wire nsel = ~sel; wire selb = sel & b; wire nsela = nsel & a ;
assign out endmodule = nsela | selb;
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Logic Conflict Resolution with Nets

If the same net is driven from multiple sources a conflict occurs Net types have a resolution function to determine final value of target y declared as wire y ; tri y ; b a y ? b y declared as wand y ; triand y ; y declared as wor y ; trior y ; assign y = a ; assign y = b ;
b b 0 1 x z a 0 1 x z a a 0 1 x z 0 0 x x 0 0 0 0 0 0 0 0 1 x 0 1 x 1 x 1 1 0 1 x 1 1 1 1 1 1 x x x x x x 0 xx x x x 1 x x z 0 1 x z z 0 1 x z z 01 x x Synthesis wire and tri are synthesisable, some synthesis tools support wor and wand
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Register Types
Register types stores value until a new value is assigned Various register types are available reg is the most commonly used Register values changes with procedural assignment
module mux (a, b, c, sel, op) ; input a, b, c, ; input sel ; output op ; reg op ;
always @ (a or b or sel) begin if (sel = = 1) op = a; Synthesis else reg and integer are synthesisable, but do not op = b; have to synthesis to a flip-flop in hardware end endmodule Register types:reg reg [3:0] vect ; // 4-bit unsigned vector reg [2:0] p, q ; // two 3-bit unsigned vector integer integer i ; // 32-bit signed integer real reg s ; // unsized reg defaults to 1-bit time
time delay ; // time value
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Register Assignment ( a, b, c, sel, mux ) ; module mux

Register types can only be updated from within a procedure Procedures can only update register types Registers and nets can be mixed on the right-hand-side of an assignment Error Net type assigned in procedure Error Register type assigned outside procedure
input a, b, c ; input sel ; output mux ; wire aandb, nmux ; reg mux, nota ; always @ (a or b or sel) if (sel = = 1) begin mux = a ; nmux = b ; end else begin mux = a ; nmux = b ; end assign nota = ~a; assign aandb = a & b ;
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Choosing the Correct Data Type

net/register atop btop
Input Port net a b Output Port net/register net y Inout Port
net ytop
net
module top; wire ytop; reg atop, btop; initial begin atop = 1b0; btop = 1b0; end dut U1 (.a(atop), .y(ytop), . b(btop)); endmodule
module dut (y, a, b) ; output y; input a, b; assign y = a&b; endmodule
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Parameters
Parameters are used to declare run-time constants. Can be used anywhere that you can use a literal. Make code more readable Parameters are local to the module in which they are defined. Can be used to size local variable declarations Including module ports Must be declared before used // parameter list parameter pl = 8, REAL_p = 2.039, X_WORD = 16bx ;
module mux (a, b, sel, out) ; parameter WIDTH = 2; input [WIDTH 1:0] a; input [WIDTH 1:0] b; input sel ; output [WIDTH 1:0] out ; reg [WIDTH 1:0] out ; always @ (a or b or sel) if (sel) out = a; else out = b; endmodule
Overriding the Values of Parameters

parameter NIB = 4: input [NIB-1:0] anib, bnib; input [7:0] abus, bbus; input sel;
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Constant values can be changed for each instantiation of module

module muxs (abus, bbus, anib, bnib, opbus, opnib, opnib1, sel );
module mux (a, b, sel, out); parameter WIDTH = 2; .
output [NIB-1:0] opnib, opnib1; output [7:0] opbus ; // module instantiations for different sized muxes mux # (8) mux8 (.a(abus), .b(bbus), . Sel(sel), .out(opbus) ); mux # (NIB) mux4 (.a(anib), .b(bnib), .sel(sel), .out(opnib) ); mux mux4a (.a(anib), .b(bnib), .sel(sel), .out(opnib1) ); defparam mux4a.width=4; endmodule
Example follows..
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Generic Decoder
module gen_dec (en,a,y); parameter sizein=3, sizeout=8;
module gen_dec_call (ena,enab,adda,addb,decadda,decaddb);

input ena; input enb;
input en; input [sizein-1:0]a; output [sizeout-1:0]y; reg [sizeout-1:0]y; integer i; always @(en or a) begin if(!en) y=0; else if(a > sizeout-1 ) for (i=0;i<= sizeout-1;i=i+1) y[i]=1'bx; else for (i=0;i<= sizeout-1;i=i+1) if(a==i) y[i]=1; else y[i]=0; end
endmodule
input [1:0]adda; input [1:0]addb; output [3:0]decadda; output [3:0]decaddb; gen_dec#(2,4) dec2_4(ena,adda,decadda); gen_dec #(3,8) dec3_8(enb,addb,decaddb); endmodule
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Two Dimensional Arrays

Verilog supports two-dimensional array of registers
reg [15:0 ] mem [0 : 1023] ; integer int_arr [99 :0] ; // 1K x 16-bit 2-d array // Array of integers 100 deep
A array element is addressed by an index to the 2-d array

-You can only reference one element of memory at a time
Multiple words accesses require multiple statements Single bit accesses require an intermediate variable reg [7:0] mem_array [0:255]; // memory array reg [7:0] mem_word; reg membit; mem_word = mem_array [5]; // access address 5 mem_word = mem_array [10]; // access address 10 membit = mem_word [7] ; // access bit 7 of address 10
Synthesis: Two-dimensional arrays generally not synthesisable
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Summary
A net type behaves like a real wire driven by a logic gate Nets not explicitly declared default to type wire Net values changed with assign statement or when driven by a module/primitive
Register types stores value until a new value is assigned Register types do not have to synthesise to a register hardware element Procedural assignment can only be updated with a procedural assignment When assigning integer to reg, sign information is disregarded Registers and nets can be mixed on the right-hand-side of an assignment Module ports are defined as wire by default
Inputs must be net types, but can be driven by nets or registers Inouts must be net types and can only be driven by a net Outputs can be net or a register types, but can only drive a net
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Verilog Operators
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Aims and Topics

Aims -Introduce the operators available in the Verilog language Topics
Operator Type arithmetic bit-wise logical reduction shift relational equality conditional concatenation replication Symbol +-*/ % ~& ^~^ !&& & ^ ~ & ~ ~ ^ << >> < > <= >= == != === !== ?: {} {{ }}
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+ * / %
Arithmetic Operators ( ) ; module arithops

add substract multiply divide modulus
integer ans, int ; parameter FIVE = 5 ; reg [3:0] rega, regb, regc, num ; initial begin rega = 3 ; // 0011 regb = 4b1010 ; regc = 2; // 00010 int = -3 ;
Binary arithmetic is unsigned Integer arithmetic is signed
Synthesis % not synthesisable / only synthesisable if dividend is a power of 2
ans = FIVE * int; // ans = -15 ans = (int + 5) /2; // ans = 1 ans = FIVE / int ; // ans = -1 num = rega + regb; // num= 1101 num = regc + regb; // num= 1100 num = int; // num = 1101 num = regc % rega; // num = 0010 end endmodule
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Bit-Wise Operators
~ not & and or ^ xor ~ ^ xnor ^ ~ xnor Bit-wise operators operate on vectors. Operations are performed bit by bit on individual bits.
module bitwise ( ) ; reg [3:0] rega, regb, regc ; reg [3:0] num ;
initial begin rega = 4 b1001 ; regb = 4 b1010 ; regc = 4 b11x0 ;

num = ~rega; // num num = rega & 0 ; // num num = rega &regb; // num num = rega | regb; // num num = regb & regc; // num num = regb | regc; // num end endmodule = = = = = = 0110 0000 1000 1011 10x0 1110
Note: Unknown bits in an operand do not necessarily lead to unknown bits in the result
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Logical Operators module logical ( );

! not && and or Logical operators are an operand reduction, followed by single bit operation - Vectors containing any 1 reduce to 1b1 - Vectors containing all 0 reduce to 1b0 - Vectors containing any x or z with only 0 reduce to 1bx
parameter FIVE = 5; reg ans ; reg [3:0] rega, regb, regc ; initial begin rega = 4b0011; // reduces to 1 regb = 4b10xz; // reduces to 1 regc = 4b0z0x; // reduces to x ans = ! rega; // ans = 0 ans = rega && 0; // ans = 0 ans = rega | | 0; // ans = 1 ans = rega && FIVE; // ans = 1 ans = regb && rega ; // ans = 1 ans = regc | | 0; // ans = x end endmodule
Unary Reduction Operators

& and or ^ xor ~& nand ~ nor ~ ^ xnor ^ ~ xnor Reduction operators perform a bit-wise operation on all the bits of a single operand. The result is always 1b1, 1b0 or 1bx.
module reduction ( ) ; reg val ; reg [3:0] rega, regb;
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initial begin rega = 4b0100; regb = 4b1111; val = & rega ; val = | rega ; val = & regb ; val = | regb ; val = ^ rega ; val = ^ regb ; val = ~ | rega ; val = ~ &rega; val = ^rega && regb; end endmodule // val = 0 // val = 1 // val = 1 // val = 1 // val = 1 // val = 0 // val = 0 // val = 1 // val = 1
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Shift Operators
> > shift right < < shift left Shift operators perform left or right bit shifts on the operand. Shift is logical 0 is used for extra bits Shifts can be used to implement division or multiplication by powers of two
module shift ( ) ; reg [9:0] num ; reg [7:0] rega ; initial begin rega = 8b00001100;
num =rega >> 1; // num = 0000000110 num = rega >> 3; // num = 0000000001 num = rega << 5; // num = 0110000000
end endmodule zeros added first, then shift by 5 to the left
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Relational Operators
> greater than < less than >= greater than or equal <= less than or equal
The result is: 1b1 if the condition is true
1b0 if the condition is false 1bx if the condition cannot be resolved
module relationals; reg [3:0] rega, regb, regc; reg val ;

initial begin rega = 4b0011; regb = 4b1010; regc = 4b0x10; val = regc val = regb val = regb val = regb end endmodule > rega ; < rega ; >= rega ; > regc ; // // // // val = x val = 0 val = 1 val = x
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Conditional Operator (in, enable, out); module tribuf

? : conditional in out
input in, enable; output out; reg out; always @ (enable or in) out = enable ? In : 1bz; endmodule wire out3; reg out1, out2; always @ (a or b or sel) out1 = sel ? a : b ;
enable
a b sel
Note: sometimes the if else construct may be more readable
out
always @ (a or b or sel) if (sel) out2 = a; else out2 = b; assign out3 = sel ? a : b;
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Concatenation
{ } concatenation Allows you to select bits from different vectors and join them into a new vector. Used for bit reorganization and vector construction e.g.rotates Can used on either side of assignment
module concatenation; reg [7:0] rega, regb, regc, regd, new; reg [3:0] nib1, nib2; initial begin rega = 8 b00000011; regb = 8 b00000100; regc = 8 b00011000; regd = 8 b11100000; new = { regd [6:5], regc [4:3], regb[3:0]; // new = 8 b11_11_0100 new = {2 b11, regb[7:5], rega[4:3], 1 b1}; // new = 8 b11_000_00_1 new = {regd [4:0], regd[7:5]}; // rotate regd right 3 places // new = 8b00000_111 {nib1, nib2} = rega; // nib1 = 4 0000, nib2 = 4 0011 end endmodule
Important
Literals used in concatenation must be sized
Replication
{ { } } replication Replication allows you to reproduce a sized variable a set number of times Can be nested and used with concatenation Syntax is:{ <repetitions> {<variable>} } Important Literals used in replication must be sized 4x rega concatenated with 2x regc [1:0] regc concatenated with 2x regb regc concatenated with 2x 1b1 and replicated 2 times
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module replicate ( ) ; reg rega; reg [1:0] regb; reg [3:0] regc; reg [7:0] bus; initial single bit rega begin replicated 8 times rega = 1 b1; regb = 2b11; regc = 4 b1001; bus = {8{rega}}; // bus = 11111111 bus = { {4{rega}}, {2{regc[1:0] }} }; // bus = 1111_01_01 bus = { regc, {2{regb}} }; // bus = 1001_11_11 bus = {2 {regc[2:1], {2{1b1}}} }; // bus = 00_1_1_00_1_1 end endmodule
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Operator Precedence
Do not rely on Operator Precedence use parentheses
Type of Operators Concatenation / Replication Inversion (Logical / Bitwise) Arithmetic Logical Shift Relational Equality Bit-wise / Reduction Symbols {} {{ }} ! ~ * / % + << >> < <= > >= == != === !== & ~& ^ ^~ ~ && ?: Highest
Precedence
Logical Conditional
Lowest
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Procedural Statements
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Aims and Topics

Aim
To introduce some of the most commonly used procedural statements
Topics
Procedures Procedural statements
if then else case loops
initial versus always Procedures

There are 2 types of procedural block
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reg a, b, zor, zand; initial begin a = 1b1; b = 1b0; end always @ (a or b) begin if (a | b) event list zor = 1b1; else zor = 1b0; if (a & b) zand = 1b1; else zand = 1b0; end
always procedure executes repeatedly throughout the simulation it is triggered by a change of value for any variable in the event list initial procedure executes once at start of simulation begin end must be used for multiple statements within a block Synthesis Initial procedures cannot be synthesized
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Procedural Assignments
Assignments made inside
procedural blocks are called procedural assignments All variables on the left-hand side must be register data-types, e.g. reg Here carry is not declared, and defaults to a 1-bit wire.
module fulladder (out, a, b, cin); input a, b, cin; output [1:0] out; reg sum; reg [1:0] out;
always @ (a or b or cin) begin sum = a ^ b ^ cin; carry = ((a & b) | ( cin & (a ^ b))); out = {carry, sum};
end endmodule
Error carry is a net type-should be declared reg carry;
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Event Control
always procedure executes when one or more variables in the event list change value Synthesis Include all signals read by the block in the event list for the generation of combinational logic
always @ (a or b or sel) begin if (sel = = 1) event list y = a; else y = b; end
Can also use negedge or posedge Execute procedure on a specific edge always @ (negedge clk) of a variable // procedural statements Used for modeling synchronous logic always @ (negedge clk or rst) Synthesis: cannot mix edge and level triggers in // not synthesisable event list
always @ (posedge clk) // procedural statements
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Procedural Blocks within Verilog

module design; wire nsela; wire nsel = !sel; wire selb = sel & b; always @ (nsel or selb) out = nsel | selb;
Procedure
Procedure
assign nsela = nsel & a;

always @ (a or b or sel) begin // procedural statements end
Procedure Procedure
// continuous statements endmodule
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if Statement Example
if is a conditional statement Each if condition is tested in sequence -Condition is boolean expression The first valid test executes that branch Conditions can overlap
module if_example (a, b, c, d, y); input [3:0] a, b, c, d; output [3:0] y; reg [3:0] y; always @ (a or b or c or d) if (d = = 4 b0000) y = a; else if (d <= 4b0101) y = b; else y = c; endmodule
d Synthesis if synthesis to mux structures c b a
0101 d 0000 <= = 0 0 y 1 1 mux mux
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if Statement Syntax
if (CONDITION) begin / / procedural statements end if (CONDITION) begin / / procedural statements end else begin / / procedural statements end if (CONDITION) begin / / procedural statements end else if (CONDITION) begin / / procedural statements end else begin / / procedural statements end
Signal if statement execute procedural statements only if the condition is true.. .. add an unconditional else to execute procedural statements when the if condition is false.. add else if to test further conditions if the first is false -Final else is optional and can be used to indicate default operation Use begin and end to bound multiple procedural statements
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case Statement Example

case is a multiway conditional statement case expression is evaluated and compared against each item in turn -Branch items can overlap -The first item match executes that branch The optional default captures unspecified values In this example, values containing x or z
module case_example (a, b, c, d, y); input [3:0] a, b, c, d; output[3:0] y; reg [3:0] y; always @ (a or b or c or d) case (d) 0 : y = a; 1,2,3,4,5 : y = b; 6 : y = c; 7 : y = c: default : y = 4 b0000; endcase endmodule
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for Loop
Iterates around loop for a specified number of times Loop variable must be declared When loop executed: -Loop variable initialized -Loop statement(s) executed -Loop operation performed -When condition false, loop exits
// for loop expansion tmp = 0 ^ a[0]; // =a[0] tmp = tmp ^ a[1]; tmp = tmp ^ a[2]; tmp = tmp ^ a[3]; Synthesis for loop with fixed limits is synthesisable
module parity (a, odd); input [3:0] a; output odd; reg odd, tmp; integer i; always @ (a) begin tmp = 0; for (i = 0; i <= 3; i = i + 1) tmp = tmp ^ a[i]; odd = tmp; end endmodule
tmp
a[0] a[1] a[2] a[3]
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repeat and while Loops

module multiplier (result, op_a, op_b); input [3:0] op_a, op_b; output [7:0] results; reg [7:0] results; reg [7:0] shift_opa; reg [3:0] shift_opb;
always @ (op_a or op_b) begin result = 0; while (count < 10) shift_opa = op_a; // zero extend left begin shift_opb = op_b; // statements repeat (4) count = count + 1; begin end if (shift_opb[0] ) result = result + shift_opa; shift_opa = shift_opa << 1; // shift left shift_opb = shift_opb >> 1; // shift right end endmodule
repeat loops iterate by the number specified -Number can be literal, variable or expression while loop iterates while the expression is true, or non-zero
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Loop Statement Syntax

for loop requires a loop variable declaration while loop continues while the condition is true repeat iterates the number of times defined by the expression forever loops forever
// loop variable must be declared for (initial, condition, inc_dec) begin // statements end
while (condition) begin // statements end repeat (expression) begin / / statements end forever begin // statements end
Synthesis -for loop synthesizable for fixed range. - repeat synthesizable for fixed repetitions - while generally not synthesizable - forever generally not synthesisable
Unsynthesizable loops used in testbenches and simulation models
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Continuous and procedural statements
Objective: To explain difference between continuous and procedural statements
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Continuous Assignments
They are: continuously driven order independent They: operate on net data type only & reside outside procedures Example: wire a; wire out; .. assign a=x+y; assign out=a+z;
x y
z
a + out
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Multiple Continuous Assignments

Example: wire z; . .. assign z=a+b; assign z=c+d; What would be value on signal z ?
a b c d
+
? +
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Multiple Continuous Assignments
Multiple assignments to single variable are wired together If z is wire type ,then following table resolves value wire/tri | 0 1 x z ----------------------0 | 0 x x 0 1 | x 1 x 1 x | x x x x z | 0 1 x z As per need one can use wand or wor types for resolution|
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Procedure statements execute in sequence or triggered by event occurring on variable in event list
Variables are updated immediately Procedures execute concurrently
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Example: module andor(a,b,z_or,z_and); input a,b; output z_or,z_and; reg z_or,z_and; always @(a or b) begin if(a | b) z_or=1; else procedural assignments z_and=0; if(a & b) z_and=1; else z_and=0; end endmodule
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Multiple Assignments in Procedure

What happens when same variable is assigned in procedure? Ex: . reg z; .. always @(a or b or c or d) begin c z=a+b; z z=c+d; d end Last statement overrides previous assignment.
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Example..
Code the following block:
a
b sel
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Example..
1) always@ (a or b or sel) 2) always@ (a or b or sel) begin begin z=b;//default assig. if(sel) if(sel) z=a; z=a; else end z=b; end Last statement takes effect
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Conditional Assignments
This can be used in either procedural or continuous assignments Procedure containing single if can be replaced by continuous assignments Example: always @(a or b or c or sel) if (sel==0) z=a; else if(sel<= 4b1010) z=b; else z=c; endmodule alternate to above procedure is to use conditional operator
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Conditional Assignment..
always @(a or b or c or sel) z=(sel==0) ? a:((sel<=4b1010) ?b:c);
Using continuous assignment: .. assign z=(sel==0) ? a:((sel<=4b1010) ?b:c);
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Avoid feedback loops

What would happen if you use following code ?
assign z=z+x; Or always @(z or x) z=z+x;
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Avoid feedback loops
Creates feedback loop with zero-delay. Program shall go in infinite loop in simulation and simulation will lock.
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Review
1.What happens if multiple procedural assignment are
made to the same variable? 2. Is a conditional assignment statement continuous, procedural or both ? 3. Why should you not create combinational feedback loops? 4. Code the following hardware using i) a continuous assignment and ii) using a procedure
a[3:0]
+
b[3:0] c[4:0] add
1 0
d[4:0]
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Procedural Statements and the Simulation Cycle
Objective: To explain capabilities of procedures and blocking non-blocking assignments Simulation cycle
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Contents
Blocking Procedural Assignment Non-blocking procedural assignment Simulation cycle Timing control Review
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Procedure and Event Control

Example: 1. always @(a or b or c) begin:adding y=a+b; z=a+c; end 2. always @(posedge clk) if(clr) q <= 0; else q <= d;
Procedures executes whenever any event occurs on variable Procedures can be named
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Blocking Procedural Assignment

Blocking assignment:=
Variable assignment is immediate -before the next statement is executed

Can create problems with some code structures Example..
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Example
Will this segment of code Swap the upper and lower byte contents? .. initial begin byte=8b00001111; #20; byte[3:0]=byte[7:4]; byte[7:4]=byte[3:0]; #20;
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Contents
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Non-Blocking Assignment
Non-blocking assignment:<= Variable update is scheduled -value is calculated and stored -Variable is updated at the end of time slice
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Example
Will this segment of code Swap the upper and lower byte contents? .. initial begin byte<=8b00001111; #20; byte[3:0]<=byte[7:4];//byte[3:0] scheduled to receive 4b0000 byte[7:4]<=byte[3:0];// byte[7:4] scheduled to receive 4b1111 #20; // procedure suspends, scheduled assignments updated and nibbles successfully swapped Yes !!!
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Contents
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Simulation cycle(1)
___ ___
Variable Event list a<=1
___ ___
procedure schedule
module sim_ex(a,m,y,w); Input a; Output m,y,w; Reg m,y,w; Always@ (a or m) begin:p1 m<=a; y<=m; End start Always@ ( m) begin:p2 w<=m; End endmodule
variable at a:m:y:w=0
Assume a,w,m,y all zero a changes from zero to one
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Simulation cycle(2)
___ ___ ____
Variable Event list m<=1
____
module sim_ex(a,m,y,w); Input a; Output m,y,w; Reg m,y,w; always@ (a or m) begin:p1 m<=a; y<=m; End Always@ ( m) begin:p2 w<=m; End endmodule
procedure schedule p1
variable at start a:1,m:y:w:0
a updated from 1b0 to 1b1 Procedure p1 executes Update to m scheduled No change in the value of y
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Simulation cycle(3)
module sim_ex(a,m,y,w); Input a; Output m,y,w; Reg m,y,w;
____ _____ ____ _____

Variable Event list m<=1 procedure schedule p1 p2
always@ (a or m) begin:p1 m<=a; y<=m; End always@ ( m) begin:p2 w<=m; End endmodule
variable at start a:1,m:1y:w:0
m changes value to 1b1 Procedure p1 placed on scheduler list Procedure p2 placed on scheduler list
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Simulation cycle(4)
____ ____ ____ ____
module sim_ex(a,m,y,w); input a; output m,y,w; Reg m,y,w; always@ (a or m) begin:p1 m<=a; y<=m; end always@ ( m)
Variable Event list y<=1

W<=1
procedure schedule
variable values after one delta a:1,m:1y:w:0
Procedure p1 and p2 execute(random) Update to y and w scheduled No change in value for m
begin:p2 w<=m; end endmodule
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Simulation cycle(5)
____ ____ ____
Variable Event list
____
module sim_ex(a,m,y,w); Input a; Output m,y,w; Reg m,y,w; always@ (a or m) begin:p1 m<=a; y<=m; End always@ ( m)
procedure schedule
begin:p2 w<=m; End endmodule
variable values after two deltas a:1,m:1y:1w:1
y and w are updated to 1b1; no more procedures to be executed
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Simulation cycle:summary
Variable Event list a<=1 procedure schedule p1 variable values a:1,m:0 y:0,w:0
module sim_ex(a,m,y,w); Input a; Output m,y,w; Reg m,y,w;

always@ (a or m) begin:p1 m<=a; y<=m; End always@ ( m) begin:p2 w<=m; End endmodule
m<=1
p1 p2
a:1,m:1 y:0,w:0
Y<=1 W<=1
a:1,m:1 y:1,w:1
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Delta cycle and simulation Time

Multiple delta cycles at each point of simulation time
One can specify timing inside procedural blocks Following are three types of timing controls Edge-sensitive timing control:@ regular delay: # level sensitive :wait
Simulation time
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More on blocking and non-blocking assignments
Objectives: Guidelines on usage of blocking and non-blocking assignments
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contents
Blocking and non-blocking assignment-Review Usage in clocked procedures Usage in combinational procedures Mix usage
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Blocking assignment review

Blocking assignment:=
Variable update is immediate -before other statements are executed always @(posedge clk) if(sel) z=a; else z=b;
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Non-blocking assignment review

Non-blocking assignment:<= Variable update is scheduled -after the procedure suspends .. reg q; always @(posedge clk) q<=d; ..
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contents
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Blocking assignment in clocked procedures

What is value of cvar in following segment of code?
initial begin avar=1b1; bvar=1b1; end always @(posedge clk) bvar=avar+1b1; always @(posedge clk) cvar=bvar;
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Blocking assignment in clocked procedures

Blocking assignment can lead to race conditions Specifically when:-variable written in one procedure and read in another -both procedures have same event list In example shown above: -both procedures execute on positive edge of clock -assignments to bvar and cvar are immediate -final value of cvar depends on which procedure is executed first
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Non-Blocking assignment in clocked procedures

Non=blocking assignment avoids race conditions Example:both procedures execute on positive on positive edge of clock assignments to bvar and cvar are scheduled
initial begin avar=1b1; bvar=1b1; end always @(posedge clk) bvar<=avar+1b1;

always @(posedge clk) cvar<=bvar; Use non-blocking assignment for synchronous logic
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Position dependent code

always @(posedge clk)
always @(posedge clk)
begin b=a; c=b; d=c; end

Using blocking signal assignment in clocked procedures can also result in position dependent code
begin d=c; c=b; b=a; end
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contents
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Combinational logic
always @ (a or b) begin m=a; n=b; p=m+n; end Use blocking assignment for combinational procedures
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Combinational logic
always @(a or b or m or n) begin:p1 m<=a; n<=b; p<=m+n; end
Variable event event list a<=1 b<=2 m<=1 n<=2 p<=3 procedure scheduler p1
p1
Non-blocking assignment can be inefficient for combinational logic Specifically when logic contains serial serial behavior or intermediate variables -intermediate variables must be added to event list -procedure will take several delta cycles to reach steady state
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Multiple assignments
always @(a or b or c) begin m=a; n=b; p=m+n; m=c; q=m+n; end
Multiple assignments should be either blocking or non-blocking
always @(a or b or c or m or n) begin m<=a; n<=b; p<=m+n; m<=c; q<=m+n; end

Multiple assignments can be made to a variable within one procedure -last assignment wins for nonblocking
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contents
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Mixed assignments
always @(posedge clk) begin tempa=ip1; tempb=f(tempa); op1<= tempb; end always @(posedge clk)
begin temp=a+b; q<=temp+c; end
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Mixed assignments
Blocking assignments can be used within clocked procedures for temporary variables usage: - assign inputs to temporary variables with blocking assignment -perform algorithm with temporary variables and blocking assignment -assign temporary variables to outputs with nonblocking assignment
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Definition of RTL Code
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AIMS and Topics

AIM
To define that rule and coding guidelines for RTL code, and to give an overview of portability issues
-
Topics
-Combinational Procedures -Clocked procedures
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RTL Style
Combinational Procedure
always @ (a or b or c) begin ... end ...
Clocked Procedure
always @ (posedge clock)
Begin
...
end Tip Non-blocking assignment (<=) should be used
Tip blocking assignment (=) should be used
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Complete Event List

Even List for
combinational logic must contain all variables read within procedure What would the behavior be if sel was missing ?
always @ (a or b or sel) begin if (sel = = 1) y = a; else y = b; end
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Incomplete Event List

Synthesis For combinational logic, include all variables read in event list,
always @ (a or b or sel) begin if (sel = = 1) y = a; else y = b; end
always @ (a or b) a
always @ (a or b or sel)
a
b
sel y
b
sel y
Incomplete Assignments in Combinational Logic
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What is the value of b if ctrl = 0 ?

What hardware would be built it this is synthesized ? How can you avoid this type of hardware ?
module incomplete (ctrl, a, b); input a, ctrl; output b; reg b; always @ (ctrl or a) if (ctrl) b = a; endmodule
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Avoiding Latches
Two ways to avoid latches:Use default statement Add else clause
module completel (ctrl, a, b); input a, ctrl; output b; reg b;
always @ (ctrl or a) begin b = 0; // default module complete2 (ctrl, a, b); if (ctrl) input a, ctrl; b = a; output b; end reg b; endmodule always @ (ctrl or a) begin if (ctrl) Question b = a; which do you think would be best for else a procedure with complex nested if b = 0; / / default end statements? endmodule
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Continuous Assignments
Continuous assignments drive values onto nets -Outputs update simultaneously with any input change -Combinational logic is implied
module orand (out, a, b, c, d, e); input a, b, c, d, e; output out; assign out = e & (a b) & (c d) ; endmodule a b e
out
c d
Rules for the Synthesis of Combinational Logic
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Complete event list Default assignments to prevent latches Use blocking assignments Continuous assignment synthesizes to combinational logic Avoid combinational feedback loops (Functions synthesize to combinational logic)
Functions will be described later
Register Inference in Clocked Procedures

module counter (count, clk); output [3:0] count; input clk; reg [3:0] count; always @ (posedge clk) if (count > = 9) count < = 0 ; else count < = count + 1; endmodule
Sandeepani
Clocked procedures triggered on clock edge Use only posedge/negedge in event list Registers are inferred on all non-blocking assignments in synchronous procedures
count
4
+
4
0 1
sel
Question What is the issue with this counter description?
<
clk
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Resetting Clocked Logic

Synchronous Reset
module counter (count, clk, rst); output [3:0] count ; input clk, rst; reg [3:0] count ; always @ (posedge clk) if (rst) / / active high reset else if (count > = 9) count < = 4 b0 ; else count < = + 4 b1 ; endmodule
Asynchronous Reset
module counter (count, clk, rst); output [3:0] count; input clk, rst; rst [3:0] count; always @ (posedge clk or posedge rst) if (rst) // active high reset count < = 4 b0; else if (count < 9) count < = 4 b0; else count < = count + 4 b1; endmodule
if-else used to add reset to clocked procedure if defines reset behavior First else defines clocked behavior For asynchronous resets, active edge of reset added to event list
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Clocked Procedure Templates

always @ (posedge clk or negedge rst) if (!rst) begin // asynchronous reset behavior end else begin // all synchronous actions end
always @ (posedge clk) if (!rst) begin // synchronous reset behavior end else begin // all synchronous actions end always @ (posedge clk) begin // all synchronous actions end
always procedure Event list only contains: posedge/negedge reset posedge/negedge reset for asynchronous reset Code must follow these templates
TIP
Keep procedures with asynchronous resets separate from procedures with synchronous resets.
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Synchronous Feedback Inferrence

Incomplete assignment in clocked procedure implies synchronous feedback
module dffn (q, d, clk, en); input d, clk, en; output q; reg q; always @ (posedge clk) if (en) q < = d; endmodule
d en clk
0 1
mux
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Clocked Procedure Assignment

a b c
clk
Question How would you code this design in Verilog?
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Blocking and Non-blocking Assignment

1
always @ (posedge clk) begin c < = b; b < = a; end always @ (posedge clk) begin c = b; b = a; end
always @ (posedge clk) begin b < = a; a < = b; end
always @ (posedge clk) begin b = a; c = b; end
Easier to use non-blocking assignment to infer registers in synchronous procedures Order independent Register inferred for each assignment
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The Synthesis Process
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AIMS ANDS TOPICS

* AIMS - To introduce synthesis process and look at its strenths and weaknesses * TOPICS - How a synthesis tool works - Synthesis based methodology - Synthesis strengths and weakness - Programmable Logic device synthesis issues - Language subsets
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clk
WHAT DOES SYNTHESIS DO?

* Infers registers from cloked procedures * Builds optimized combinational logic * A new engineer task: - How much of it? - How well? - Do you trust it?
Verilog code Synthesis flow
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Constraints File
Technology library Synthesis Engine
* Verilog code is the important input - the quality of results depends mainly on the code * Technology Library is used to build the circuit from the verilog description * Constraints File drives the synthesis engine
area/Speed Curve
Schematic
Gate Level Netlist
Area
How Synthesis works

Constrains file
Boolean Mapping
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Verilog code
Parsing
Technology Library
Gates
Optimization
Gate Level Netlist
Schematic
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clk
Coding Styles Affect Results

* Number of registers - Combinational logic optimised only, not register numbers or placement * Amount of combinational logic inbetween registers - Pipelining and logic timing mut be considered when code written * structure of .logic
Translation Can Be Literal!
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* Synthesis tools generate logic directly from the structure of your code -Here == operator is redundant but may still appear in the synthesized netlist 011
d
always @ (posedge clk) if (d < 3) y <= a; else if (d > 3) y <=b; else if (d == 3) y <= c; d = > 011 d < 0 1 mux y 011
?
c b
0
1 mux 0 1mux
a ? Question What would be the input at ? clk

Inferred hardware structure
What Synthesis Sometimes Cant Do Well..
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* Clock trees - Usually require detailed, accurate net delay information * Complex clocking schemes - Synthesis tools prefer simple single clock synchronous designs * Memmory, IO pads, technology -specific cells - You will probably need to instantiate these by hand * Specific macro -cells * Always as well as you can - Although it can analyze hundreds of implementations in the time taken for designer to analyze one
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Programmable Logic Device Specific Issues

* Different architectures for different technologies * Fixed architecture within a specific technology * Architecture specific tricks for good utilization and speed * Code becomes technology specific * How your synthesis tool handles your technology
change code
A Synthesis Methodology
Change constraints file
netlist
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constraints
tech library
synthesis
y meets area/speed? functional? y gate simulation
verilog
rtl simulation testbench change code compare golden results
results
Language Support
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* Synthesizeable Verilog is a subset of the full language * There is no standard for synthesizeable code * Diferent tool vendors have slightly different interpretations of what is synthesizeable
Synthesis Subset
Tool1 Tool2 Tool3 Tool4 Tool5
Full Verilog Language
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Summary
* RTL for synthesis
* Logic and gate optimization * Coding style affects results * Synthesis tools support subsets of language style
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Verilog Coding Guidelines
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Blocking and nonblocking statements Coding guidelines Coding for Performanance(Examples)
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Blocking and non-blocking assignments

Guidelines
Use blocking assignments in always blocks that are written to generate combinational logic Use nonblocking assignments in always blocks that are written to generate sequential logic
Ignoring these guidelines can result in a mismatch between behavior of synthesized circuit and the pre-synthesis simulation results
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Comparison
Evaluation of blocking statements requires less simulator memory Evaluation of Non blocking statements requires more simulator time
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Coding Guidelines
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Guideline 1
To model combinational logic within an always block, use blocking statements
always @(a or b or c) temp = a & b; out = c & temp; endmodule
temp
out
b c
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Guideline 2
In order to model sequential logic, use non-blocking assignment statements
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Guideline 3
In order to model latches, use nonblocking statements
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Whats wrong with this block?

always @(test or PC or AluOut) begin if (select) begin output = PC; end else begin output = AluOut; end end
Hint: Look at the sensitivity list.
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Sensitivity List
A signal that appears on the right-hand side of a combinational always block must appear in the sensitivity list of the always block. The only exceptions here are signals that are also generated in the always block (are on the left-hand side).
Verilog only evaluates always blocks only when a signal in the sensitivity list changes.
always @(a or b or c) temp = a & b; out = c & temp; endmodule
Sandeepani
Whats wrong with this block?

always @(select or PC or AluOut or IR1 or add3) begin if (select == 2'h0) begin output1 = PC; PC output2 = add3 end else if (select == 2'h3) begin output1 = AluOut; output2= IR1; 2 end end select IR1 add3 AluOut
Selector
output1
output2
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If/Case construct in Combinational always block
Each left-hand side signal must be assigned in every possible case. If it is not assigned to in one of the cases, then you have "implied a latch" -- there is some set of inputs for which this gate does not take on a new value and therefore "holds" its old value. No longer a combinational logic element!
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Correct implementation
always @ (select or PC or AluOut or IR1 or add3 or output1 or output2) begin if (select == 2'h0) begin output1 = PC; output2 = add3 end else if (select == 2'h3) begin output1 = AluOut; output2= IR1; end else begin output1 = output1; output2 = output2; end end
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Whats not good here?

always @(posedge CLK) begin Q <= `TICK D; Z <= `TICK (a ^ b) & (sig1 | sig2); end
a b sig1 sig2
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More readable code

wire nextZ; assign nextZ = (a ^ b) & (sig1 | sig2); always @(posedge CLK) begin Q <= `TICK D; Z <= `TICK nextZ; end
Q Z nextz
a b sig1 sig2
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Add comments in your code

Others can read and understand your design You can understand your design after 3 months when you may have to debug the design! Make sure that you modify the comments if you are modifying the design! If you are modifying someone elses code, add comments regarding what modification you made and the date of modification. Do not delete old code; comment it. Learn to write simple and helpful comments.
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Indentation
Indent your code. Proper indentation makes your code easier to read and debug. Indentation also forces you to write better code: levels of nesting will be in kept in check!
Sandeepani
`define statements
Do not use hardwired constants all over the place; instead, use meaningful names.
if (opcode == 6b`000010) then begin end else if (opcode = 6b`000011) then begin end
`define ADD 6b`000010 `define SUB 6b`000011 if (opcode == ÀDD) then begin end else if (opcode = `SUB) then begin end
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Examples of coding style
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Priority Encoder
module my_if (c, d, e, f, s, pout); input c, d, e, f; input [1:0] s; output pout; reg pout; always @ (s or c or d or e or f) begin : myif_pro if (s == 2'b 00) begin pout <= c; end else if (s == 2'b 01 ) begin pout <= d; end else if (s == 2'b 10 ) begin pout <= e; end else begin pout <= f; end end endmodule // module my_if
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Multiplexer
module mux (c, d, e, f, s, muxout); input c, d, e, f; input [1:0] s; output muxout; reg muxout; always @ (s or c or d or e or f) begin : mux1 case (s) 2'b 00: begin muxout <= c; end 2'b 01: begin muxout <=d; end 2'b 10: begin muxout <= e; end default: begin muxout <= f; end endcase end endmodule // module mux
c d e f
Sandeepani
Multiplexer vs Latch
a y b
if (select) y = a; else y = b;
select
if (select) y = a;
Sandeepani
Register with Asynchronous Reset
data
module dff_async_reset (data, clk, reset, q); input data, clk, reset; output q; reg q; always @ (posedge clk or negedge reset) if (~reset) q = 1 b0 else q = data; endmodule
clk reset
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Clock-triggered Flip-flop with Enable control

module ff_clk (d, en, clk, clr, q); input d, en, clk, clr; output q; reg q; always @ (clk or clr) begin if (clr == 1'b 0) begin q <= 1'b 0; end else if (clr & clk == 1'b 1 ) begin if (en == 1'b 1) begin q <= d; end end end endmodule / / module ff_clk
clk en clr
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Resource Sharing:I
A + if (select) sum <= A + B; else sum <= C + D;
B
Mux sum C +
select
We are sharing the multiplexer.
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Resource Sharing:II
A mux
B
select C + sum
mux select
if (select) begin temp1 <= A; temp2 <= B; end else begin temp1 <= C; temp2 <= D; end sum <= temp1 + temp2;
We are sharing the adder.
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Resource Sharing:III
vsum +
mux 0
Offset[0]
0 Offset[1]
mux
vsum = sum; for (i=0;i<3;i++) begin if (req[i]=1b1) begin vsum <= vsum + offset[i]; end; end loop;
0 Offset[2]
mux
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Resource Sharing:IV
mux vsum
R
+
mux
0
Offset[0] Offset[1] Offset[2]
Can we rewrite to code to generate hardware that looks like this?
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Code that forgets performance

sum := start; for (i=0;i<2;i++) begin sum <= sum + inc[i]; end;
+
inc[1]
inc[2]
start inc[0]
sum
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Performance-oriented coding
start inc[0]
sum = ((inc[2] + inc[1]) + ((inc[0] + start));
+
+
inc[1]
sum
+
inc[2]
Loop Unrolling performed by designer!
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Overchecking for conditions can increase hardware

data_in data_out
clk en
always @ (posedge clk) begin if (req == 4'b1000) data_out <= data_in; end end
req
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Simplifying the code

data_in data_out
always @ (posedge clk) begin if (req(3) == 1'b1) data_out <= data_in; end end
clk en req[3]
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Optimization in case statements

always @ (posedge clk) begin if (req) begin case (r) 5'b00001: c <= a(0); 5'b00011: c <= a(1); 5'b00101: c <= a(2); 5'b00111: c <= a(3); 5'b01001: c <= b(0); 5'b01011: c <= b(1); 5'b01101: c <= b(2); 5'b01111: c <= b(3); default: c <= 1'bx; end case end
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How can we obtain this hardware instead?
a[3:0]
8-to-1 mux
c DFF
r[4] r[0]
b[3:0]
clk
r [3:1]
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Summary
Synthesis is still an evolving art
Unless you describe exactly what you want, the synthesizer will misunderstand you!
Following a set of guidelines will help Good coding styles will help you and the synthesis tool
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Finite State Machines
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Topics
FSM Basics Steps for FSM design Example design HDL code for FSM
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Any Sequential Logic Circuit is a State Machine

Single flip-flop has two states - `0`, `1` A circuit with 2 flip-flops can have a maximum of 4 states. n flip-flops can have 2n states.
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Flip Flip as an FSM
CLK
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Simple Transition Sequence

Sequential circuits like counters and shift registers have a fixed transition sequence Counters - 00000, 00001, 00010, 00011 each count is a state, total 25 Shift Registers - 00001, 00010, 00100, each shift position is a state, total 5
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Complex trasitions
Coin collection FSM
TO 00p 25p 50p 75p 100p Possible Possible Possible 00p
Possible Possible Possible 25p
Possible Possible 50p FROM
Possible 75p
100p
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What is an FSM?
Design Specification Point of View
State machines are a means of specifying sequential circuits which are generally
complex in their transition sequence and depend on several control inputs.
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What is an FSM?
Digital Circuit Point of View
State machines are a group of flip-flops, whose group-state transition pattern (from one set of values to another ) is
generally unconventional and depends on several control inputs
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FSM Structure
COMBINATORIAL ACTION PORTS CURRENT STATE COMB. LOGIC for NEXT STATE NEXT STATE CURRENT STATE
CONTROL INPUTS
STATE REGISTER FLIP-FLOPS REGISTERED ACTION PORTS
CLOCK ASYNC CONTROL
PORTS
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FSM Design Steps

Define the ports Define the states Define transitions and conditions Define the actions Write code for synthesis
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State Machine: State Diagram

01 = 1bo 01 =1 bo
A
3b000
b=1 b 1
a= 1b1
01 =1b0 02 =1b0
B
3b001
3b011
b= 1b o
{a, b} = 2b11 a= 1b0

3b010
01 = 1b1 02 = 1b1
{a ,b}=2b01
a =1b1
State Names (A,B,C,D,E,) State encoding: A=3 b000, B=3b001 Transition Conditions: {a ,b}=2b01 Output values: 01=1b0
01 = 1b0 02 = 1b0
3b110
01= 1b0 02= 1b1
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State Machine: Declarations and Clocked Procedure

Use parameters for state encoding
Reset strategy for state register Partition into clocked procedure and combinational procedures
State register
Output Logic 01 02
a b
Next State Logic state Next_state
module fsm (a, b, clock, reset, 01, 02); input a, b, clock, reset; output 01, 02 ; // parameter declarations (state encoding) parameter A = 3b000, B = 3b001, C = 3b011, D = 3b010, E = 3b110; // wire and reg declarations reg [2:0] state, next_state ; reg 01, 02 ; // clocked procedure always @(posedge clock or posedge reset) begin: STATEREGISTER if (reset) state < = A; else state < = next_state ; end
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State Machine: Declarations and Clocked Procedure

Use parameters for state encoding
Reset strategy for state register Partition into clocked procedure and combinational procedures
State register
Output Logic 01 02
a b
Next State Logic state Next_state
module fsm (a, b, clock, reset, 01, 02); input a, b, clock, reset; output 01, 02 ; // parameter declarations (state encoding) parameter A = 3b000, B = 3b001, C = 3b011, D = 3b010, E = 3b110; // wire and reg declarations reg [2:0] state, next_state ; reg 01, 02 ; // clocked procedure always @(posedge clock or posedge reset) begin: STATEREGISTER if (reset) state < = A; else state < = next_state ; end
State Machine: Combinational Procedures

always @ (a or b or state) begin: NEXTSTATE next_state = state ; case (state) A : begin if (a) next_state = C; else if (b) next_state = B; end B: begin if (~b) next_state = A; else if ( { a,b} = = 2b01) next_state = D; end C: begin if (a) next_state = E; else if ( {a,b} = = 2b11) next_state = D; end D:next_state = A; E: if (~a) next_state = C; end // end next state logic
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always @ (state) begin: OUTPUTDECODE // DEFAULT ASSIGNMENTS 01 = 1b0 ; 02 = 1b0 ; case (state) B: begin 01 = 1b1; 02 = 1b1; end E: 02 = 1b1; end end // end output decode logic
Next state and output decode combinational procedures could be merged Next state and state register procedures could be merged
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If Synthesis
module if_example (a, b, c, ctrl, op); input a, b, c; input [3:0] ctrl ; output op; reg op;
always @ (a or b or c or ctrl) if (ctrl) = = 4b0000) op = a; else if (ctrl < = 4b0100) op = b ; else op = c ;

endmodule
Question Draw the architecture of hardware that this represents.
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If and Case Architectures

if (ctrl = = 4b0) op = a ; else if (ctrl < = 4d4 ) op = b ; else op = c ; if synthesis c b a ctrl case (ctrl) 0: 0,1,2,3,4 : default: endcase op = a; op = b; op = c;
o
ctrl
<=
4
Question What hardware structure is created for a case statement? 1 op Depends if case statement is parallel or not!
=
0
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Case statement allowed to have overlapping choices

Choices prioritized in order of appearance
Case Synthesis
Some synthesis tools infer priority encoder structure

Even for cases with no choice overlap
Case with mutually exclusive choices can be built

with non-prioritized logic
case (ctrl) 0; 0, 1, 2, 3, 4 : default endmodule
op = a ; op = b ; op = c ;
Prioritized case synthesis ctrl c b a

<= 4 ctrl 0 1
case (ctrl) 0: op = a ; 1, 2, 3, 4 : op = b ; default : op = c ; endcase
=
0
1 op
Parallel Case Statement

Case with mutually exclusive choices known as parallel case Can be implemented with non-prioritized logic Most synthesis tools can recognize parallel case Others may need to be told case is parallel Directives can be used to control synthesis Embedded comments which are recognized by synthesis Important Never apply directive to a nonparallel case Tip: If your synthesis tool supports it, create parallel case by design not by directive
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case (ctrl) 0: op = a ; 1, 2, 3, 4 : op = b ; default : op = c ; endcase case (ctrl) // rtl_synthesis parallel_case 0: op = a ; 1, 2, 3, 4 : op = b ; default op = c ; endcase
ctrl
c <
5 ctrl
>
5
op parallel case synthesis
Synthesis Directives
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Most synthesis tools handle directives or programs Directives are verilog comments, ignored by simulation but meaningful to synthesis
Aim is to control synthesis optimization from within the RTL code.
case (test) // rtl_synthesis parallel_case 2b00: op = 1 ; 2b01, 2b10: op = 2 ; 2b11: op = 3 ; default : // rtl_synthesis off $ display (unknown test!); // rtl_synthesis on endcase
$display writes a message to the simulator transcript window Caution Can lead to different RTL/Gate level functionality from Same design use With caution!
Casez Synthesiscasez is treated similar to

always @ (pri_in) begin casez (pri_in) 4 b1??? : op = 3 ; 4 b01?? : op = 2 ; 4 b001? : op = 1 ; 4 b0001 : op = 0 ; default : op = 0 ; endcase end always @ (ctrl) begin {int0, int1, int2 } = 3 b000 casez (ctrl) 3 b?/1 : int0 = 1 b1 ; 3 b?1?: int1 = 1 b1 ; 3b1?? : int2 = 1 b1 ; endcase end
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case by the synthesis tool casez can be parallel or non-parallel

Parallel casez will synthesis to parallel logic Non-parallel casez will synthesize to prioritized logic
Synthesis tool may need to be told casez is parallel
Important Make sure casez actually is parallel before using directives
Question
Are these casez statements parallel or not?
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Full Case
// declarations for examples module case_1 (b, c, ctrl, op) ; input [3:0] b, c ; input [1:0] ctrl ; output [3:0] op ; reg [3:0] op always @ (ctrl or b or c) case (ctrl) 0, 1 : op = b ; 2 : op = c ; endcase
Case branches do not need to cover all values for case expression
Can cause incomplete assignments in combinational code. -Will synthesze latches
Full case (for synthesis) covers all binary values of case expression.
Ignoring x and z value combinations
always @ (ctrl or b or c) case (ctrl) 0, 1: op = b ; 2: op = c ; default : op = 0 ; endcase
case not fulllatches inferred
always @ c(ctrl or b or c) case (ctrl) 0, 1 : op = b ; 2 : op = c ; 3 : op = 0 ; endcase
default makes full case for synthesis and simulation Full case for synthesis
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Full Case Directive

always @ (ctrl or b or c) //rtl_synthesis full_case case (ctrl) 0, 1 : op = b ; 2, 3 : op = c ; endcase
Caution
Make sure case actually is full before using directives
always @ (ctrl or b or c) begin op = c ; case (ctrl) 0, 1 : op = b ; 2 : op = c ; endcase end
Most synthesis tools can recognize full case Others may need to be told case is full Can use synthesis directive to force full case What happens if directive applied to case description which is not full? Assumes missing case values can be implemented as dont care Can cause RTL to gate level simulation mismatches Full case issue avoided if default assignments used
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Case Directive Exceptions

A full case statement can still synthesize latches
Even if the full_case directive and default option are used
Incomplete assignments can occur for any variable assigned to in a combinational procedure.
Default statements can prevent problems
module select (a, b, sl ) ; input [1:0] sl ; output a, b ; req a, b ; always @ (sl) case (sl) // rtl_synthesis full_case 2 b00 : begin a = 0 ; b = 0 ; end 2 b01 : begin a = 1 ; b = 1 ; end 2 b10 : begin a = 0 ; b = 1 ; end 2 b11 : b = 1 ; default : begin a = bx; b = bx; end endcase endmodule
Question There is latch inferred from this code. What is the name of the latches variable and how can it be prevented?
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Initial Statements
module counter (clk, q ) ; input clk ; output [ 3 : 0 ] q ; reg [3:0] q: initial q = 0 ; always @ (posedge clk) if (q > = 9) q < = 4 b0 ; else q <= q+1;
module counter (clk, rst, q ) ; input clk, rat ; output [3 : 0] q ; reg [3 :0] q ; always @ (posedge clk) if (rst) q < = 4 b0; // synchronous reset else if (q >= 9) q < = 4 b0; else q<=q+1; endmodule
endmodule
Question Synthesis What does this initial statement mean: Synthesizable equivalent-add 1.For simulation? reset 2.For synthesis?
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Summary
FSM is a systematic way of specifying any sequential logic Ideally suited for complex sequential logic Translating the problem in terms of discrete states is the difficult part Define the FSM and generate the code
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Structural Modeling
Aims and Topics
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* Aims - Learn about the full capabilities of verilog for structural ,gate level modeling and modeling memories * Topics - Built in primitives - Modeling memories
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Structural Modeling
* Pure structural model only contains instantiated modules, primitives and wire connections * Used for block diagrams, schematics, post synthesis netlist and ASIC/FPGA a nsela sel
nsel
selb
out module mux (a, sel, b, out); input a, sel, b; output out; wire nsela, selb, nsel; OR2 U32(.A(nsela), .B(selb), .Z(out) ); IV U33 (.A(sel), Z(nsel) ); AN2 U34 (.A(a), .B(nsel), .Z(nsela) ); AN2 U35 (.A(b), .B(sel), .z(selb) );
Conditional Primitives
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* Four different types of conditional primitives * Conditional primitives only have three pins: output, input and enable * Enabled and disabled by the enable pin - When disabled outputs are at high impedance Primitive Name bufif1 bufif0 notif1 notif0 Functionality Conditional buffer with logic 1 as enabling input Conditional buffer with logic 0 as enabling input Conditional inverter with logic 1 as enabling input Conditional inverter with logic 0 as enabling input
Conditional Buffers
bufif1
data out data
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bufif1
out
enable
bufif1(out, data, enable) enable bufif1 0 data 1 x z 0 z z z z 1 0 1 x x x L H x x z L H x x
enable
bufif1(out, data, enable) enable bufif0 0 1 x z 0 0 1 x x 1 z z z z x L H x x z L H x x
note : Verilog uses the symbols L and H to represent partially unknown logic values
Modeling a Memory Device
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A memory device must do two things : * Declare a memory of appropriate size * Provide some level of access to its contents, such as : - Read only - Read and Write - Write and Simultaneous read - Multiple reads , simultaneous to a single write - Multiple simultaneous reads and writes, with some method of ensuring consistency
Simple ROM Model

timescale 1ns / 10ps module myrom (read_data, addr, read_en_); input read_en_; input [3:0] addr; output [3:0] read_data; reg [3:0] read_data; reg [3:0] mem [0:15]; initial $readmemb (my_rom_data, mem); always @ (addr or read_en_) if (! read_en_) read_data = mem[addr]; endmodule
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my_rom_data 0000 0101 1100 0011 1101 0010 0011 1111 1000 1001 1000 0001 1101 1010 0001 1101
ROM data is stored in a separate file
Simple RAM Model
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module mymem (data, addr, read, write); inout [3:0] data; input [3:0] addr; input read , write; 4 bit , 16 word array for reg [3:0] memory [0:15]; memory contents // read assign data = (read ? memory [addr] : 4bz); // write always @ (posedge write) tr i- state controller memory[addr] = data; enabled by read endmodule
rising edge triggered RAM write
Note :Simultaneous models for internal RAM/ROM usually supplied by technology vendor
Scalable Memory device

* Parameters can be used to scale memory models
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module scalable _ROM (mem_word, address); parameter addr_bits = 8; size of address bus parameter wordsize = 8; width of memory word parameter words = (1 << addr_bits); size of memory output [wordsize : 1] mem_word; input [addr_bits : 1] address; reg [wordsize : 1] mem [0 : words - 1]; // output one word of memory wire [wordsize : 1] mem_word = mem[address]; endmodule output word
address bus memory declaration continuous assignment to output
Loading a Memory
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* ROM will need to be loaded with data * RAM may need to be initialzed * Memory can be pre - loaded via loops or from an external file
// initialize memory via loop for (i = 0 ; i< memsize ; i = i+1) mema [i] = {wodsize {1 b0}};
// load memory from a file $ readmemb (mem_file . txt, mema);
Using inout Ports

module mymem (data , addr , read , write); inout [3 : 0] data; input [3 : 0] addr; input read, write; ............. assign data = (read ? memory[addr] : 4 bz); ...................
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* Bi - directional ports are declared with the inout keyword * You can not directly connect an inout port to a register * Your design should drive an inout port from only one direction at a time - To avoid bus contention - You must design logic around the inout port to ensure proper operation
Bidirectional Ports Using Primitives

en_a_b
bus_a b2 b1 bus_b en_b_a
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module bus_xcvr(bus_a , bus_b, en_a_b, en_b_a); input bus_a, bus_b; When en_a_b = 1, input en_a_b , en_b_a; primitive b1 is enabled bufif1 b1 (bus_b , bus_a , en_a_b); and the value on bus_a bufif1 b2 (bus_a , bus_b , en_b_a); is transferred to bus_b //structural module logic endmodule When en_b_a = 1, primitive b2 is enabled and the value on bus_b is transferred to bus_a
Bidirectional Ports Using Continuos Assignment en_a_b b1 bus_a b2 bus_b en_b_a
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module bus_xcvr(bus_a , bus_b, en_a_b, en_b_a); input bus_a, bus_b; When en_b_a = 1, input en_a_b , en_b_a; this assignment drives assign bus_b = en_a_b ? bus_a : bz; the value of bus_b assign bus_a = en_b_a ? bus_b : bz; on to bus_a //structural module logic endmodule When en_a_b = 1, this assignment drives the value of bus_a on to bus_b
Modeling Memory Ports

Test Bench rd data bus wr module ram_cell (databus, rd, wr); input databus; input rd, wr; reg datareg; assign databus = rd ? datareg : bz; always @ (negedge wr); datareg <= databus; endmodule
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RAM cell
data reg
when rd = 1 the value of datareg is assigned to databus When wr deasserts the value of databus is writteb to datareg
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Gate level Modeling
Aims and Topics

* Aims - Understand how to model simple delays for simulations and gate level models * Topics - Lumped delays - Distributed delays - Path delays - Specify timing blocks
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Delay Modeling Types

noror ASIC cell
a b n1 net1 1
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Lump the entire delay at the last gate
o1
out
2 distribute the delay across each gate Typical delay specification Delays can be modeled in three ways : delay from a to out =2 delay from b to out = 3 delay from c to out = 1
3 Use a specify block to specify pin-to-pin delays for each path
Lumped Delay
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* Lumped delays place entire delay on the last gate -Simple to implement - Does not allow for different path delays a b path delay as modeled a -> out is 3 out b -> out is 3 c #3 c -> out is 3
timescale 1ns / 1ns module noror (out, a, b, c); output out; input a, b, c; nor n1 (net1, a, b); or #3 o1 (out, c, net1); endmodule
Distributed Delays
* distributed delays divide delay over more than one gate - Allows different delays for different paths - Delays accumulate along the path a b #2
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#1
path delay as modeled a -> out is 3 out b -> out is 3 c -> out is 1
timescale 1ns / 1ns module noror (out, a, b, c); output out; input a, b, c; nor #2 n1 (net1, a, b); or #1 o1 (out, c, net1); endmodule
Module Path Delays

* Specify block allows individual path delay to be defined - Paths from the inputs to outputs of a module a b n1 net1
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o1
path delays a -> out is 2 out b -> out is 3 c -> out is 1
The Specify Block

module noror (out, a, b, c); output out; input a, b, c; nor n1 (net1, a, b); or o1 (out, c, net1); specify (a => out) = 2; (b => out) = 3; (c => out) = 1; endspecify endmodule
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* Specify block defines module timing data - Separates timing information from functionality * Typical tasks for specify block: - Define module timing paths - Assign delays to those paths - Perform timing checks * Module parameters can not be used in a specify block - Specify blocks use a special specify parameter (specparam) - See later .............
Specify Block Parameters

Module noror (op. a, b, c); output op; input a, b, c; nor n1 (net1, a, b); or o1 (op, c, net1); specify
Sandeepani
specparam aop = 2; bop = 3; cop = 1; (a => op) = aop; (b => op) = bop; (c => op) = cop; endspecify endmodule
* Specparam declares parameters for specify block * Must be declared inside specify block - Only visible inside block * Cannot be over-ridden like parameters * Parameters cannot be used inside a specify block - Must use specparam
Accurate Delay Control
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*Rise, fall and turn-off delays can be specified for gates and module paths - Rise is transition to 1 - Fall is transition to 0 - Turn-off is transition to z
and # (2, 3) (out, in1, in2, in3); // rise, fall bufif0 #(3, 3, 7) (out, in, ctrl); // rise, fall. turn-off spacify (in => out) = (1, 2); // rise, fall (a = > b) = (5, 4, 7); // rise, fall, turn-offs endspecify
* Minimum , typical and maximum values can be specified for each delay - Syntax - (minimum : typical : maximum)
or # (3 . 2 : 4 . 0 : 6 . 3) o1 (out, in1, in2); // min : typ : max not # (1 : 2 : 3, 2 : 3 : 5) (o, in); // min : typ : max for rise, fall specify // min:typ:max for rise, fall and turn-off (b => y) = (2 : 3 : 4, 3 : 4 : 6, 4 : 5 : 8); endspecify
Parallel and Full Connection Module PathsSandeepani

* => represents parallel connection - Must be between ports must be of the same size * * > represents full connection - All listed inputs connect to all listed outputs Full module path Parallel module path q output q output input a input a bits b bits bits b qb bits qb 2 paths 4 paths Bit - to - bit connections Bit - to - vector connections Use => to define path Use *> to define path (a, b *> q, qb) = 15; (a, b => q, qb) =15; is equivalent to is equivalent to (a => q ) = 15; (a => q ) = 15; (b => q ) = 15; (b => qb ) =15; (a => qb ) = 15; (b => qb ) = 15;
State Dependent Path Delays
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* State dependent path delay are assigned to module path only if a specific condition is true - Note : not an if statement - no else is allowed....
module jexor (op, a, b); input a, b; output op; xor (op, a, b); specify if (a) (b => op) = (5 : 6 : 7); if (!a) (b => op) = (5 : 7 : 8); if (b) (a => op) = (4 : 5 : 7); if (!b) (a => op) = (5 : 7 : 9); endspecify endmodule
op
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User Defined Primitives
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AIMS AND TOPICS

Aims
* Learn how to build logic using user defined primitives
Topics
* Understand verilog composite libraries * Understand functional modeling of ASIC libraries * Learn about the use of UDPs in ASIC library models
WHAT IS A UDP ?
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Verilog has over two dozen gate level primitives for modeling structural logic . In addition to these primitives Verilog has user defined primitives (UDPs) that extend the built in primitives by allowing you to define logic in tabular format. UDPs are useful for ASIC library cell design as well as small scale chip and medium scale chip design * You can use UDPs to augment the set of predefined primitive element s * UDPs are self contained , they do not instantiate other modules * UDPs can represent sequential as well as combinational elements * UDP behavior is described in a truth table * To use a UDP you instantiate like a built in primitive
FEATURES
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* UDPs can have only one output * UDPs can have 1 to 10 inputs * All ports must be scalar and no bi-directional ports are allowed * The Z logic value is not supported * The output port must be listed first in the port list * The UDP output terminal can be initialized to a known value at the start of simulation * UDP can not be synthesized
COMBINATIONAL EXAMPLE : 2 - 1 MULTIPLEXER Sandeepani The output port must be the This is the first port name of the primitive multiplexer (o, a, b, s); primitive output o; input a, b, s; table // a b s : o 0 ? 1 : 0; 1 ? 1 : 1; ? 0 0 : 0; ? 1 0 : 1; 0 0 x : 0; 1 1 x : 1; These entries endtable reduce pessimism endprimitive
* UDP definitions occur outside of a module * The output becomes x for any input combination not specified in table
COMBINATIONAL EXAMPLE : FULL ADDER
Sandeepani
Cin A B
G1
G2 G4
Sum
G5
G3
Cout
Cin A B
U_ADDR2_S
Sum
U_ADDR2_C
Cout
You can implement the full adder with only two combinational UDPs cont........next...
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//FULL ADDER CARRY- OUT TERM primitive u_addr2_c (co, a, b, ci); output co; input a, b, ci; table a b ci : co 1 1 ? : 1; 1 ? 1 : 1; ? 1 1 : 1; 0 0 ? : 0; 0 ? 0 : 0; ? 0 0 : 0; endtable endprimitive
//FULL ADDER SUM TERM primitive u_addr2_s (s, a, b, ci); output s; input a, b, ci;
table // a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 ci : 0 : 1 : 0 : 1 : 0 : 1 : 0 : 1 : s 0; 1; 1; 0; 1; 0; 0 1
endtable endprimitive
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LEVEL - SENSITIVE SEQUENTIAL EXAMPLE : LATCH
primitive latch ( q, clock, data); output q; reg q; input clock, data; initial q = 1 b1; table // clock data current next // state state 0 1 : ? : 1; 0 0 : ? : 0; 1 ? : ? : - ; endtable endprimitive The ? is used to represent dont care conditions in the inputs and current state
Note the use of a register for storage The output is initialized to 1 b1
Notice the additional field used to specify a next state
EDGE - SENSITIVE SEQUENTIAL EXAMPLE : D FLIP - FLOP primitive d_edge_ff ( q, clk, data ); output q; input clk, data; reg q table // clk dat state next : (01) 0 : ? : 0 ; (01) 1 : ? : 1 ; (0x) 1 : 1 : 1 ; (0x) 0 : 0 : 0 ; (x1) 0 : 0 : 0 ; (x1) 1 : 1 : 1 ; // ignore negative edge of clock (?0 ) ? : ? : - ; (1x) ? : ? : - ; // ignore data changes on steady clock ? (??) : ? : - ; endtable endprimitive
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SHORTHAND TO IMPROVE READABILITY
Sandeepani
Verilog has symbols that can be used in UDP table to improve readability
Symbol Interpretation Explanation
b
r
0 or 1
( 01)
Any known value

0 -> transition
f
p
( 10 )
1 -> 0 transition
( 01) or ( 0x ) or ( x1) Any positive edge,including unknowns
n
*
( 10 ) or ( 1x ) or ( x0 ) Any negative edge,including unknowns

( ?? ) Any transition
SUMMARY
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* UDPs allow you to create your own primitives to extend those built in to Verilog - Behavior is defined using a table - UDPs are instantiated like built - in primitive * They are a compact, efficient method of describing logic functions - Both combinational and sequential behavior can be described - UDPs are self - contained - Many built - in primitives can be replaced by a single UDP * There are some restrictions on using UDPs, including :- There must be a separate UDP for every output - The Z value is not supported hence UDP ports can not be bi - directional - UDPs are not synthesisable
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Verification Overview
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Objectives
After completing this module ,you will be able to..
Understand verification flow

Testbench structure
Different ways of generating vectors
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Outline
Introduction Vector generation
Simulation tips
summary
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Verification Flow
System Specifications
TB
RTL
Test Pass
Yes
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Introduction
Purpose of writing testbench: Instantiate the hardware model under test
Generate stimulus waveforms in the form of functional test vectors during simulation
Generate expected waveforms in the form of reference vector and compare with the output from RTL model Pass or fail indication
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Introduction
Testbench Structure
MODEL UNDER TEST

Stimulus Vectors Output Vectors
WAVE FORM
Reference Vectors
Test vectors File
GENERATION
COMPARE RESULTS
Results Files
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Outline
Simulation tips
summary
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Vector generation
Generate vectors on-the-fly Read vectors from files Writing vectors to a test file
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Vector generation
Different ways of generating system waveforms a) Use continuous loops for repetitive signals b) Use assignments for signals with few transitions c) Use relative or absolute time generated signals d) Use loop constructs for repetitive signal patterns
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Vector generation
Reading test vectors from file
Writing vectors to a text file
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Outline
Simulation tips
summary
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Simulation tips
Simulate Corner Cases only Use code coverage tools Use the triple equals Use the $display and $stop statements
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Summary
Verification flow Testbenches Simulation tips
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Verilog Testbenches
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Aims and Topics

* Aims Learn coding styles and methods that are commonly used to create a test bench * Topics - Simulation behavior - Testbench organization - Stimulus - Clock generation
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Design Organization
include files simulator design files
data clk read write
vendor libraries
compilation
file input: stimulus expects patterns
simulation
file output: stimulus results patterns
Simulation of a Verilog Model

initial avec = --------procedure
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compilation
procedure
initialization
procedure
procedure
x
procedure procedure
o x
procedure
l
procedure
simulation
Testbench
Testbench Organization
Design to verify
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stimulus
* Simple testbench - Just send data to desgin - No interaction - Few Processes * Sophisticated testbench - Models environment around designs - Talks to design - Evolves towards system model - self - checking
Testbench
stimulus verify Design to verify
results
In Line Stimulus
module inline_tb; reg (7:0) data_bus, addr; reg reset; // instance of DUT initial begin reset = 1bo; data_bus = 8hoo; # 5 reset = 1b1; #15 reset = 1bo; #10 data_bus = 8h45; #15 addr = 8hf0; #40 data_bus = 8h0f; end endmodule
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* Variables can be listed only when their values change * Complex timing relationships are easy to define * A test bench can become very large for complex tests
Stimulus From Loops

module loop_tb; reg clk; reg [7:0] stimulus; integer i; //instance of DUT //clock generation initial begin for(i = 0; i<256; i = i+1) @(negedge clk) stimulus = i; end endmodule
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* The same set of stimulus variables are modified in every iteration * Easy to enter * Compact Description * Timing relationships regular in nature * Best for stimulus:- Regular values - Set time period
**Important Do not forget to insert timin control in the loop
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Simple Delays
initial clk=0; always clk = ~clk; Will above code generate clk?
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Simple Delays
always #10 clk = ~clk;
#< value> provides simple time delay This is useful in providing timing for - Stimulus in testbenches - propagation delays in gate level simulation models
Summary
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* There are several Verilog constructs which are very useful in testbench construction e.g. * Several methods of applying stimulus have been examined:- In-line stimulus from an initial block - Stimulus from loop - Creating clocks
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System Control
Objective:Describe some of the compiler directives , system tasks and system functions available in Verilog
Topics:
Text output Simulation control
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$display
displays specified variables on execution -Example: reg[7:0]in_bus; #10; $display(At time %d in_bus is %h,$time,in_bus) Output:
At time 10 in_bus is 1f
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$monitor
-displays all values in the list each time any of them changes -$monitor($time, " A = %b B = %b CIN = %b SUM = %B CARRY = %b", A,B,CIN,SUM,CARRY);
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$monitor
module TB_FULL_ADD;
reg A, B, CIN; wire SUM, CARRY; FULL_ADD U1(A, B, CIN, SUM, CARRY); initial begin $monitor($time, " A = %b B = %b CIN = %b SUM = %B CARRY = %b", A,B,CIN,SUM,CARRY); A = 0; B = 0; CIN = 0; #5 A =1;B = 0; CIN = 0; #5 A =0;B = 1; CIN = 0; #5 A =1;B = 1; CIN = 0; #5 A =0;B = 0; CIN = 1; #5 A =1;B = 0; CIN = 1; #5 A =0;B = 1; CIN = 1; #5 A =1;B = 1; CIN = 1; #5 $finish; end
endmodule
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$monitor
Monitor list for full adder test bench
0 a=0 b=0 CIN=0 SUM =0 CARRY=0 5 a=1 b=0 CIN=0 SUM =1 CARRY=0 10 a=0 b=1 CIN=0 SUM =1 CARRY=0 15 a=1 b=1 CIN=0 SUM =0 CARRY=1 20 a=0 b=0 CIN=1 SUM =1 CARRY=0 25 a=1 b=0 CIN=1 SUM =0 CARRY=1 30 a=0 b=1 CIN=1 SUM =0 CARRY=1 35 a=1 b=1 CIN=1 SUM =1 CARRY=1 $finish at simulation 40
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$monitor
$monitoron //switches monitor on $monitoroff //switches monitor off
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Simulation control
simulation flow
#200 $stop;
simulation suspends at time 200
#1000 $finish;
simulation terminates at time 1000
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Compiler directives
ìnclude <file name> Example:file global.txt
//clock and simulator constants Parameter initial_clk=1; Parameter period=20; Parameter max_cycle=5; Parameter end_time=period*max_ cycle
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Compiler directives:Example
Usage: Module clock_gen; ìnclude global.txt always begin $monitor( $time,\t clk=%d,clk); clk=initial_clk; while ($time<end_time) begin #(period/2) clk=~clk ; end $display($time,simulation ends) $finish; End endmodule
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More compiler directives

`define add16 reg[15:0] add16 can be interpreted as reg[15:0] interpreted as reg[15:0] input address 10ns is the time unit for the block and these are rounded off to a 1ns precision
àdd16 input adress;
`timescale 10ns/1ns
#10 clk =~clk
10 time units =100ns
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File outputs
32 channels available
32h000_0001 32h000_0800 channel descriptor for standard output(bit 0 set) channel descriptor for 11th channel (bit 11 set)
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$fopen, $fclose
$fopen integer chan_num1,chan_num2;
declaration of channel descriptors

Chan_num1=$fopen(file1.out); Chan_num2=$fopen(file2.out); Chan_num1=32h0000_0002(bit 1 set) Chan_num2=32h0000_0004(bit 2 is set)
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Writing into file

integer chan_num1; initial begin chan_num1=$fopen(file1.out); $fmonitor(chan_num1,$time,add_in=%d,add_out=%b, add_in,add_out); monitor results go to file1.out
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Writing into multiple file

integer chan_num1,chan_num2,mdesc; initial begin chan_num1=$fopen(file1.out); chan_num2=$fopen(file2.out); mdesc= chan_num1 | chan_num2; $fmonitor(mdesc,$time,add_in=%d,add_out=%b, add_in,add_out);
monitor results are written to file1.out and file2.out Files can be closed using $fclose
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$readmemb and $readmemh module mem8x8; reg [0:7] mem8x8 [0:7]; integer chan_num1, i; initial begin $readmemb("init8x8.dat", mem8x8); chan_num1 = $fopen ("mem8x8.out"); for (i = 0; i < 8; i = i + 1) $fdisplay(chan_num1, "memory [%0d] = %b", i, mem8x8[i]); $fclose(chan_num1); end endmodule
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init8X8.dat @2 11111111 10101010 00000000 @6 Xxxxzzzz 1x1x1x1x
start address specified with @ consecutive data applies to consecutive address
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mem8x8.out memory[0]=xxxxxxxx memory[1]=xxxxxxxx memory[2]=11111111 memory[3]=10101010 memory[4]=00000000 memory[5]=xxxxxxxx memory[6]=xxxxzzzz memory[7]=1x1x1x1x
address 0,1 and 5 were not initialized (==x)
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Tasks and Functions
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Tasks and Functions

Subprograms -Encapsulate portions of repeated code -Sequential statements -Execute in sequence like software
Task - Zero or more input/outputs - Is a procedural statements

Function - Multiple inputs, single return value - Can only be used as part of assignment
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Task Declaration and call

task zero_count; (Task name) 1.Task call is a procedural statement //input arguments //output arguments //Local variable input [7:0]in_bus; output [3:0] count; integer i;
begin count=0; #5; for (i=0;i<8;i=i+1) if(!in_bus[i]) count=count+1; end endtask
//assign outputs
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module zerotask(); reg[7:0] a_bus; reg clk; reg [3:0] a_count; reg a_zero; //task declaration initial begin clk=0; a_bus=8'b00011111; end always # 20 clk =~clk ;
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always @(posedge clk) begin zero_count (a_bus, a_count); if ( a_count == 4'b0010) a_zero=1'b1; else a_zero=1'b0; end endmodule
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Multiple Task calls

Tasks can be called from more than one location Tasks are not duplicated like sub-routines - only one copy of tasks exists Avoid simultaneous concurrent calls -Can cause conflict with task variables abd input/output arguments ,Example
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Multiple Task calls

task neg_edge; input [31:0] no_of_edges; begin repeat(no_of_edges) @(negedge clk); end endtask
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Multiple Task calls

module multiple_task_calls; reg clk; reg p;
initial begin clk=1; p=0; end always #50 clk=~clk; initial begin neg_edge(4); p=1; end
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Multiple Task calls

always @(posedge clk) begin neg_edge(10); p=0; end endmodule
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Task Calls from Different Modules

module mytasks; task neg_edge; input [31:0] no_of_edges; begin repeat(no_of_edges) @(negedge clk); end endtask Task cpu_driver; . . endmodule
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Task Calls from Different Modules

//test bench
module test_busif; reg clk; //clock generation . //instantiation of task module mytask m1 ( ) ; //creating stimulus.. Initial begin m1.neg_clocks(6); m1.cpu_driver(8h00); end endmodule
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Disabling tasks and named blocks

Tasks or named blocks can be disabled - Here in Ex.if CPU interrupt is detected the cpu_driver task is forced to exit -The CPU interrupt can then be sreviced - Does not prevent subsequent task calls Named blocks are disabled in the same way Example follows..
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Disabling tasks and named blocks

module test_busif; always #20 clk=~clk; .. initial begin: stimulus neg_clock(5); cpu_driver(8h00); cpu_driver(8hff); always @(posedge interrupt) begin disable cpu_driver; service_interupt; end endmodule
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Task without timing controls

A Task normally contains timing But without timing controls it executes in zero time A task without timing control can be always be expressed as a function Example follows..
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Task without timing controls

task zero_count input [7:0]in_bus; output [3:0] count; integer i; begin count=0; for (i=0;i<8;i=i+1) if(!in_bus[i]) count=count+1; end endtask
function integer zero_count; input [7:0]in_bus; integer i; begin zero_count=0; for (i=0;i<8;i=i+1) if(!in_bus[i]) zero_count=zero_count+1; end endfunction
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Function Declaration
function integer zero_count; input [7:0]in_bus; integer i; begin zero_count=0; for (i=0;i<8;i=i+1) if(!in_bus[i]) zero_count=zero_count+1; end endfunction
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function Call
module zfunct (a_bus,b_bus,clk,azero,b_count); input[7:0] a_bus,b_bus; input clk; output azero, b_count; reg azero; Wire[3:0] b_count; //function declaration assign b_count=zero_count(b_bus); always @(posedge clk) if(zero_count(a_bus)==320) azero=1b1; else azero=1b0 endmodule
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Functions
Function can enable other functions but not another task Functions always execute in zero simulation time Functions cannot include delays,timing or timing control statements
Functions must have at least one input argument

Functions return a single value.they cannot have output or inout arguments
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Examples
1.Write a function to add two 4 bit numbers 2.Write task for the waveform specification given below: 3.Write task to count number of clock cycles 4.Write task to load time in alarm clock design
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Verilog PLI
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Outline
Introduction PLI Interface TF/ACC Routines Creating PLI Applications
Summary
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Introduction
Verilog Programming Language Interface is one of the most powerful features of Verilog
PLI provides both H/S designers to interface their programs to commercial Verilog simulators
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Introduction
Generations of PLI IEEE 1364 Verilog TF / ACC routines. VPI routines PLI 1.0 PLI 2.0 1990 1993
Introduction
Capabilities of Verilog PLI
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Access to programming language libraries Simulation analysis
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Outline Introduction PLI Interface TF/ACC Routines Creating PLI Applications Summary
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PLI Interface
User Design Representation And Stimulus
Invokes UserDefined System Task
User Defined System Task #1 User-Defined System Task #2 User-Defined System Task #3 Invokes UserPLI Library defined C Routines routine User-Defined C routine # 1 User-Defined C routine # 2 User-Defined C routine #3
Pass data Verilog Compilation
Internal design Representation (Data Structures)
Access Internal structures
Simulation
Simulation Output
PLI Library Routines to do Miscellaneous Operations
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Objects in Verilog
Module instances, ports, pin-to-pin paths, intermodule paths Top-level modules Primitive instances, terminals
Nets, registers, parameters, specparams Integer,time and real variables
Timing checks & Named events
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Conceptual Internal Representation a Module
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Example
Example: 2-to-1 Multiplexer
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Internal Data Representation of 2-to-1 Multiplexer
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Outline Introduction PLI Interface TF/ACC Routines Creating PLI Applications Summary
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TF/ACC Routines
Role of Access and Utility Routine
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Outline
Introduction PLI Interface TF/ACC Routines Creating PLI Applications
Summary
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General steps to create PLI applications

1. Define system task / function 2. Write C language routine 3. Register system task/function name and associate C language routine with Verilog simulator 4. Compile C source file which contains PLI application & link object files into Verilog simulator.
Some useful tf routines

int tf_nump()-Returns number of arguments in system
task
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int tf_typep(n)- Returns constants that reps.data type
viod tf_error()-Prints error massage & causes simulation

to abort
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Some useful ACC Routines

handle acc_handle_tfarg(n)-Returns pointer to system t/f handle int acc_fetch_type(object)- Returns constant that identifies type of argument char *acc_fetch_fullname(object)-Returns fulltype property of object
char *acc_fetch_value(object,format_str,value)-Return value of verilog object
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PLI application example

$show_value Uses PLI to access specific activity within a Verilog simulator, by listing the name and current value of net This system task $show_value illustrates using PLI to allow a C routine to read current logic values within a Verilog simulation
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Step I module test; reg a, b, ci; wire sum, co; ... initial begin ... $show_value (sum); end endmodule
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Step II Two user-defined C routines will be associated with $show_value: A C routine to verify that $show_value has the correct type of arguments A C routine to print the name and logic value of the signal
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Writing a checktf routine for $show_value

# include veriuser.h library */ # include acc_user.h library */ Int ShowVal_checktf( ) { int arg_type; handle arg_handle; /* IEEE 1364 PLI TF routine /* IEEE 1364 PLI ACC routine
if (tf_nump( ) != 1) tf_error ($show_value must have 1 argument.); else if (tf_typep(1) == TF_NULLPARAM) tf_error ($show_value arg cannot be null.); contd
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Writing a checktf routine for $show_value

else { arg_handle = acc_handle_tfarg(1); arg_type = acc_fetch_type(arg_handle); if (! (arg_type == accNet || arg_type == accReg) ) tf_error ($show_value arg must be a net or reg.); } return (0); }
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Writing a calltf routine for $show_value

# include veriuser.h # include acc_user.h int ShowValCalltf( ) { handle arg_handle; arg_handle = acc_handle_tfarg(1); io_printf (Signal %s has the value %s \n, acc_fetch_fullname(arg_handle), acc_fetch_value(arg_handle, %b, null) );
return (0); }
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Step III : Registering the system task/function Interface mechanism The type of application which is a system task or system function The system task or system function name The name of the calltf routine and other C routines associated with the system task/function. Other information about the system task/function required by simulator
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The default standard veriusertfs array

s_tfcell veriusertfs [ ] = { { type, user_data, checktf_app, sizetf_app, calltf_app, mistf_app, tf_name, 1, 0, 0 }, { type, user_data, checktf_app, sizetf_app, calltf_app, misctf_app, tf_name, 1, 0, 0 }, ...
{ 0 }, /* first field in final array cell is 0 */

};
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S-tfcell structure definition is:

typedef struct t_tfcell { short type; /* one of the constants: usertask, user function, user real /* data passed to use routine */ /* pointer to the checktf routine */ /* pointer to the sizetf routine */ /* pointer to the calltf routine */ /* pointer to the misctf routine */ /* name of the system task/function */ /* usually set to 1 */ /* usually ignored */ /* usually ignored */
function */ short data; int (*checktf) ( ); int (*sizetf) ( ); int (*calltf) ( ); int (*misctf) ( ); char *tfname; int forwref; char *tfveritool; char *tferrmessage; } s_tfcell, *p_tfcell;
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Example veriusertfs array for registering TF/ACC applications

/* prototypes for the PLI application routines */ extern int Showval_checktf( ), pow_sizetf( ); extern int pow_checktf( ), pow_sizetf( ), pow_calltf( ), pow_misctf( ); /* the veriusertfs array */ s_tfcell veriusertfs [ ] = { { usertask, 0, ShowVal_checktf
/* type of PLI routine */ /* user_data value */ /* checktf routine */
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Interfacing PLI Application

0,
ShowVal_calltf, 0, $show_value, 1 }, {
/* sizetf routine */
/* calltf routine */ /* misctf routine */ /* system task/function name */ /* forward reference = true */ /* type of PLI routine */ /* user_data value */ /* checktf routine */ /* sizetf routine */ /* calltf routine */
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/* misctf routine */ /*system task/function name 1 }, /* forward reference = true
{0}
};
/*** final entry must be 0
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Interfacing PLI Application

Compiling and linking PLI applications
cl c I <simulator path>\include <name of c file>
link -dll export:veriusertfs <name of .obj file> <simulator path>\ Win32\mtipli.lib
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A test case for $show_value

`timescale 1ns / 1ns module test; reg a, b, ci, clk; wire sum, co; addbit i1 (a, b, ci, sum, co); initial begin a = 0; b = 0; ci = 0; #10 a = 1; contd
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$show_value(sum); $show_value(co); $show_value(i1.n3); #10 $stop; $finish; end Endmodule
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Output from running the $show_value test case

Compiling source file show_value_test.v Highest level modules: Test
Signal test.sum has the value 1 Signal test.co has the value 0 Signal test.11.n3 has the value 0 L32 show_value_test.v: $stop at simulation time 20
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Thank You
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Verilog Sample Design
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Aims and Topics

Aims
To review basic Verilog concepts and code structures To explore a real life example
Topics
FIFO (First-in First-out) design specification Implementation Module declarations Functional code Testbench design and implementation
FIFO Specification
Data is read and written on rising edge of clock Asynchronously resetable
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FIFO design is a register block at the end of a data path FIFO is synchronous When write enable is high, data is written into FIFO and stored When read enable is high, data is read from FIFO
In the same order that it was written
Both enable lines are not allowed to be active in the same clock cycle
If this occurs, both read and write operations are suppressed
When the FIFO is full, set f_full high and ignore write operations When the FIFO is empty, set f_empty high and ignore read operations FIFO should be parameterisable for data width and FIFO
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FIFO Implementation
Use register array for FIFO contents Array accessed by write and read pointers Status of FIFO derived from pointer addresses FIFO full FIFO empty 0 1 2 3 . . .
FIFO length . . . . n FIFO width
rd_ptr Read pointer follows write and accesses data in same order as written
wr_ptr FIFO write: assign data to current write pointer & increment wr_ptr
rd_ptr
wr_ptr
three
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FIFO Model Structure

module fifo (data_in, data_out, clock, reset, wr_en, rd_en, f_full, f_empty); // parameter declarations // input declarations // output declarations // register declarations // internal variable declarations // functional code // clocked procedures // combinational procedures endmodule
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Design Constants
Parameters used to 0 1 2 3 . . . . . . LENGTH-1 define data and 0 address width 1 Must be declared 2 before input/output . . ports Values can be changed WIDTH-1 in module instantiation rd_ptr[ADDRESS_WIDTH-1 : 0]
module fifo (data_in, // parameter declarations parameter WIDTH = 8; parameter ADDRESS_WIDTH = 5; parameter LENGTH = (1 << ADDRESS_WIDTH ); // 16 location fifo of 16 bit data fifo #(16,4) fifo16x16. (
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FIFO I/O
module fifo (data_in, data_out, clock, reset, wr_en, rd_en, f_full, f_empty // parameter declarations parameter WIDTH = 8; parameter ADDRESS_WIDTH 5; parameter LENGTH = (1 << ADDRESS_WIDTH ); // input declarations input [WIDTH-1:0] data_in; input clock, reset; input wr_n, rd_en; // output declarations output f_full; output f_empty; output [WIDTH-1:0] data_out; // register declarations // internal variable declarations // functional code endmodule data_in WIDTH wr_en rd_en fifo data_out WIDTH f_full f_empty
reset clock
Register and Internal Variable Declarations

module fifo. // parameter declarations parameter WIDTH = 8; parameter ADDRESS_WIDTH = 5; parameter LENGTH = (1 << ADDRESS_WIDTH); // input and output declarations // FIFO array declaration reg [WIDTH 1:0] fiforeg [LENGTH 1:0]; // pointer declarations reg [ADDRESS_WIDTH 1:0] wr_ptr; reg [ADDRESS_WIDTH 1:0] rd_ptr; // integer needed with for loops integer I;
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wr_ptr rd_ptr . . . . . . . . . .
fiforeg 0 1 2 3 . . . . . . . [WIDTH 1 :0]
LENGTH-1.
// functional code. endmodule
FIFO Functional Code
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always @ (posedge clock or posedge reset) if (reset) Clocked procedure begin rd_ptr < = {ADDRESS_WIDTH {1b0}}; describes functionally wr_ptr < = {ADDRESS_WIDTH {1b0}}; for:Reset for (I = 0; I < LENGTH; I = I + 1) Pointer updates fiforeg[1] < = {WIDTH {1;B0}}; Writing to FIFO array end else Clocked procedure begin Uses non-blocking if (rd_en && (!wr_en) && (!f_empty)) assignment rd_ptr < = rd_ptr + 1; if ((rd_en) && wr_en && (if_full)) begin fiforeg[wr_ptr] < = data_in; wr_ptr < = wr_ptr + 1 ; end end read operation: increment read pointer write operation: write data at current pointer and update pointer
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FIFO Outputs If write pointer cather read pointer FIFO full
Module fifo
/ / declarations / / clocked procedure / / full and empty pointers assign and empty pointers
assign f_full = ( ( rd_ptr wr_ptr) = = 5b000001); assign data_out= fiforeg[rd_ptr]; End module Outputs are combinational If read pointer catchers write pointer, FIFO empty
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Testbench
Instantiates and connects Design Under Test (DUT) Applys stimuli to input data and control ports Monitors output ports to check for correct behavior for given stimuli
Monitors output ports to check for correct behaviour for given stimuli
- may be done via waveform display in simulator
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DUT Instantiation
module fifo_tb;
fifo is the reference name of the
/ / Data type declaration

/ / FIFO instantiation fifo # (WIDTH, ADDRESS_WIDTH) dut ( .data_in (data_in) .data_out (data_out), .clock .reset .wr_en .f_full .f_empty (clock) (reset) (rd_en) (f_full), (f_empty)
module under test
dut is the name of this instance

FIFO parameters are reassigned in the instantiation Named port connection used to link FIFO ports to local variables -Syntax .port (variable) Local variables and parameters must be defined
Question Why are there no ports for the test fixture ?
/ / Apply stimuls endmodule
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Testbench Declarations
module fifo_tb Parameter WIDTH =8; Parameter ADDRESS_WIDTH = 5: Parameter PERIOD = 10;
/ / input declarations
reg [WIDTH-1:0] data;

reg clock, wr_en, rd_en, reset;
/ / output declarations
wire f_full;
Wire f_empty; wire endmodule
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Describing Stimulus
initial begain data = { WIDTH {1b0}}; {wr_en, rd_en} = 2b00; $monitor (data_out,, f_full,,,f_empty reset=1b0; #2; reset = 1b1; read from an empty fifo to check the empty flag Any tune these signals change, display their stable values in the standard output Initial clock = 1b0; Always # PERIOD clock = - clock,
#5;
reset =1b0; @(negedge clock) ; rd_en = 1b0; wr_en = 1b1; for (i = 0, i <35; i = i + 1) begin @(negedge clock); data = 255 i; halt simulation read two words to check advancing read pointer Fill FIFO and then write to check full flag
end
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Describing Stimulus
rd_en = 1b1; wr_en = 1b0; repeat (2) @(negedge clock); $stop;
end
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Review
1.How can you change the value of parameter ? 2. What are basic fundamental blocks of test fixture ? 3.Using a parameter, write code that creates a clock stimulus.

Sandeepani Verilog

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Sandeepani Verilog

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Sandeepani

Verilog HDL Coding for Simulation & Synthesis

Verilog Supports: Structure

Timing Abstraction levels

Physical -silicon -Switch

Layout / place & Route

Abstraction Level Example:Divide by 2

always @ (posedge clk) op <= data >> 1; Gate Level Netlist

Benefits of Using an HDL

Verilog Based Simulation

Verilog Language Introduction

Aims and Topics

Connecting Hierarchy-Named Port Connection instantiation

module a sum b carry

Procedural Blocks (Procedures)

The Verilog Connectivity Model

Procedures contained in a module

Compile into WORK

Design Compilation compiled from a list Design

behavioral RTL/structural behavioral

Comments and Spacing

Identifier Naming Rules

unit_32 structural bus_16_bite a$b unit@32 unit - 32 16_bit_bus

Verilog Logic System and Data Types

Aims and Topics

4-Value Logic System in Verilog

Hiz, High Impedance, Tri-State, Undriven, Unconnected, Disabled Driver (Unknown)

Wire and assign

Logic Conflict Resolution with Nets

Register Assignment ( a, b, c, sel, mux ) ; module mux

Choosing the Correct Data Type

module dut (y, a, b) ; output y; input a, b; assign y = a&b; endmodule

Overriding the Values of Parameters

Constant values can be changed for each instantiation of module

module mux (a, b, sel, out); parameter WIDTH = 2; .

module gen_dec_call (ena,enab,adda,addb,decadda,decaddb);

Two Dimensional Arrays

A array element is addressed by an index to the 2-d array

Synthesis: Two-dimensional arrays generally not synthesisable

Aims and Topics

Arithmetic Operators ( ) ; module arithops

Binary arithmetic is unsigned Integer arithmetic is signed

Synthesis % not synthesisable / only synthesisable if dividend is a power of 2

initial begin rega = 4 b1001 ; regb = 4 b1010 ; regc = 4 b11x0 ;

Logical Operators module logical ( );

Unary Reduction Operators

module relationals; reg [3:0] rega, regb, regc; reg val ;

Conditional Operator (in, enable, out); module tribuf

Aims and Topics

initial versus always Procedures

Error carry is a net type-should be declared reg carry;

always @ (a or b or sel) begin if (sel = = 1) event list y = a; else y = b; end

always @ (posedge clk) // procedural statements

Procedural Blocks within Verilog

assign nsela = nsel & a;

// continuous statements endmodule

d Synthesis if synthesis to mux structures c b a

0101 d 0000 <= = 0 0 y 1 1 mux mux

case Statement Example

a[0] a[1] a[2] a[3]

repeat and while Loops

Loop Statement Syntax

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