2.

5 Program Execution by Typical 32-bit Microporcessors

Design of 32-bit microprocessors such as the Pentium have many powerful features the mainframe computers in the same chip. 32-bit microprocessors include cache memory, memory management, pipelining, floatingpoint arithmetic, and branch prediction.

 Cache memory is a high-speed read/write memory implemented as on-chip hardware in typical 32-bit microprocessors to increase processing rates. Memory management allows programmers to write programs much larger than those that could fit in the main memory space available to the microprocessors.

Pipelining
pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput . Pipelining increases the number of instructions that can be processed at once, thus reducing the delay between completed instructions. 32-bit microprocessors implement the pipelining to prefetch the next instruction while the control unit is busy decoding the current instruction. Pipelining was first implemented in Motorolas 68020. Followed by Intels 80486

Pipelining Concept
In 32-bit microprocessors, the pipeline concept is typically used for carrying out two tasks:
arithmetic operations instruction execution.

Arithmetic Pipelines
The pipeline concept is widely used in designing floating- point arithmetic units. In summary, addition or subtraction of two floating-point numbers calls for four activities: 1. Exponent comparison 2. Exponent alignment 3. Significand addition or subtraction 4. Postnormalization

It is important to realize that each segment in this pipeline is composed primarily of combinational components such as multiplexers. The shifter used in this system is a barrel shifter. Note that a barrel shifter is a fast shift register that shifts data in one direction

Instruction Pipeline
32-Bit microprocessors such as the Motorola 68020 contain a three-stage instruction pipeline. Note that an instruction cycle typically involves the following activities: 1. Instruction fetch 2. Instruction decode 3. Operand fetch (Data Read) 4. Operation execution 5. Result routing.

Branch Prediction Feature

Typical 32-bit microprocessors implement a multiple-branch prediction feature. This allows these microprocessors to anticipate jumps of the instruction flow ahead of time. 32-bit microprocessors maintain an instruction pool for a sequence of instructions and perform a useful task rather than executing the present instruction and then going on to the next. The branch prediction feature of the Pentium speeds up execution of program loops

 Pentium includes on-chip hardware called the Branch Unit (BU). The BU contains the branch execution unit (BEU) and the branch prediction unit (BPU). The BU evaluates the instructions branch condition using the BEU and determines whether the branch should or should not be taken. Once the BU determines the branch condition, it calculates the starting address (Branch target) of the next block of code to be executed. The Pentium then starts fetching code at the new address.

Scalar & Superscalar Microprocessors

Scalar processors such as the 80486 can execute one instruction per cycle. The 80486 contains only one pipeline. Superscalar microprocessors, on the other hand, can execute more than one instruction per cycle. These microprocessors contain more than one pipeline.

RISC vs CISC
RISC (Reduced Instruction Set Computing) is a CPU design strategy based on the insight that simplified instructions can provide higher performance if this simplicity enables much faster execution of each instruction. CISC (Complex instruction set computing) is a computer where single instructions can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) and/or are capable of multi-step operations or addressing modeswithin single instructions.

 The following list summarizes the typical features of a RISC microprocessor: 1. The RISC microprocessor is designed using hardwired control with little or no microcode. 2. ARISC microprocessor executes most instructions in a single cycle. 3. The instruction set of a RISC microprocessor typically includes only register, load, and store instructions.

4. The instructions have a simple fixed format with few addressing modes. 5. A RISC microprocessor has several general-purpose registers. 6. A RISC microprocessor processes several instructions simultaneously and thus includes pipelining. 7. Software can take advantage of more concurrency. For example, jumps occur after execution of the instruction that follows. This allows fetching of the next instruction during execution of the current instruction.

 RISC microprocessors are well suited for applications such as image processing, robotics, graphics, and instrumentation. Typical 32- and 64-bit RISC microprocessors include PowerPC microprocessors.

 CISC microprocessors, on the other hand, contain a large number of instructions and many addressing modes, while RISC microprocessors include a simple instruction set with a few addressing modes.

 CISC is more difficult to pipeline; RISC provides more efficient pipelining. An advantage of CISC over RISC is that complex programs require fewer instructions in CISC with fewer fetch cycles, while RISC requires a large number of instructions to accomplish the same task with several fetch cycles. However, RISC can significantly improve its performance with a faster clock, more efficient pipelining, and compiler optimization.

 PowerPC and Intel 8OXXX utilize RISC and CISC architectures, respectively. Members of the Pentium family and Motorola 68060 use a combination of RISC and CISC architectures for providing high performance. The Pentium Pro and other succeeding members of the Pentium family use to implement efficient pipelining for simple instructions. CISC for complex instructions is utilized by the Pentium to provide upward compatibility with the Intel 8086180x86 family.