Utilizando Design Compiler e FPGA Compiler II

Fluxo de Sntese partindo de SystemC

Cdigo SystemC RTL

Compile SystemC DC_SHELL

Verilog File

FPGA Compiler II

Arquivo EDIF

Ferramenta ISE

FPGA

Caractersticas de SystemC

Caractersticas de uma Linguagem para CoDesign

Mdulos Processos Portas Sinais Amplo conjunto de tipos para portas e sinais Amplo conjunto de tipos de dados

Clocks Simulao baseada em ciclo Mltiplos Nveis de Abstrao Protocolos de Comunicao Suporte para Depurao Trace de Formas de Onda

Modelo de Programao de

SystemC
Mod 1

Mod 2

Mod 3

Um conjunto de mdulos interagindo atravs de sinais. A funcionalidade de um Mdulo descrita por

processos.

Um Exemplo Simples: Definindo um Module

Led
SC_MODULE(led) { sc_in<bool> Clk,Reset;

Clk
Reset
PhighFreq

Pled Led
}

sc_in<bool> PhighFreq; sc_out<out> Pled; ...

Um Exemplo Simples: Definindo um Mdulo

#include "systemc.h" SC_MODULE (led) { sc_in< bool > Clk; sc_in< bool > Reset; sc_in< bool > PhighFreq; sc_out< bool > Pled; sc_signal< bool > Sled; sc_signal< sc_uint< 25 > > Scount; void led::go() {

#include "systemc.h #include "led.h" if (!Reset.read()) { Scount.write(0); Pled.write(false);

led.h

led.cpp

} else {
if (PhighFreq.read()) { Scount.write(Scount.read() + 10); } else { Scount.write(Scount.read() + 1); } if (Scount.read() >= 27000000) { Scount.write(0); Sled.write(!Sled.read()); Pled.write(!Sled.read()); } else { Pled.write(Sled.read()); } } }

void go(); SC_CTOR(led) { SC_METHOD(go); sensitive_pos << Clk; sensitive_neg << Reset; } };

Design Compiler traduo SystemC -> Verilog

Copiando os exemplos:

http://www/~msml/led/led.cpp e led.h

Inciando o Design Compiler (dc_shell)

Logar no servidor synopsys Ir para o diretrio onde encontram-se os arquivos copiados (o exemplo) Digitar no prompt o comando:dc_shell

Design Compiler traduo SystemC -> Verilog

Convertendo de SystemC RTL para Verilog

compile_systemc -rtl -format [verilog ou vhdl] <arquivo.cpp>

Cdigo Verilog Gerado pelo dc_shell

always @(posedge Clk or negedge Reset) begin : go

module led(Clk, Reset, PhighFreq, Pled); input Clk; wire Clk; input Reset; wire Reset; input PhighFreq; wire PhighFreq;

if (!Reset)

begin
Scount <= 25'b0000000000000000000000000;

led.v

Pled <= 0; end else begin if (PhighFreq) Scount <= 25'b0000000000000000000001010 + Scount; else Scount <= 25'b0000000000000000000000001 + Scount; if (Scount >= 25'b1100110111111110011000000) begin Scount <= 25'b0000000000000000000000000; Sled <= !Sled; Pled <= !Sled; end else Pled <= Sled;

output Pled;
reg Pled; reg [24:0] Scount; reg Sled;
end end endmodule

...

Utilizando Design Compiler

Para verificar se os comandos esto sendo direcionados ao arquivo certo: current_design

retorna o nome do design corrente

Reports sobre timing e area. Os respectivos comandos so:

report_area report_timing

Gerando edif a partir do Verilog

Inciando o FPGA Compiler II

Na sua mquina digitar o comando:

xhost pesqueira

Logar no servidor pesqueira e executar os comandos

source /usr/synopsys/tcshrc.u-2003.03-SP1 setenv DISPLAY <nome_maq>:0.0 fc2

FPGA Compiler II

Passo 1: criando um projeto

FPGA Compiler II

Passo 2: selecionar os arquivos HDL Passo 3: selecionar a entidade top e clicar em next

FPGA Compiler II
4
Passo 4: selecionar o dispositivo alvo Passo 5: configurar otimizaes Passo 6: gerar o EDIF

FPGA Compiler II Visualizando o esquemtico

Passo 1: clicar no chip Passo 2: opo view schematic

FPGA Compiler II Visualizando o esquemtico

FPGA Compiler II Gerando Relatrio do Projeto

Passo 1: clicar no menu file Passo 2: opo project report Passo 3: escolher local para salvar o report (.txt)

FPGA Compiler II Gerando Relatrios

================== Chip led-Optimized ==================

Project Report

Chip Parameters: ---------------Optimize for: Speed Optimization effort: High Frequency: 50 MHz Is module: No Keep io pads: No

Number of flip-flops: 27
Number of latches: 0

...

Utilizando o ISE a partir do EDIF

Processo anlogo ao que foi apresentado...

Comparando a Sntese do FC2 com o ISE para Verilog

ISE - Map Report Led Entrada do Projeto: Edif (gerado pelo FC2 a partir do verilog) Design Summary -------------Logic Utilization: Number of Slice Flip Flops: 26 out of Number of 4 input LUTs: Total Number 4 input LUTs: Number used as logic: 41 out of 63 out of 41 21,504 21,504 21,504 1% 1% 1% ISE - Map Report Led Entrada do Projeto: Verilog Design Summary

-------------Logic Utilization: Number of Slice Flip Flops: 26 out of Number of 4 input LUTs: Total Number 4 input LUTs: Number used as logic: 58 out of 106 out of 58 21,504 21,504 21,504 1% 1% 1%

Number used as a route-thru: 22 Number of bonded IOBs: IOB Flip Flops: Number of GCLKs: 4 out of 1 1 out of 633 16 6% 624 1%

Number used as a route-thru: 48 Number of bonded IOBs: IOB Flip Flops: Number of GCLKs: 4 out of 1 1 out of 16 939 6% 624 1%

Total equivalent gate count for design: Additional JTAG gate count for IOBs: Peak Memory Usage: 98 MB 192

Total equivalent gate count for design: Additional JTAG gate count for IOBs: Peak Memory Usage: 99 MB 192

Comparando a Sntese do FC2 com o ISE para VHDL

ISE - Map Report Led Entrada do Projeto: Edif (gerado pelo FC2 a partir do vhdl) Design Summary -------------Logic Utilization: Number of Slice Flip Flops: 26 out of Number of 4 input LUTs: Total Number 4 input LUTs: Number used as logic: 39 out of 61 out of 39 21,504 21,504 21,504 1% 1% 1% ISE - Map Report Led Entrado do Projeto: VHDL Design Summary

-------------Logic Utilization: Number of Slice Flip Flops: 26 out of Number of 4 input LUTs: Total Number 4 input LUTs: Number used as logic: 46 out of 92 out of 46 21,504 21,504 21,504 1% 1% 1%

Number used as a route-thru: 22 Number of bonded IOBs: Number of GCLKs: 3 out of 1 out of 613 624 16 1% 6%

Number used as a route-thru: 46 Number of bonded IOBs: Number of GCLKs: 3 out of 1 out of 811 624 16 1% 6%

Total equivalent gate count for design: Additional JTAG gate count for IOBs: Peak Memory Usage: 98 MB 144

Total equivalent gate count for design: Additional JTAG gate count for IOBs: Peak Memory Usage: 98 MB 144

Utilizando Design Compiler e FPGA Compiler II