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SEQUENTIAL LOGIC

Memory Elements Latches: S-R Latch, D Latch Flip-flops: S-R flip-flop, D flip-flop, J-K flip-flops, T flip-flops Asynchronous Inputs Synchronous Sequential Circuit: Analysis and Design Memory Memory Unit Read/Write Operations Memory Arrays
CS2100 sequential logic

Sequential

circuit

Submitted to: Sumit Yadav

Submitted by: tushita das


CS2100 sequential circuit 2

Two classes of logic circuits


Combinational Sequential

Combinational Circuit
Each output depends entirely on the immediate (present) inputs.

Sequential Circuit

Each output depends on both present inputs and state.

inputs : :

Combinational Logic

::

outputs

inputs : :

Combinational Logic

::

outputs

INTRODUCTION (1/2)
CS2100

Memory

sequential circuit

Two types of sequential circuits:


Synchronous: outputs change only at specific time Asynchronous: outputs change at any time

Multivibrator: a class of sequential circuits


Bistable (2 stable states) Monostable or one-shot (1 stable state) Astable (no stable state)

Bistable logic devices


Latches and flip-flops. They differ in the methods used for changing their state.

INTRODUCTION (2/2)
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Memory element: a device which can remember value indefinitely, or change value on command from its inputs.
command
Memory element Q

stored value

Characteristic table:
Command (at time t) Set Reset Memorise / No Change Q(t) X X 0 1 Q(t+1)

Q(t) or Q: current state


1 0 0 1

Q(t+1) or Q+: next state

MEMORY ELEMENTS (1/3)


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Memory element with clock.


command Memory element

Q
stored value

clock

Clock is usually a square wave.


Positive pulses

MEMORY ELEMENTS (2/3)


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Positive edges

Negative edges

Two types of triggering/activation


Pulse-triggered Edge-triggered

Pulse-triggered
Latches ON = 1, OFF = 0

Positive pulses

Edge-triggered

Flip-flops Positive edge-triggered (ON = from 0 to 1; OFF = other time) Negative edge-triggered (ON = from 1 to 0; OFF = other time)

Positive edges

Negative edges

MEMORY ELEMENTS (3/3)


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Two inputs: S and R. Two complementary outputs: Q and Q'.


When Q = HIGH, we say latch is in SET state. When Q = LOW, we say latch is in RESET state.

For active-high input S-R latch (also known as NOR gate latch)

R = HIGH and S = LOW Q becomes LOW (RESET state) S = HIGH and R = LOW Q becomes HIGH (SET state) Both R and S are LOW No change in output Q Both R and S are HIGH Outputs Q and Q' are both LOW (invalid!)

S-R LATCH (1/3)

Drawback: invalid condition exists and must be avoided.


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Active-high input S-R latch:


10100 R

Q 11000
Q' 0 0 1 1 0

10001 S

S 1 0 0 0 1

R 0 0 1 0 1

Q Q' 1 0 initial 1 0 (afer S=1, R=0) 0 1 0 1 (after S=0, R=1) 0 0 invalid!

Block diagram:
S R Q Q'

S-R LATCH (2/3)


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S-R LATCH (3/3)

Characteristic table for active-high input S-R latch:


S 0 1 0 1
S R 0 0 1 1 0 1 0 1

S R

Q Q'

R 0 0 1 1

Q NC 1 0 0
Q(t+1)

Q' NC 0 1 0 No change. Latch remained in present state. Latch SET. Latch RESET. Invalid condition.

Q(t) No change 0 Reset 1 Set indeterminate

Q(t+1) = ?

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sequential circuit

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Flip-flops are synchronous bistable devices.


Output changes state at a specified point on a triggering input called the clock. Change state either at the positive (rising) edge, or at the negative (falling) edge of the clock signal.
Clock signal
Positive edges Negative edges

FLIP-FLOPS (1/2)
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S-R flip-flop, D flip-flop, and J-K flip-flop. Note the > symbol at the clock input.
S
C R Q'

D
C

Q
Q'

J
C K

Q
Q'

Positive edge-triggered flip-flops


S C R Q' Q D C Q' Q J C K Q' Q

FLIP-FLOPS (2/2)

Negative edge-triggered flip-flops

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sequential circuit

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S-R flip-flop: On the triggering edge of the clock pulse,


R = HIGH and S = LOW Q becomes LOW (RESET state) S = HIGH and R = LOW Q becomes HIGH (SET state) Both R and S are LOW No change in output Q Both R and S are HIGH Invalid!

Characteristic table of positive edge-triggered SR flip-flop: S R CLK Q(t+1) Comments


S C R Q' Q
0 0 1 1 0 1 0 1 X Q(t) 0 1 ? No change Reset Set Invalid

S-R FLIP-FLOP

X = irrelevant (dont care) = clock transition LOW to HIGH

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sequential circuit

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D flip-flop: Single input D (data). On the triggering edge of the clock pulse,
D = HIGH Q becomes HIGH (SET state) D = LOW Q becomes LOW (RESET state)

Hence, Q follows D at the clock edge.


Convert S-R flip-flop into a D flip-flop: add an inverter.
D CLK S C R Q' Q

D CLK 1 0

Q(t+1) 1 0

Comments Set Reset

D FLIP-FLOP (1/2)

A positive edge-triggered D flipflop formed with an S-R flip-flop.

= clock transition LOW to HIGH

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sequential circuit

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J-K flip-flop: Q and Q' are fed back to the pulsesteering NAND gates.
No invalid state. Include a toggle state
J = HIGH and K = LOW Q becomes HIGH (SET state) K = HIGH and J = LOW Q becomes LOW (RESET state) Both J and K are LOW No change in output Q Both J and K are HIGH Toggle

J-K FLIP-FLOP (1/2)


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J-K flip-flop circuit:


J Pulse transition detector Q

CLK K

Q'

Characteristic table:
J 0 0 1 1 K 0 1 0 1 CLK Q(t+1) Q(t) 0 1 Q(t)' Comments No change Reset Set Toggle

Q 0 0 0 0 1 1 1 1

J 0 0 1 1 0 0 1 1

K 0 1 0 1 0 1 0 1

Q(t+1) 0 0 1 1 1 0 1 0

J-K FLIP-FLOP (2/2) Q(t+1) = ?

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T flip-flop: Single input version of the J-K flipflop, formed by tying both inputs together.
T
Q CLK Pulse transition detector Q'

T CLK

Q Q'

C
K

Characteristic table:
Q T 0 1 0 1 Q(t+1) 0 1 1 0

T 0 1

CLK

Q(t+1) Q(t) Q(t)'

Comments No change Toggle

0 0 1 1

T FLIP-FLOP

Q(t+1) = ?
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S-R, D and J-K inputs are synchronous inputs, as data on these inputs are transferred to the flipflops output only on the triggered edge of the clock pulse.

Asynchronous inputs affect the state of the flipflop independent of the clock; example: preset (PRE) and clear (CLR) [or direct set (SD) and direct reset (RD)].
When PRE=HIGH, Q is immediately set to HIGH. When CLR=HIGH, Q is immediately cleared to LOW.

ASYNCHRONOUS INPUTS (1/2)


CS2100 sequential circuit

Flip-flop in normal operation mode when both PRE and CLR are LOW.
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A J-K flip-flop with active-low PRESET and CLEAR asynchronous inputs.


PRE J PRE Q Pulse transition detector

J C

Q
CLK

K
CLR CLK PRE CLR

Q'

K CLR

Q'

J = K = HIGH

Preset

Toggle

Clear

ASYNCHRONOUS INPUTS (2/2)


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SYNCHRONOUS SEQUENTIAL CIRCUITS


Building blocks: logic gates and flip-flops. Flip-flops make up the memory while the gates form one or more combinational subcircuits. We have discussed S-R flip-flop, J-K flipflop, D flip-flop and T flip-flop.

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sequential circuit

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FLIP-FLOP CHARACTERISTIC TABLES

Each type of flip-flop has its own behaviour, shown by its characteristic table.
J 0 0 1 1 K 0 1 0 1 Q(t+1) Q(t) 0 1 Q(t)' Comments No change Reset Set Toggle

S 0 0 1 1

R 0 1 0 1

Q(t+1) Q(t) 0 1 ?

Comments No change Reset Set Unpredictable

D 0 1

Q(t+1) 0 1 Reset Set

T 0 1

Q(t+1) Q(t) Q(t)' No change Toggle

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sequential circuit

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FLIP-FLOP EXCITATION TABLES (2/2)

Excitation tables: given the required transition from present state to next state, determine the flip-flop input(s).
Q 0 0 1 1 Q+ 0 1 0 1 J 0 1 X X K X X 1 0
Q 0 0 1 1 Q+ 0 1 0 1 S 0 1 0 X R X 0 1 0

JK Flip-flop
Q 0 0 1 1 Q+ 0 1 0 1 D 0 1 0 1

SR Flip-flop
Q 0 0 1 1 Q+ 0 1 0 1 T 0 1 1 0

D Flip-flop

T Flip-flop
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Counters are sequential circuits that cycle through some states. They can be implemented using flip-flops. Two examples are shown: Ring counter and Johnson counter. Implementation is simple: using D flipflops. (This and next few slides on ring counter and Johnson counter are just for your reading.)

COUNTERS
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RING COUNTERS

An n-bit ring counter cycles through n states. Example: A 6-bit ring counter (also called mod-6 ring counter)
PRE
D Q

Q0

D Q

Q1

D Q

Q2

D Q

Q3

D Q

Q4

D Q

Q5

CLR CLK

Clock 0 1 2 3 4 5

Q0 1 0 0 0 0 0

Q1 0 1 0 0 0 0

Q2 0 0 1 0 0 0

Q3 0 0 0 1 0 0

Q4 0 0 0 0 1 0

Q5 0 0 0 0 0 1
CS2100

100000 000001 000010 000100


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010000 001000

JOHNSON COUNTERS (1/2)


An n-bit Johnson counter (also called twisted-ring counter) cycles through 2n states. Example: A 4-bit John counter (also called mod-8 Johnson counter)

D Q

Q0

D Q

Q1

D Q

Q2

D Q Q'

Q3'

CLR CLK
Clock 0 1 2 3 4 5 6 7 Q0 0 1 1 1 1 0 0 0 Q1 0 0 1 1 1 1 0 0 Q2 0 0 0 1 1 1 1 0 Q3 0 0 0 0 1 1 1 1

0000
0001 0011 0111 1111
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1000 1100 1110

JOHNSON COUNTERS (2/2)


Requires decoding logic for the states. Example: Decoding logic for a 4-bit Johnson counter.
Clock 0 1 2 3 4 5 6 7 A 0 1 1 1 1 0 0 0 B 0 0 1 1 1 1 0 0 C 0 0 0 1 1 1 1 0 D 0 0 0 0 1 1 1 1
Decoding

A'.D' A.B' B.C' C.D' A.D A'.B B'.C C'.D

A' D'
A B' B C' C D' A D A' B
CS2100 sequential circuit

State 0 State 1 State 2 State 3 State 4 State 5


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B' C C' D

State 6 State 7

thank you

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sequential circuit

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