Reflections on the CPU and Instruction Set

Simplicity The MSP430 was designed from the start for low power consumption. Most programs today are written in C so the processor is designed for efficient compilation rather than hand-crafted assembly code A straightforward set of 16 registers that includes all the special-purpose registers as well as the general-purpose registers for addresses and data

Is the MSP430 a RISC ?

Small set of general-purpose instructions Large bank of general-purpose registers Loadstore architecture Single-cycle execution

Conclusions on the Instruction Set

Orthogonality is wonderful : meaning that all addressing modes can be used with all instructions Access to memory is simple and uniform The constant generator makes programs faster and more compact with no effort from the programmer

Resets
A reset is a sequence of operations that puts the device into a well-defined state, from which the users program may start A reset is also generated if the device detects a serious fault in hardware or software from which the users program cannot be expected to recover

Resets
MSP430 has two levels of reset, depending on whether the reset was caused by hardware or software Power-on Reset (POR) : This is generated by severe conditions related to hardware Power-up Clear (PUC) :This always follows a power-on reset. It is generated when software appears to be out of control

Power-on Reset (POR)

POR is raised if the supply voltage drops to so low a value that the device may not work correctly. Almost all current MSP430s include a brownout detector. A low external signal on the RST/NMI pin resets the device if the pin is configured for the reset function rather than the nonmaskable interrupt

Power-on Reset (POR)

Larger variants have a more comprehensive supply voltage supervisor (SVS). This is configurable, unlike the brownout detector. It sets the SVSFG flag if the voltage falls below the programmed level and can optionally reset the device

Power-up Clear (PUC)

Generated when software appears to be out of control in the following ways The watchdog timer overflows in watchdog mode. The watchdog is active by default and must either be disabled or regularly cleared before it rolls over

Power-up Clear (PUC)

An attempt is made to write to the watchdog control register WDTCTL without the correct password 0x5A (available as the symbol WDTPW) in the upper byte The registers for the flash memory controller, FCTLn, are protected by a password in the same way as WDTCTL. The value is 0xA5, available as the constant FWKEY.

Power-up Clear (PUC)

An attempt to fetch an instruction from the range of addresses reserved for peripheral registers

Conditions after Reset

The RST/NMI pin is configured for reset Most input/output pins are configured as digital inputs. The status register is cleared The watchdog timer starts in watchdog mode. The program counter is loaded with the the reset vector, which is stored in the word at 0xFFFE

Interrupt flag register 1

For large programs or networked systems it may be necessary to identify the source of a reset Most information are in the interrupt flag register 1

Interrupt flag register 1

This may contain the following flags, depending on the variant: WDTIFG shows that the watchdog timed out or its security key was violated. OFIFG indicates an oscillator RSTIFG shows a reset caused by a signal on the RST/NMI pin. PORIFG is set for a power-on reset. NMIIFG flags a nonmaskable interrupt (not reset) caused by a signal on the RST/NMI pin.

Clock System
All microcontrollers contain a clock module to drive the CPU and peripherals clock module provides three outputs: Master clock, MCLK is used by the CPU and a few peripherals. Sub-system master clock, SMCLK is distributed to peripherals. Auxiliary clock, ACLK is also distributed to peripherals

Clock System

Clock System
Most peripherals choose SMCLK, which is often the same as MCLK and in the megahertz range ACLK, which is typically much slower and usually 32 KHz The frequencies of all three clocks can be divided

Clock System
Up to four sources are available for the clock, depending on the family and variant Low- or high-frequency crystal oscillator, LFXT1: Available in all devices. It is usually used with a low-frequency watch crystal (32 KHz) but can also run with a high-frequency crystal (typically a few MHz) in most devices. An external clock signal can be used instead of a crystal if it is important to synchronize the MSP430 with other devices in the system.

Clock System
High-frequency crystal oscillator, XT2: Similar to LFXT1 except that it is restricted to high frequencies. It is available in only a few devices and LFXT1 (or VLO) is used if XT2 is missing

Clock System
Internal very low-power, low-frequency oscillator, VLO: Available in only the more recent MSP430F2xx devices.

It provides an alternative to LFXT1 when the accuracy of a crystal is not needed.

Clock System
Digitally controlled oscillator, DCO: Available in all devices and one of the highlights of the MSP430. It is basically a highly controllable RC oscillator that starts in less than 1micro sec in newer devices

Clock System
ACLK comes from a low-frequency crystal oscillator
at 32 KHz.
Both MCLK and SMCLK are supplied by the DCO with a frequency of around 1 MHz. This is stabilized by the FLL where present. frequency can be raised provided that VCC is high enough to support it