Final Project Presentation

Development of OVM Verification Environment for Functional Verification of Quad Serial Peripheral Interface

Kiran N.
CGB0910003 M. Sc. [Engg.] in VLSI System Design

Academic Guide : Cyril Prasanna Raj . P HoD, Dept. of EEE, MSRSAS, Bangalore.

Industrial Guide : Linu Thomas, Manager, IC Design Engineering, Broadcom (I) Pvt. Ltd.
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Aim of the Project

To design and develop an OVM based verification environment for the Quad SPI IP and attain maximum possible coverage for the same

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Top Level Block Diagram

QSPI

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Project Objectives
To review literature on Quad SPI module, OVM and verification environments To study Quad SPI module functionality and arrive at functional specifications for verification environment To develop OVM based verification environment for Quad SPI To identify suitable test cases and verify functionality of Quad SPI To perform functional verification and achieving maximum possible coverage of the QSPI module for various test cases.

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Methods and Methodology

Literature review for Quad SPI protocol IP has been carried out by referring reviewed journals, books, manuals and related documents. Literature review for OVM verification environment has been carried out by referring reviewed journals, books, manuals and related documents. Literature review for developing suitable test cases for attain maximum coverage has been carried out by referring reviewed journals, books, manuals and related documents. Based on application and reviewed literature design specifications for the verification environment has been arrived at. The specifications and design of the individual components OVM has been carried out.
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Methods and Methodology

Design of the verification environment has been carried out based on specifications derived using System Verilog hardware design and verification language and integrating the individual components Based on the literature review conducted on quad SPI module test case for its functional verification has been written The functional verification is then carried out using the VCS tools and observations have been documented The waveforms have been debugged using the VERDI tool and any bugs have been reported and rectified. The quad SPI IP has been integrated into the verification environment and tests have been run. The tests have been run using the different test cases in the designed environment using the VCS tool.
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Methods and Methodology

Based on the literature review conducted the techniques used for attaining more coverage for the QSPI design have been adopted.

Coverage driven verification methodologies implemented in order to attain more coverage.

have

been

Maximum coverage for QSPI IP using the VCS tool and the waveform debug tool VERDI is reported.

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Introduction
Quad SPI module is an advanced version of the commonly used Serial Peripheral Interface (SPI) module. The SPI is used for synchronous serial data communication between a host processor and the peripherals connected to it. It is master-slave protocol type of interface. It was primarily developed by Motorola In its most general form the SPI consists of two data lines and two control lines.

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Introduction cont..
The two control lines are Chip Select(CS) which is used to select the corresponding peripheral device connected and then Clock Select (SCLK) which is used for synchronizing the data transfer. The two data lines are for the data input and output. The SPI in general consists of a shift register which is used to shift data into and out of the interface and a serial buffer which stores the data when the module is made inactive. The Quad SPI module consists of four data lines and a characteristic two control lines. The QSPI module which is verified in this project can also operate in dual mode in which there are two data lines and two control lines

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Introduction cont..
The QSPI module finds its application in System On Chip (SoC) designs to assists the hard core processor to communicate with the peripherals attached to it. Since the interconnect is small the noise immunity is best in case of serial communication which the QSPI uses and also the frequency of operation is around 6MHz is which is ideal and well suited for on chip operations. Verification methodologies are a must to tackle verification complexities and design closure times. Out of the popular verification methodologies (Open Verification Methodology) OVM preferred in the industry for SoC designs.

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Introduction cont..
OVM is Functional verification methodology developed using the System verilog (Hardware Design Verification language)HDVL The three main building blocks of OVM include OVM_ components, OVM_env and OVM_test. Component classes include 1. Sequencer 2. Driver 3. Monitor 4. Scoreboard Env class helps connect all the components together. QSPI
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Scope of the project

The OVM verification environment is a reusable entity which can be used further for many serial communication IP with few required adjustment made into the design and has a long life span. Since the serial communication protocols are preferred means of data communication in SOC designs and also QSPI works at highest frequency comparatively and hence it has tremendous implementation scope. QSPI being a relatively new technology also has a long life span till there is new advancement in serial interface technology.

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Motivation for the project

The motivation for the project is developing an OVM based verification environment which is able to perform the functional verification of the QSPI module and obtain a respectable coverage to avoid costly respins. Without it saving time and improving the verification effort by covering all the difficult corners of design and attaining maximum possible coverage will be difficult The QSPI module is capable of high through puts of up to 80MHz and hence from an integral part of the SoC designs. Without it faster serial data transfer will not be possible and hence in turn restricting the overall performance of the SoC

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Challenges faced during the project

The QSPI is a relatively new and advanced interface so there are not many supporting documents other than few data sheets to understand the behavior of module once implemented hence few key insights into the cases or modes of operation are missing for developing a stronger verification effort. Developing the OVM verification environment from scratch and integrate all the component classes with the Design Under Test DUT (QSPI) and ensuring proper working of the entire verification environment Attaining high values of coverages as the some of the functionality depends on other blocks inside in SoC

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Literature Review
SPI module plays an important role in the embedded systems and SoC designs as they provide a high speed and high noise immunity mode of communication between the host processor and the corresponding peripheral connected.[1] The goal of adopting a particular methodology is to obtain maximum level of confidence in the quality of the design in a given amount of time and engineering resources. For achieving this goal methodologies use assertions, functional abstraction, automation through randomization, reuse all at the same time.OVM supports all the above features and also functional verification. [2]

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Literature Review cont..

Verification begins from the specifications: the design specs and the test plans. The goal for the verification engineers is to create, based on these specs, a full verification environment, and do that as fast as possible, with minimal effort. Thus the enablers must be:
Means to capture all SOC specifications and complexity in an executable form Automation of all verification activities Reusability of verification components. [3]

For good quality of verification always functional verification of the design should be prioratized. Test writing writing should be intense and attack the design by first random tests and then constraining the random vectors and finally usage of assertion and directed tests to plug holes in verification[4][5]
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Literature Review Comparison

Sl no. 1. Title A methodology for timely verification of Complex SoC Author Guy Regev, Peretz Landau Year 2009 Specificatio Merits and n demerits System/SW based verification methodolog y, bottom up methodolgy System based verification, test polarisation to pin point system bugs +High coverage achieved, -covering BMP functionality

2.

A Methodology for the Verification of a System on Chip

D. Geist, G. Brain, T. Arons, M. Slavkin, Y. Nustov, M. Farkas, K. Holtz

2008

+efficient verification of the entire system on chip design

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Summary of Literature Summary

The present SPI module used as interface between host processor and external peripherals currently operates at a frequency of 30MHz with a single data_in line. Quad SPI module has 4 data lines which can be used for high speed data transfer. It operates at a higher frequency of 60 MHz. The present verification environment is suitable for verification of low speed interface and so a new verification environment has to developed for the verification of the QSPI module in a short duration. For speedy verification of sub blocks of SOC designs OVM is sought after methodology in the industry

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Design of the QSPI

AXI Syste m bus

Interface to control register data transfer

SPI data Lines

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Design of the QSPI cont

QSPI primarily consists of 3 blocks Boot Serial Peripheral Interface (BSPI) Master Serial Peripheral Interface (MSPI) Read Ahead FIFO (RAF). 1.Boot SPI The boot SPI is purely for the fast read data read operation at the boot time. The AXI bus interfaced with the BSPI is purely used for read operation and no write is allowed. During the boot the BSPI is programmed to automatically and independently read from the flash drive connected the processor hence saving valuable processing cycles.
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Design of the QSPI cont

2.Master SPI This module acts as the master for the several peripherals connected to the processor sending commands for the read and write operations through the four data lines. The MSPI is configured using the APB bus which is used for register configuration. 3. Read ahead FIFO The read operation from the flash memory peripheral is done directly from the BSPI or can be done through the RAF module for better control over data extraction. RAF is a DMA like module which provides efficient access. It works on a separate clock called Rbus clock.

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Verification Env for QSPI

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Components of OVM env

Sequencer: A sequence is series of transaction and sequencer is used to for controlling the flow of transaction generation. A sequence of transaction is defined by extending ovm_sequence class. ovm_sequencer does the generation of this sequence of transaction, ovm_driver takes the transaction from Sequencer and processes the packet/ drives to other component or to DUT. Generator: The generator is class which decides the actual data that needs to sent into the DUT check for the desired functionality. The different modes of operation and all possible scenarios should be covered. For this the test generator class has been programmed with knobs which decide which particular operation to check for. Checker: The checker class is design to check for the correlation between the results obtained to the expected output related to the particular type input stimulus provided to the DUT by the test generator. The checker helps in debugging any faults in the design.
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Simulation results for BSPI

Start address of 0600h

AXI interf ace

Output at all four data lines

Data read from flash

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Simulation results for MSPI

AXI bus idle Comman d (1C h)for fast read

APB interf ace

Read address M.S.Ramaiah School of Advanced Studies

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Simulation results for RAF

Read operation

Register write operati on

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Coverage Analysis
Coverage value represents the verification effort carried on the designs.

Line Coverage: It is the measure to check for the total number of lines of code which is being executed.
Condition Coverage: It is the measure to check for completeness about all the conditions present in the code. FSM Coverage: It is a measure to find out the state transitions & unvisited states in an FSM Toggle Coverage: It measures the transitions of the stimulus [changes in the signal logic] w.r.t the execution of the code.
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Regression Result

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Coverage Report for QSPI

The final coverages obtained Line :89.88 Conditional: 83.63 Toggle: 58.93

100 80 60 40 20 0 Coverage

Line Conditional Toggle

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Applications of the Project

The QSPI finds its application in almost any and every SoC designs and in swift data transmission applications like digital streaming, digital signal processing. The QSPI can communicate with wide range of peripherals like flash memories ,sensors, ADC, DAC,LCD displays etc The verification environment can be used for other serial and other on chip communication protocol and interfaces. The verification environment is tool independent as System Verilog programming language is used for coding and hence the same design can used for other tools from other EDA tool vendors.

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Conclusion
The design implementation flow and the verification methodology adopted for verifying the QSPI has been designed and verified. The environment has been designed, which is developed using the OVM base classes is reusable and configurable according to any serial communication design A verification environment has been developed to verify this QSPI design and functional coverage is reported for the implemented design. Function simulation and function coverage is carried out using Synopsys VCS, VERDI tools
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Conclusion cont..
Functional verification of QSPI is carried out by applying constraint random test cases. Line coverage is reported 89.32%, conditional coverage is reported at 83.62% and toggle coverage is reported at 58.33% for constraints random test cases The coverages values obtained are only for the functionality of the module which is required for the SoC on which is implemented and hence the overall coverage of the module can be increased if the entire functionality of the design is verified

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Recommendations for Future work

The verification environment developed can enhance by introducing more blocks which help debug the design in a easier like monitor, score board etc The present verification environment can be enhanced for verification of other communication protocols with suitable modifications the test cases block of the design The verification environment design complexity can be reduced by using the enhanced features of the System verilog language which is used to design it. The verification environment can be tool and language independent so that any design can be verified on any platform
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Literature

1.

Books
Santanu Chattopadhyay (2010), Embedded System Design, PHI learning pvt. Ltd., USA.

2.

Janick Bergeron (2006), Verification methodology manual for

SystemVerilog, Springer Pvt. Ltd., London.

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Literature
Technical Papers
3. D. Geist, G. Biran, T. Arons, M. Slavkin, Y. Nustov, M. Farkas, K. Holtz (2008), A Methodology For the Verification of a System on Chip, DAC, Louisiana.

4. Pretez landau, Guy Regev (2009), A Methodology for Timely Verification of a Complex SoC, Percello Ltd., USA.

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Literature
Technical Papers Contd.,
5. Parag Goel, Pushkar Naik (October 22nd 2011), System Verilog

+ OVM: Migrating Verification Challenges and Maximizing

Reuseability , Applied Microelectronics.

6. A. Molina and O. Cadenas (2007), Functional verification: approaches and challenges, Computer architecture Department, Universitat politecnica de catalunya, Barcelona, Spain.

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Literature

7.

Data sheets
S25FL128R, S25FL256R, S25FL512R Marketing

Requirements Specification, Spansion Datasheet.

8.

Daniel

McKenna,

Using

the

QuadSPI

Module

on

MPC56xxS, freescale semiconductors, application note,

Document Number: AN4186

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Thank You

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