ECE369 Chapter 2

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Instruction Set Architecture

A very important abstraction interface between hardware and low-level software standardizes instructions, machine language bit patterns, etc. advantage: different implementations of the same architecture disadvantage: sometimes prevents using new innovations

Modern instruction set architectures: IA-32, PowerPC, MIPS, SPARC, ARM, and others

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Instructions:
Language of the Machine Well be working with the MIPS instruction set architecture Simple instruction set and format Similar to other architectures developed since the 1980's Almost 100 million MIPS processors manufactured in 2002 used by NEC, Nintendo, Cisco, Silicon Graphics, Sony,
1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 1998 1999 2000 2001 2002 Other SPARC Hitachi SH PowerPC Motorola 68K MIPS IA-32 ARM

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The MIPS Instruction Set

Used as the example throughout the book Stanford MIPS commercialized by MIPS Technologies (www.mips.com) Large share of embedded core market Applications in consumer electronics, network/storage equipment, cameras, printers, Typical of many modern ISAs See MIPS Reference Data tear-out card, and Appendixes B and E

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MIPS arithmetic
All instructions have 3 operands Operand order is fixed (destination first) Example: C code: MIPS code: a = b + c add a, b, c (well talk about registers in a bit) The natural number of operands for an operation like addition is threerequiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple

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MIPS arithmetic
Design Principle: simplicity favors regularity. Of course this complicates some things... C code: MIPS code: a = b + c + d; add a, b, c add a, a, d

Operands must be registers, only 32 registers provided Each register contains 32 bits Design Principle: smaller is faster. Why?

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Registers vs. Memory

Arithmetic instructions operands must be registers, only 32 registers provided Compiler associates variables with registers What about programs with lots of variables

Control Memory Datapath

Processor

Input

Output
I/O

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Memory Organization
Viewed as a large, single-dimension array, with an address. A memory address is an index into the array "Byte addressing" means that the index points to a byte of memory.

0 1 2 3 4 5 6 ...

8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data

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Memory Organization
Bytes are nice, but most data items use larger "words" For MIPS, a word is 32 bits or 4 bytes. 0 32 bits of data 4 32 bits of data Registers hold 32 bits of data 32 bits of data 8 12 32 bits of data ... 232 bytes with byte addresses from 0 to 232-1 230 words with byte addresses 0, 4, 8, ... 232-4 Words are aligned i.e., what are the least 2 significant bits of a word address?

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Instructions
Load and store instructions Example: C code: A[12] = h + A[8]; # $s3 stores base address of A and $s2 stores h MIPS code: lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 48($s3) Can refer to registers by name (e.g., $s2, $t2) instead of number Store word has destination last Remember arithmetic operands are registers, not memory! Cant write: add 48($s3), $s2, 32($s3)

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Instructions
Example: C code: g = h + A[i];

# $s3 stores base address of A and # g,h and i in $s1,$s2 and $s4 Add $t1,$s4,$s4 Add $t1,$t1,$t1 Add $t1,$t1,$s3 Lw $t0,0($t1) Add $s1,$s2,$t0

t1 = 2*i t1 = 4*i t1 = 4*i + s3 t0 = A[i] g = h + A[i]

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So far weve learned:

MIPS loading words but addressing bytes arithmetic on registers only Instruction add $s1, $s2, $s3 sub $s1, $s2, $s3 lw $s1, 100($s2) sw $s1, 100($s2) Meaning $s1 = $s2 + $s3 $s1 = $s2 $s3 $s1 = Memory[$s2+100] Memory[$s2+100] = $s1

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Policy of Use Conventions

Name Register number 0 $zero 2-3 $v0-$v1 4-7 $a0-$a3 8-15 $t0-$t7 16-23 $s0-$s7 24-25 $t8-$t9 28 $gp 29 $sp 30 $fp 31 $ra Usage the constant value 0 values for results and expression evaluation arguments temporaries saved more temporaries global pointer stack pointer frame pointer return address

Register 1 ($at) reserved for assembler, 26-27 for operating system

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MIPS Format

Instructions, like registers and words are also 32 bits long

add $t1, $s1, $s2 Registers: $t1=9, $s1=17, $s2=18

Fetch,Decode,Execute, PC !!

Instruction Format:
000000 op 10001 rs 10010 rt 01001 rd
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00000 shamt

100000 funct

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Our Goal
add $t1, $s1, $s2 ($t1=9, $s1=17, $s2=18) 000000 10001 10010 01001 00000 op rs rt rd shamt 100000 funct

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MIPS Format

How about lw $s1, 100($s2)

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Machine Language
Consider the load-word and store-word instructions, What would the regularity principle have us do? New principle: Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions other format was R-type for register Example: lw $t0, 32($s2) 35 op 18 rs 9 rt 32 16 bit number

Where's the compromise?

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Summary
Nam e Register num ber Usage 0 the constant value 0 $z ero 2-3 values for results and expression evaluation $v 0-$ v1 4-7 arguments $a 0-$ a3 8-15 temporaries $t 0-$ t7 in s t r u c ft io rnm o p r s o at 16-23 saved $s 0-$ s7 add R 0 re 24-25 more temporaries $t 8-$ t9 28 global pointer $g p sub R 0 re 29 stack pointer $s p lw I 3 5 re 30 frame pointer $f p sw I 4 3 re 31 return address $r a

r t r d s h a mf ut n cat d d r e s g re g re g 0 3 2 n a g re g re g 0 3 4 n a g re g n a n a n a a d d re s g re g n a n a n a a d d re s

A[300]=h+A[300] Lw $t0,1200($t1) Add $t0, $s2, $t0 Sw $t0, 1200($t1)

# $t1 = base address of A, $s2 stores h # use $t0 for temporary register Op rs,rt,address Op,rs,rt,rd,shamt,funct Op,rs,rt,address
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35,9,8,1200 0,18,8,8,0,32 43,9,8,1200 18

Summary of Instructions We Have Seen So Far

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Shift and Logical Operations

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Summary of New Instructions

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Control Instructions

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Using If-Else

$s0 = f $s1 = g $s2 = h $s3 = i $s4 = j $s5 = k

Where is 0,1,2,3 stored?

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Addresses in Branches
Instructions: bne $t4,$t5,LabelNext instruction is at Label if $t4$t5 beq $t4,$t5,LabelNext instruction is at Label if $t4=$t5 Formats: I op rs rt 16 bit address

What if the Label is too far away (16 bit address is not enough)

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Addresses in Branches and Jumps

Instructions: bne $t4,$t5,Label beq $t4,$t5,Label j Label Formats:

if $t4 != $t5 if $t4 = $t5 Next instruction is at Label

I J

op op

rs

rt

16 bit address

26 bit address

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Control Flow
We have: beq, bne, what about Branch-if-less-than? If (a<b) # a in $s0, b in $s1

slt $t0, $s0, $s1 bne $t0, $zero, Less

# t0 gets 1 if a<b # go to Less if $t0 is not 0

Combination of slt and bne implements branch on less than.

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While Loop
While (save[i] == k) i = i+j; # i, j and k correspond to registers # $s3, $s4 and $s5 # array base address at $s6

Loop: add $t1, $s3, $s3 add $t1, $t1, $t1 add $t1, $t1, $s6 lw $t0, 0($t1) bne $t0, $s5, Exit add $s3, $s3, $s4 j loop Exit:
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What does this code do?

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Overview of MIPS
simple instructions all 32 bits wide very structured, no unnecessary baggage only three instruction formats R I J op op op rs rs rt rt rd shamt funct

16 bit address

26 bit address

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What is the use of $ra?

Policy of Use Conventions
Name Register number 0 $zero 2-3 $v0-$v1 4-7 $a0-$a3 8-15 $t0-$t7 16-23 $s0-$s7 24-25 $t8-$t9 28 $gp 29 $sp 30 $fp 31 $ra Usage the constant value 0 values for results and expression evaluation arguments temporaries saved more temporaries global pointer stack pointer frame pointer return address

Register 1 ($at) reserved for assembler, 26-27 for operating system

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Example
swap(int v[], int k); { int temp; temp = v[k] v[k] = v[k+1]; v[k+1] = temp; }

Let $s5 store k value and $s4 store base address of the v[]

Byte addressing problem???

swap: muli $s2, $s5, 4 add $s2, $s4, $s2 : swap: muli $s2, $s5, 4 add $s2, $s4, $s2 lw $t15, 0($s2) lw $t16, 4($s2) sw $t16, 0($s2) sw $t15, 4($s2) jr $31

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Summary

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Other Issues
More reading: support for procedures linkers, loaders, memory layout stacks, frames, recursion manipulating strings and pointers interrupts and exceptions system calls and conventions Some of these we'll talk more about later We have already talked about compiler optimizations

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Nested Procedures,

function_main(){ function_a(var_x); : return; } function_a(int size){ function_b(var_y); : return; } function_b(int count){ : return; }

/* passes argument using $a0 */ /* function is called with jal instruction */

/* passes argument using $a0 */ /* function is called with jal instruction */

Resource Conflicts ???

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Function Call and Stack Pointer

jr
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Recursive Procedures Invoke Clones !!!

int fact (int n) { if (n < 1 ) return ( 1 ); else return ( n * fact ( n-1 ) ); } n corresponds to $a0 Program starts with the label of the procedure fact How many registers do we need to save on the stack?

Registers $a0 and $ra

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Factorial Code
200 fact:addi $sp, $sp, -8 204 sw $ra, 4($sp) sw $a0, 0($sp) slti beq addi addi jr addi jal lw lw addi mult jr $t0, $a0, 1 # is n<1? $t0, $zero, L1 # if not go to L1 $v0, $zero, 1 $sp, $sp, 8 $ra $a0, $a0, -1 fact $a0, 0($sp) $ra, 4($sp) $sp, $sp,8 $v0,$a0,$v0 $ra : 100 fact(3) 104 add . ra = 104 a0= 3 sp= 40 vo=

L1: 236 240

# call fact(n-1) # restore n # restore address # pop 2 items # return n*fact(n-1) # return to caller
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What is the Use of Frame Pointer?

Variables local to procedure do not fit in registers !!!

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Elaboration
Name Register number 0 $zero 2-3 $v0-$v1 4-7 $a0-$a3 8-15 $t0-$t7 16-23 $s0-$s7 24-25 $t8-$t9 28 $gp 29 $sp 30 $fp 31 $ra Usage the constant value 0 values for results and expression evaluation arguments temporaries saved more temporaries global pointer stack pointer frame pointer return address

What if there are more than 4 parameters for a function call? Addressable via frame pointer References to variables in the stack have the same offset Use of jal? Saves address of the next instruction that follows jal into $ra Procedure return can now be simply jr $ra 39
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Data and Stack Segments

Given the following initial layout of memory Each box represents a word (two bytes), $S0 initially contains the value 5, what is the result of each of the following instructions? (Assume that each instruction begins with memory laid out as shown) How is memory affected by: sw $S0, 4($sp) What is the value in $S0 after lw $S0,0($sp) What is contained in $S0 after lw $S1,-4($sp) lw $S0,6($s1) What is contained in $S0 after lw $S1,-2($sp) lw $S0,0($S1) Write the sequence of instructions to store contents of $S0 into address stored in $sp+6
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Using If-Else

$s1-$s5: g-k

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Jump Address Table

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MIPS Example, Use of Jump Address Table

Name Register number 0 $zero 2-3 $v0-$v1 4-7 $a0-$a3 8-15 $t0-$t7 16-23 $s0-$s7 24-25 $t8-$t9 28 $gp 29 $sp 30 $fp 31 $ra

Usage the constant value 0 values for results and expression evaluation arguments temporaries saved more temporaries global pointer stack pointer frame pointer return address
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Using Jump Table

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Same Code, this time using If-Else

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CPI

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Arrays vs. Pointers

clear1( int array[ ], int size) { int i; for (i=0; i<size; i++) array[i]=0; } clear2(int* array, int size) { int* p; for( p=&array[0]; p<&array[size]; p++) *p=0; }

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Clear1
clear1( int array[ ], int size) { int i; for (i=0; i<size; i++) array[i]=0; }

array in $a0 size in $a1 i in $t0

add loop1: add add add sw addi slt bne

$t0,$zero,$zero # i=0, register $t0=0 $t1,$t0,$t0 # $t1=i*2 $t1,$t1,$t1 # $t1=i*4 $t2,$a0,$t1 # $t2=address of array[i] $zero, 0($t2) # array[i]=0 $t0,$t0,1 # i=i+1 $t3,$t0,$a1 # $t3=(i<size) $t3,$zero,loop1 # if (i<size) go to loop1
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Clear2

for (i=0; i<size; i++) array[i]=0;

clear2(int* array, int size) { int* p; for( p=&array[0]; p<&array[size]; p++) *p=0; }

Array and size to registers $a0 and $a1

loop2:

add sw addi add add add slt bne

$t0,$a0,$zero $zero,0($t0) $t0,$t0,4 $t1,$a1,$a1 $t1,$t1,$t1 $t2,$a0,$t1 $t3,$t0,$t2 $t3,$zero,loop2

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# p = address of array[0] # memory[p]=0 # p = p+4 # $t1 = size*2 # $t1 = size*4 # $t2 = address of array[size] # $t3=(p<&array[size]) # if (p<&array[size]) go to loop2 49

Clear2, Version 2
clear2(int* array, int size) { int* p; for( p=&array[0]; p<&array[size]; p++) *p=0; }

Array and size to registers $a0 and $a1

add add add add sw addi slt bne

$t0,$a0,$zero $t1,$a1,$a1 $t1,$t1,$t1 $t2,$a0,$t1 $zero,0($t0) $t0,$t0,$4 $t3,$t0,$t2 $t3,zero,loop2

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# p = address of array[0] # $t1 = size*2 # $t1 = size*4 # $t2 = address of array[size] # memory[p]=0 # p = p+4 # $t3=(p<&array[size]) # if (p<&array[size]) go to loop2 50

loop2:

Array vs. Pointer

loop1: add add add add sw addi slt bne $t0,$zero,$zero $t1,$t0,$t0 $t1,$t1,$t1 $t2,$a0,$t1 $zero, 0($t2) $t0,$t0,1 $t3,$t0,$a1 $t3,$zero,loop1 # i=0, register $t0=0 # $t1=i*2 # $t1=i*4 # $t2=address of array[i] # array[i]=0 # i=i+1 # $t3=(i<size) # if (i<size) go to loop1

add add add add sw slt bne

$t0,$a0,$zero $t1,$a1,$a1 $t1,$t1,$t1 $t2,$a0,$t1 $zero,0($t0) addi $t0,$t0,$4 $t3,$t0,$t2 $t3,zero,loop2

# p = address of array[0] # $t1 = size*2 # $t1 = size*4 # $t2 = address of array[size] # memory[p]=0 # p = p+4 # $t3=(p<&array[size]) # if (p<&array[size]) go to loop2
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loop2:

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Big Picture

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Compiler

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Addressing Modes

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Our Goal
add $t1, $s1, $s2 ($t1=9, $s1=17, $s2=18) 000000 10001 10010 01001 00000 op rs rt rd shamt 100000 funct

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Assembly Language vs. Machine Language

Assembly provides convenient symbolic representation much easier than writing down numbers e.g., destination first Machine language is the underlying reality e.g., destination is no longer first Assembly can provide 'pseudoinstructions' e.g., move $t0, $t1 exists only in Assembly would be implemented using add $t0,$t1,$zero When considering performance you should count real instructions

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Summary
Instruction complexity is only one variable lower instruction count vs. higher CPI / lower clock rate Design Principles: simplicity favors regularity smaller is faster good design demands compromise make the common case fast Instruction set architecture a very important abstraction indeed!

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