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Memory Capacitys How Ram is used? Architecture of a RAM


Working of 6T RAM Cell Problems faced in 6T

About 7T, 8T & 9T Conclusion References


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Invented at IBM by alanshugart in1967 8-Inch 100Kb 5.25 inches 360kb 3.5 inch 1.44Mb

1024 Terabytes = 1 Petabyte 1024 Petabytes = 1 Exabyte 1024 Exabytes = 1 Zettabyte 1024 Zettabytes = 1 Yottabyte 1024 Yottabytes = 1 Brontobyte 1024 Brontobytes = 1 Geopbyte

A D D R E S S

X-DRIVER

DECODER

MEMORY CELL

MEMORY CELL

Y-DECODER

Process variations will limit 90nm SRAMs to around 0.7V operation due to degraded RSNM and reduced write margin. Small transistors combine with random and systematic process variations to cause a large spread in RSNM that leads to destructive read errors. Standard write operation depends on the ratio of current and process variations makes this ratio difficult to maintain Vdd decrease leading to write errors.
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SNM For WRITE access versus temperature and process corner(TT,WW,SS,WS and SW)at vdd=0.3v(a) and vdd =0.6v.

Read operation occurs exactly similar to that of the 6TSRAM.

N5-Transistor is kept ON During WRITE, the feedback is disconnected by switching OFF N5

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For READ operation it uses separate bit line RBL and RWL are as control signal. During Write operation PMOS AND NMOS Transistors of the inverters can be maintained of the minimum width as the read operation is separated. RBL is read according to value stored at the storage nodes when high

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WRITE: the bitlines BL and BLB are driven with the data in the nodes. The footer M9 is switched off during write by making the signal WR go low. This weakens the feed back and hence faster write. During Read WR is kept high so that the data at node stays stable

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PDP Savings SRAM (%) Writing Reading

7(T) 2.80 44.8

8(T) 4.48 -0.9

9(T) 5.64 66.18

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Operating a SRAM device in sub-threshold Region requires sufficient writing ability and good static noise margin for the design. 7T SRAM proposed has best performance in case WRITE. 8T SRAM has best in case of READ. The NEW 9T SRAM Design Combining the advantages of these designs.
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[1] Calhoun, B.H.; Chandrakasan, A.;, "A 256kb Sub-threshold SRAM in 65nm CMOS," Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International, vol., no., pp.25922601, 6-9 Feb 2006 [2] Moradi, F.; Wisland, D.T.; Aunet, S.; Mahmoodi, H.; Tuan Vu Cao;"65NM sub-threshold 11T-SRAM for ultra low voltage applications," SOC Conference, 2008 IEEE International , vol., no.pp.113-118, 17-20 Sept.2008 3] Wang, A.; Chandrakasan, A.P.; Kosonocky, S.V.; , "Optimal supply and threshold scaling for subthreshold CMOS circuits ," VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on, vol., no., pp.5-9,2002 [4] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed. Pearson Education, Inc., 2003.

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[5] Calhoun, B.H.; Chandrakasan, A.P.; , "A 256-kb 65-nm Subthreshold SRAM Design for Ultra-Low-Voltage Operation," SolidStateCircuits, IEEE Journal of , vol.42, no.3, pp.680-688, March 2007 [6] Singh, J.; Pradhan, D.K.; Hollis, S.; Mohanty, S.P.; Mathew, J.; , "Single ended 6T SRAM with isolated read-port for low-power Embeddedsystems," Design, Automation & Test in Europe Conference & Exhibition,2009. DATE '09. , vol., no., pp.917-922, 20-24 April 2009 [7] Azam, T.; Cheng, B.; Cumming, D.R.S.; , "Variability resilient lowpower 7T-SRAM design for nano-scaled technologies," Quality Electronic Design (ISQED), 2010 11th International Symposium on , vol., no., pp.9-14, 22-24 March 2010
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