MULTIPLIER USING REGULAR PARTIAL PRODUCTS

Under The Guidance of: Ms Sakshi ECED TU, Patiala By: Bipin Likhar VLSI Design & CAD (601161004)

Applications of Multipliers
used commonly in processors like digital signal processes(DSPs) and microprocessors. digital filter. Multiplication is an essential arithmetic operation in DSP applications. multimedia applications such as 3D graphics signal processing systems video processing

Classification of Multipliers

Steps for Multiplication

Generating partial products. Summing up all partial products until only two rows remain. Adding the remaining two rows of partial products by using a carry propagation adder.

Methods for Partial Product Generation

Radix 2 booth multiplier Radix 4 modified booth multiplier
Higher radix booth multiplier

Comparison of radix 2, radix 4 and radix 8 algorithm

Problem of isolated 1s in radix-2 is overcome by radix 4.
In radix-8 more number of operations are required to generate {+1,+2, +3, +4, -1, -2, -3, -4}. Speed of Radix 8 is highest among Radix 2, 4 and 8 but the complexity increases.

Literature Review
Sr. No.
1.

AUTHORS
S.Sri Sakthi, N.Kayalvizhi

CONTRIBUTION
Reconfigure the multiplier structure , required only n/4 clock cycle for multiplication. presented a new technique to compute the 2s complement Proposed an approach to generate a regular partial product array .

YEAR
2011

2.

Manoj Sharma , Richa verma

2011

3.

Shiann-Rong Kuang,, Jiun-Ping Wang

2010

4.

Zheng Li, Haimin Chen, Xianwen proposed new technique Yang for the disposal of negative PP based on Radix-4 Booth algorithm.

2010

Contd.
Sr. No.
5.

AUTHORS
Jung-Yup Kang, Member, JeanLuc Gaudiot,

CONTRIBUTION
Presented an algorithm to achieve fast multiplication in twos complement representation . Developed an algorithm to generate regular partial product. Described the data-path and VLSI implementation of a 32x32 bit signed unsigned (MAC) unit.

YEAR
2006

6.

Wen-Chang Yeh and Chein-Wei Jen Aamir A. Farooqui, Vojin G. Oklobdzija

2000

7.

1998

Radix-4 Multiplication

Irregular structure. Number of PP are n/2+1.

Contd.

Regular structure but still n/2+1 PPs rows.

Contd.

PP reduced to n/2 by 2s complement technique. Irregular structure.

Contd.

Taking both above technique , result will be regular PP with n/2 PP rows.

Gaps In The Study

Focus on radix-2 and radix-4, not on higher radix. New methods for finding 2s complement. Recursive modified booth multiplier helps in improving speed as compared to MBE but no emphasis has been given to reduce power dissipation.

Objectives of Proposed Studies

To implement multiplication on higher order radix. Faster methods must be used to find 2s complement. Some methods can be adopted to reduce power dissipation in recursive modified booth multiplier.

References
1. Wen-Chang Yeh and Chein-Wei Jen, High-Speed Booth Encoded Parallel Multiplier Design, IEEE, JULY 2000. 2. Jung-Yup Kang, Jean-Luc Gaudiot A Simple High-Speed Multiplier Design. IEEE, OCTOBER 2006. 3. Edwin de Angel and Earl E. Swartzlander, Jr. Low Power Parallel Multipliers. IEEE,1996. 4. Aamir A. Farooqui, Vojin G. Oklobdzija General Data-Path Organization of a MAC unit for VLSI Implementation of DSP Processors. IEEE,1998.

Contd.
5. Fayez Elguibaly ,A Fast Parallel Multiplier-Accumulator Using the Modified Booth Algorithm. IEEE ,Transactions on Circuits and SystemII VOL. 47 September 2000. 6. Osman Hasan, Skander Kort Automated Formal Synthesis of Wallace Tree Multipliers,. IEEE Transactions on VLSI, 2007. 7. S.Sri Sakthi, N.Kayalvizhi, Power Aware and High Speed Reconfigurable Modified Booth Multiplier. IEEE, February 2011.

Contd.
8. Shiann-Rong Kuang, Jiun-Ping Wang, and Cang-Yuan Guo Modied Booth Multipliers With Regular Partial Product Array. IEEE Transactions on Circuits and SystemII, VOL. 56, NO. 5, MAY 2009. 9. S.Saravanan, M.Madheswaran Design of Hybrid Encoded Booth Multiplier with Reduced Switching Activity Technique and Low Power 0.13m Adder for DSP Block in Wireless Sensor Node. IEEE 2010. 10. Zheng Li, Haimin Chen, Xianwen Yang Research on the disposal of negative partial product for booth algorithm. Information Theory and Information Security (ICITIS), 2010.

Contd.
11. Manoj Sharma Disposition (reduction) of (negative) partial product for Radix 4 Booth's Algorithm. Information and Communication Technologies (WICT), 2011. 12. Behrooz Parhami, Computer Arithmetic Algorithms and Hardware Design,2nd edition.

THANK YOU