Untitled

Integrated Circuits
A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic
Design Methodologies
December 10, 2002
Digital Integrated Circuits2nd
Design Methodologie
The Design Productivity Challenge

Logic Transistors per Chip (K) 10,000,000 .10 1,000,000 m 100,000 .35 m 10,000 1,000 100 2.5 m 10 1 1987 1989 1991 1981 1983 1985
X x X X X X X
100,000,000 Transistor/Staff Month 58%/Yr. compound Complexity growth rate 10,000,000 1,000,000 100,000 10,000 1,000 100 10 2009
21%/Yr. compound Productivity growth rate 1993 1995 1999 2007 1997 2001 2003 2005
A growing gap between design complexity and design productivity Source: sematech97
Design Methodologie
Productivity (Trans./Staff-Month)
A Simple Processor
MEMORY INPUT/OUTPUT
CONTROL
DATAPATH
Design Methodologie
A System-on-a-Chip: Example
Courtesy: Philips
Design Methodologie
Impact of Implementation Choices

100-1000 Energy Efficiency (in MOPS/mW) Domain-specific processor (e.g. DSP) Embedded microprocessor 0.1-1
10-100
Configurable/Parameterizable
Hardwired custom
1-10
None
Somewhat flexible
Fully flexible
Flexibility (or application scope)
Design Methodologie
Design Methodology
Design process traverses iteratively between three abstractions: behavior, structure, and geometry More and more automation for each of these steps
Design Methodologie
Implementation Choices
Digital Circuit Implementation Approaches
Custom
Semicustom
Cell-based
Array-based
Standard Cells Compiled Cells
Macro Cells
Pre-diffused (Gate Arrays)
Pre-wired (FPGA's)
Design Methodologie
The Custom Approach

Intel 4004
Courtesy Intel
Design Methodologie
Transition to Automation and Regular Structures
Intel 4004 (71)
Intel 8080
Intel 8085
Intel 8286
Courtesy Intel
Intel 8486
Design Methodologie
Cell-based Design (or standard cells)

Feedthrough cell Logic cell
Rows of cells
Routing channel
Functional module (RAM, multiplier, )
Routing channel requirements are reduced by presence of more interconnect layers
Design Methodologie
Standard Cell Example
[Brodersen92]
Design Methodologie
Standard Cell The New Generation

Cell-structure hidden under interconnect layers
Design Methodologie
Standard Cell - Example
3-input NAND cell (from ST Microelectronics): C = Load capacitance T = input rise/fall time
Design Methodologie
Automatic Cell Generation
Initial transistor geometries
Placed transistors
Routed cell
Compacted cell
Finished cell
Courtesy Acadabra
Design Methodologie
A Historical Perspective: the PLA

Product terms x0 x1 AND plane x2 OR plane
f0 x0 x1 x2
f1
Design Methodologie
Two-Level Logic
Every logic function can be expressed in sum-of-products format (AND-OR)
minterm
Inverting format (NORNOR) more effective
Design Methodologie
PLA Layout Exploiting Regularity

V DD And-Plane Or-Plane GND
x0 x0 x1 x1 x2 x2 Pull-up devices
f0 f1 Pull-up devices
Design Methodologie
Breathing Some New Life in PLAs

River PLAs

PRE-CHARGE
A cascade of multiple-output PLAs. Adjacent PLAs are connected via river routing.
BUFFER B U F F E R
- C
PRECHARGE
F F E
BUFFER
- C
PRE-CHARGE
F F E
BUFFER
- C
F F E
- C
No placement and routing needed. Output buffers and the input buffers of the next stage are shared.
PRECHARGE
BUFFER
Courtesy B. Brayton
Design Methodologie
Experimental Results
1.4
Area: RPLAs (2 layers) 1.23 SCs (3 layers) 1.00, NPLAs (4 layers) 1.31 Delay RPLAs 1.04 SCs 1.00 NPLAs 1.09 Synthesis time: for RPLA , synthesis time equals design time; SCs and NPLAs still need P&R.
0.6
Also: RPLAs are regular and predictable Layout of C2670
0.2 0 2
S C N P
delay
4
L A R P
6
L A
area
Standard cell, 2 layers channel routing
Standard cell, 3 layers OTC
Network of PLAs, 4 layers OTC
River PLA, 2 layers no additional routing
Design Methodologie
MacroModules
256 32 (or 8192 bit) SRAM Generated by hard-macro module generator
Design Methodologie
Soft MacroModules
Synopsys DesignCompiler
Design Methodologie
Intellectual Property
A Protocol Processor for Wireless
Design Methodologie
Semicustom Design Flow

Design Capture HDL HDL Logic Synthesis Logic Synthesis Structural Behavioral Pre-Layout Pre-Layout Simulation Simulation
Design Iteration
Post-Layout Post-Layout Simulation Simulation Circuit Extraction Circuit Extraction
Floorplanning Floorplanning Placement Placement Routing Routing Tape-out Physical
Design Methodologie
The Design Closure Problem
Iterative Removal of Timing Violations (white lines)
Courtesy Synopsys
Design Methodologie
with Physical Design

RTL (Timing) Constraints
Physical Synthesis Physical Synthesis

Macromodules Fixed netlists Netlist with Place-and-Route Info
Place-and-Route Place-and-Route Optimization Optimization

Artwork
Design Methodologie
Late-Binding Implementation
Array-based
Pre-diffused (Gate Arrays)
Pre-wired (FPGA's)
Design Methodologie
Gate Array Sea-ofgates

polysilicon VD D
rows of uncommitted cells
metal possible contact
GND
Uncommited Cell
In 1 In2
In3 In4
routing channel
Committed Cell (4-input NOR)

Out
Design Methodologie
Sea-of-gate Primitive Cells

O x id e - i s o l a t io n P M P M O S O S
S N M O S
Using oxide-isolation
Using gate-isolation
Design Methodologie
Example: Base Cell of GateIsolated GA

VDD continuous p-diff strip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
continuous n-diff strip
contact for isolator GND
n-well p-well n-diff p-diff poly m1 m2 contact
From Smith97
Design Methodologie
Example: Flip-Flop in GateIsolated GA

VDD
CLR Q
CLK Q D
GND
From Smith97
Design Methodologie
Sea-of-gates
Random Logic
Memory Subsystem LSI Logic LEA300K (0.6 m CMOS)
Courtesy LSI Logic
Design Methodologie
The return of gate arrays?
Via programmable gate array (VPGA)
Via-programmable cross-point
metal-5 programmable via
metal-6
Exploits regularity of interconnect

[Pileggi02]
Design Methodologie
Prewired Arrays
Classification of prewired arrays (or fieldprogrammable devices):
Based on Programming Technique

Fuse-based (program-once) Non-volatile EPROM based RAM based
Programmable Logic Style

Array-Based Look-up Table
Programmable Interconnect Style

Channel-routing Mesh networks
Design Methodologie
Fuse-Based FPGA
antifuse polysilicon ONO dielectric
n+ antifuse diffusion 2 l
Open by default, closed by applying current pulse
From Smith97
Design Methodologie
Array-Based Programmable Logic

I5 I4 I3 I2 I1 I0 Programmable OR array I3 I2 I1 I0 Programmable OR array I5 I4 I3 I2 I1 I0 Fixed OR array
Programmable AND array O 3O 2O 1O 0
Fixed AND array O3O2O1O0
Programmable AND array

O 3O 2O 1 O 0
PLA
PROM
Indicates programmable connection Indicates fixed connection
PAL
Design Methodologie
Programming a PROM
1 X2 X1 X0
: programmed node NA NA f 1 f 0
Design Methodologie
More Complex PAL

programmable AND array (2 jk) i3 product terms k macrocells 1
j -wide OR array D Q
OUT
j j
macrocell CLK A B C i i inputs
i inputs, j minterms/macrocell, k macrocells

From Smith97
Design Methodologie
2-input mux as programmable logic block

Configuration A 0 0 0 0 X Y Y 1 1 1 B 0 X Y Y 0 0 1 0 0 1 S 0 1 1 X Y X X X Y 1 F= 0 X Y XY XY XY X1 Y X Y 1
A B
0 F 1
Design Methodologie
Logic Cell of Actel FuseBased FPGA

A B SA C D SB S0 S1 1 1 1 Y
Design Methodologie
Look-up Table Based Logic Cell

Memory In Out 00 01 10 11 ln1 ln2 Out 00 1 1 0
Design Methodologie
LUT-Based Logic Cell must be Figure

C1....C4 4 xx D4 D3 D2 D1 xxxx xxxx xxxx Bits control x xx x xxxx xx
updated
Logic function of xxx Logic function x of xxx Logic function of xxx
xx xx xx xx
x x
xx xx x xx xx xx xx Bits control xxxx x xx x xx x
F4 F3 F2 F1
x xxxxx
xx xx H P x Multiplexer Controlled by Configuration Program x
Xilinx 4000 Series
Courtesy Xilinx
Design Methodologie
Array-Based Programmable Wiring

M
Interconnect Point
Programmed interconnection
Input/output pin
Cell
Horizontal
tracks
Vertical tracks
Design Methodologie
Network
Switch Box
Connect Box
Interconnect Point
Digital Integrated Circuits2ndCourtesy Dehon and Wawrzyniek Design Methodologie
Transistor Implementation of Mesh
Hierarchical Mesh Network
Use overlayed mesh to support longer connections Reduced fanout and reduced resistance
EPLD Block Diagram

Primary inputs
Macrocell
Courtesy Altera
Design Methodologie
Altera MAX
From Smith97
Design Methodologie
Altera MAX Interconnect Architecture

column channel t PIA row channel
LAB1
LAB2 LAB PIA
t PIA
LAB6
Array-based (MAX 3000-7000)
Mesh-based (MAX 9000)

Courtesy Altera
Design Methodologie
Field-Programmable Gate Arrays Fuse-based

I / O B u f f e r s P r o g r a m r o / T e s t / D u t e s ia g n o s t i c s V e r t i c a l
Standard-cell like floorplan

I/O B u ffe r s I/O B u ffe rs
s I / O B u f f e r s
o w s o f lo g i c m o d u le R o u t i n g c h a n n e l s
Design Methodologie
Xilinx 4000 Interconnect Architecture

12 8
Quad Single Double Long Direct
4 3 CLB 2
3
Connect
Long
12
Quad
4
Long
4
Global
8
Long
4
Carry
2
Direct
Double Single Global
Clock
Clock Chain Connect
Courtesy Xilinx
Design Methodologie
RAM-based FPGA
Xilinx XC4000ex Courtesy Xilinx
Design Methodologie
A Low-Energy FPGA (UC Berkeley)

Array Size: 8x8 (2 x 4 LUT) Power Supply: 1.5V & 0.8V Configuration: Mapped as RAM Toggle Frequency: 125MHz Area: 3mm x 3mm
Design Methodologie
Larger Granularity FPGAs

PADDI-2 (UC Berkeley)
1-mm 2-metal CMOS tech 1.2 x 1.2 mm2 600k transistors 208-pin PGA fclock = 50 MHz
P av
= 3.6 W @ 5V
Basic Module: Datapath
Design Methodologie
Design at a crossroad
System-on-a-Chip
500 k Gates FPGA MultiSpectral RAM + 1 Gbit DRAM Imager Preprocessing
64 SIMD Processor Array + SRAM Image Conditioning 100 GOPS
C system +2 Gbit DRAM

Recognition
Analog
Embedded applications where cost, performance, and energy are the real issues! DSP and control intensive Mixed-mode Combines programmable and application-specific modules Software plays crucial role
Design Methodologie
Addressing the Design Complexity Issue Architecture Reuse Reuse comes in generations
Generation 1st 2nd 3rd 4th Reuse element Standard cells IP blocks Architecture IC Status Well established Being introduced Emerging Early research
Source: Theo Claasen (Philips) DAC 00
Design Methodologie
Architecture ReUse
Silicon System Platform

Flexible architecture for hardware and software Specific (programmable) components Network architecture Software modules Rules and guidelines for design of HW and SW
Has been successful in PCs

Dominance of a few players who specify and control architecture
Application-domain specific (difference in constraints)

Speed (compute power) Dissipation Costs Real / non-real time data
Design Methodologie
Platform-Based Design
Only the consumer gets freedom of choice; designers need freedom from choice A platform is a restriction on the space of possible implementation (Orfali, et abstraction p.522) choices, providing a well-definedal, 1996,of the underlying
technology for the application developer New platforms will be defined at the architecture-micro-architecture boundary They will be component-based, and will provide a range of choices from structured-custom to fully programmable implementations Key to such approaches is the representation of communication in the platform model
Source:R.Newton
Design Methodologie
Berkeley Pleiades Processor

0.25um 6-level metal CMOS
FPGA
5.2mm x 6.7mm 1.2 Million transistors
Reconfigurable Data-path
Interface
40 MHz at 1V 2 extra supplies: 0.4V, 1.5V 1.5~2 mW power dissipation
ARM8 Core
Design Methodologie
Heterogeneous Programmable Platforms

FPGA Fabric
Embedded memories
Embedded PowerPc
Hardwired multipliers
Xilinx Vertex-II Pro

High-speed I/O Courtesy Xilinx
Design Methodologie
Summary
Digital CMOS Design is kicking and healthy Some major challenges down the road caused by Deep Sub-micron
Super GHz design Power consumption!!!! Reliability making it work Some new circuit solutions are bound to emerge
Who can afford design in the years to come? Some major design methodology change in the making!
Design Methodologie

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Integrated Circuits

Digital Integrated Circuits2nd

The Design Productivity Challenge

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Impact of Implementation Choices

Flexibility (or application scope)

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Standard Cells Compiled Cells

Pre-diffused (Gate Arrays)

Digital Integrated Circuits2nd

The Custom Approach

Digital Integrated Circuits2nd

Transition to Automation and Regular Structures

Intel 4004 (71)

Digital Integrated Circuits2nd

Cell-based Design (or standard cells)

Functional module (RAM, multiplier, )

Routing channel requirements are reduced by presence of more interconnect layers

Digital Integrated Circuits2nd

Standard Cell Example

Digital Integrated Circuits2nd

Standard Cell The New Generation

Digital Integrated Circuits2nd

Standard Cell - Example

Digital Integrated Circuits2nd

Automatic Cell Generation

Initial transistor geometries

Digital Integrated Circuits2nd

A Historical Perspective: the PLA

Digital Integrated Circuits2nd

Inverting format (NORNOR) more effective

Digital Integrated Circuits2nd

PLA Layout Exploiting Regularity

Digital Integrated Circuits2nd

Breathing Some New Life in PLAs

Digital Integrated Circuits2nd

Also: RPLAs are regular and predictable Layout of C2670

Standard cell, 2 layers channel routing

Standard cell, 3 layers OTC

Network of PLAs, 4 layers OTC

River PLA, 2 layers no additional routing

Digital Integrated Circuits2nd

256 32 (or 8192 bit) SRAM Generated by hard-macro module generator

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

A Protocol Processor for Wireless

Digital Integrated Circuits2nd

Semicustom Design Flow

Post-Layout Post-Layout Simulation Simulation Circuit Extraction Circuit Extraction

Floorplanning Floorplanning Placement Placement Routing Routing Tape-out Physical

Digital Integrated Circuits2nd

The Design Closure Problem

Iterative Removal of Timing Violations (white lines)

Digital Integrated Circuits2nd

with Physical Design

Physical Synthesis Physical Synthesis

Place-and-Route Place-and-Route Optimization Optimization

Digital Integrated Circuits2nd

Pre-diffused (Gate Arrays)

Digital Integrated Circuits2nd