ECE 681 VLSI Design Automation

Khurram Kazi Thanks to Automation press THE button outcomes the Chip !!! Reality or Myth
(most of the material in this lecture is taken from Bhatnagers book) Kazi ECE 6811

set_operating_conditions on the whole design

Describing environmental attributes

Top Level
Clock Divider Logic

set_max_capacitance Set_max_transition & set_max_fanout on Inputs and Output ports or current design

clk set_drive on Clock

Fram ing State Machine Block BIP calc

set_load on outputs

set_driving_cell on input signals

set_wire_load for each block, including top leve

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Environmental attributes
Design environment consists of defining the process parameters, I/O port attributes, and statistical wire load models.
Set_min_library <max_library filename> -min_version <min library filename> dc_shell> set_min_library ex25_worst.db \ -min_version ex25_best.db This command allows the users to simultaneously specify the best case and worst case libraries. Can be used to fix set up and hold violation. The user should set both the min and the max values for the operating conditions

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Setting operating conditions

set_operating_conditions
Specifies the process, voltage and temperature conditions of the design. Synopsys library consists of WORST, TYPICAL and BEST cases. Each vendor has their own naming convention for the libraries! Changing the value of the operating condition command, full range of process variations are covered.
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Setting operating conditions

set_operating_conditions
WORST is generally used during pre-layout synthesis phase to optimize the maximum setup time. BEST is normally used to fix any hold violations. TYPICAL is generally not used since it is covered when both WORST and BEST cases are used.

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Setting operating conditions

set_operating_conditions
It is possible to optimize the design with both WORST and BEST cases simultaneously dc_shell> set_operating_conditions WORST dc_shell> set_operating_conditions min BEST -max WORST

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Operating conditions
worst typical Delay best worst Delay typical best worst best Delay typical

Process

temperature

Voltage

min

typical

max

% yield

PVT (Process, Voltage and Temperature curve)

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Modeling wire loads

DC uses wire loads models to estimate capacitance, resistance and the area of the nets prior to floor planning or layout. The wire load model is based upon a statistically average length of a net for a given fan out for a given area
20 x 20 10 x 10

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Wire load command

DC uses wire load information to model the delay which is a function of loading Synopsys provides wire load models in the technology library, each representing a particular size. Designer can create their own wire load models for better accuracy
set_wire_load_model name <wire-load model> dc_shell -t>set_wire_load_model name MEDIUM
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Wire load mode

There are 3 modes associated with the set_wire_load_mode: top, enclosed and segmented top Defines that all nets in the hierarchy will inherit the same wire load model as the top level block. Use it if when the plan is to flatten the design later for layout. enclosed Specifies all the nets (of the sub-blocks) inherit the wire load model of the block that completely encloses the sub-blocks. For example, if blocks X and Y are enclosed within block Z, then the blocks X and Y will inherit the wire load models defined for block Z.

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Wire load mode

segmented Used when wires are crossing hierarchical boundaries. From the previous example, the sub-blocks X and Y will inherit the wire load models specific to them, while nets between sub-blocks X and Y(which are contained within Z) will inherit wire-load model specified for block Z Not used often, as the wire load models are specific to the net segments set_wire_load_mode <top|enclosed|segmented> dc_shell>set_wire_load_mode top Accurately using wire load models is highly recommended as this directly affects the synthesis runs. Wrong model can generate undesired results. Use slightly pessimistic wire load models. This will provide extra time margin that may be absorbed later in the test circuit insertion or layout
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Wire load models across hierarchy

mode = top: (ignores lower level wire loads) 50x50 40x40 20x20 30x30

mode = enclosed: (uses best fitting wire loads) 50x50 40x40 20x20 30x30

50x50

mode = segmented: (uses several wire loads) 50x50 40x40 20x20 30x30

40x40

20x20

40x40

30x30 12

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set_drive
set_drive is used at the input ports of the block. It is used to specify the drive strength at the input port. Is typically used to model the external drive resistance to the ports of the block or chip. 0 signifies highest strength and is normally used for clock or reset ports. set_drive <value><object list> dc_shell> set_drive 0 {clk rst}
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set_driving_cell
set_driving_cell is used to model the drive resistance of the driving cell to the input ports. set_driving_cell cell <cell name> -pin <pin name> <object list> dc_shell>set_driving_cell cell BUFF1 pin Z [all_inputs]

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set_load
set_load sets the capacitive load in the units defined in the technology library (pf), to the specified ports or nets of the design. It typically sets capacitive loading on output ports of the blocks during pre-layout synthesis, and on nets, for back annotating the extracted post layout capacitive information set load <value> <object list> dc_shell>set_load 1.5 [all_outputs] dc_shell> set_load 0.3 [get_nets blockA/n1234]
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Design rule constraints

Design rule constraints consist of set_max_transition, set_max_fanout and set_max_capacitance. These rules are technology dependent and are generally set in the technology library. The DRC commands are applied to input ports, output ports or on the current_design. It can be useful if the technology library is not adequate of is too optimistic, then these commands can be used to control the buffering in the design set_max_transition <value> <object list> set_max_capacitance <value> object list> set_max_fanout ,value> <object list> dc_shell t>set_max_transition 0.3 current_design dc_shell t>set_max_capacitance 1.5 [get_ports out1] dc_shell t>set_max_fanout 3.0 [all_outputs] (dc_shell t> corresponds to DC operating in tcl mode)

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Some more design constraints

dc_shell t >create_clock period 40 -waveform [list 0 20] CLK set_dont_touch_network is a very useful command and is usually used for clock and reset. It is used to set_dont_touch property on a port, or a net. This prevents DC from buffering the net in order to meet DRCs. dc_shell t>set_dont_touch_network {clk, rst}
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Some more design constraints

If a block generates a secondary clock from the primary, e.g. byte clock from the serial clock, in this apply set_dont_touch_network on the generated clock output port of the block. Helps prevent DC from buffering it up. Clock trees can later be inserted to balance the clock skew.
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Some more design constraints

set_dont_touch is used to set a dont_touch property on the current design, cells, references or net. This is frequently used during hierarchical compilations of the block. dc_shell t>set_dont_touch current_design Useful in telling DC not to touch the current design if it has been optimized to designers satisfaction. For example, if some spare gates block is instantiated, DC will not touch it or optimize it.
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Some more design constraints

set_dont_use command is normally set in .synopsys_dc.setup environment file. This command tells DC not to use certain types of cells during synthesis process. For example, one can specify not to use scan flip flops (they normally have built in Muxes) set_dont_use [list mylib/SDFF* mylib/RSFF]
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A simple schematic

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Schematic converted into a timing graph

Each arrow represents a net or a cell delay (timing arc)

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Calculating a paths delay

1.0 0.34 0.5 0.25 0.12

Path delay = 1.0 + 0.5 + 0.34 + 0.25 + 0.12 = 2.21

Path delay = 0.75 + 0.45 + 0.56 +0.1 + 0.2 +0.1 = 2.16 0.75 0.45 0.56

0.1

0.2 0.1

0.0

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BIP Calculator
Example: A B O 0 0 0 1 0 1 1 1 0 1 0
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B A

1 1 1 0 1 1 0 1 0 1 1 0 1 1 1 0

F6 28 1111 0110 0010 1000 -> 1101 1110 = BIP1

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PRBS detector
set datain

clk

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Assignment 1 must haves in the report (Due on Oct 9)

Should have more than 1 block of code (multiple VHDL files) Show how you tested the sub blocks Show how you tested the top level block (framer ASIC) Should have a test plan (description of different test cases, verifying different conditions
Should show different frame states Should show at least one BIP error condition and your circuit detected it

Code must have comments and has to be readable Should have run synthesis on it and run at least one gate level simulation (assuming we have some gate level library) The report should be a comprehensive report, telling the reader what is the functionality of the ASIC, what are its features etc Describe your test environment, i.e. pattern generator, pattern detector (signal analyzer) or self checking mechanism of all the outputs from the ASIC. (waveform analysis is not good enough)

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Suggested ideas for the project

IP Packet classification and forwarding Ethernet 10 or 100 mbps MAC or repeater Elaborate SONET framer Ethernet VLAN tagging function Some protocol mapping function (segmenting IP packets in ATM cells) Cryptography Image/video processing Bottom Line: have a system prospective in mind before delving into the functional description. FIRST cut of your project ideas are due on October 2. Should have a brief overview of what you are trying to achieve
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