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Microcontrollers
Embedded Systems
Operations managed behind the scenes by a microcontroller An integrated electronic computing device that includes three major components on a single chip
Microprocessor (MPU) Memory I/O (Input/Output) ports
Microcontroller (MCU)
Microcontrollers
Support Devices
All components connected by common communication lines called the system bus.
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Block Diagram
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Microprocessor (MPU)
A group of electronic circuits fabricated on a semiconductor chip that can read binary instructions written in memory and process binary data according to those instructions CPU and MPU
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Memory
A semiconductor storage device consisting of registers that store binary bits Two major categories
D7
D0
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Input/Output (I/O)
Input devices such as switches and keyboards provide binary information to the microprocessor Output devices such as LEDs, video screens, and printers receive information from the microprocessor
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Microprocessor-Based Systems
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Microprocessor Architecture
The MPU communicates with memory and I/O using the system bus consisting of:
Address bus: unidirectional and carries memory and I/O addresses Data bus: bidirectional; transfers binary data and instructions between MPU and memory and I/O Control lines: Read and Write timing signals asserted by MPU
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Signed Integers: Seven bits (Bit6 to Bit0) represent the magnitude of a number.
The eighth bit (Bit7) represents the sign of a number. The number is positive when Bit7 is zero and negative when Bit7 is one. Positive numbers: 00 to 7F (0 to 127) Negative numbers: 80 to FF (-1 to -128) All negative numbers are represented in 2s complement
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8 bits of a number divided into groups of four, and each group represents a decimal digit from 0 to 9 Four-bit combinations from A through F in Hex are invalid in BCD numbers
Example: 0010 0101 represents the binary coding of the decimal number 25 which is different in value from 25H.
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Microprocessor unit (MPU) Program memory for instructions Data memory for data I/O ports Support devices such as timers
Microprocessor Unit
Arithmetic Logic Unit (ALU)
WREG working register (8-bit accumulator) Status register that stores flags (5-bits)
Instruction decoder (16-bit instructions)
Registers
BSR (4-bit register used in direct addressing the data memory) FSR (12-bit registers used as memory pointers in indirect addressing data memory) Program Counter (PC) (21-bit register that holds the program memory address while executing programs)
PIC18F - Buses
Address bus
21-bit address bus for program memory addressing capacity: 2 MB of memory 12-bit address bus for data memory addressing capacity: 4 KB of memory
16-bit instruction/data bus for program memory 8-bit data bus for data memory
Data bus
Control signals
PIC18F452/4520 Memory
Program Memory: 32 K Address range: 000000 to 007FFFH Data Memory: 4 K Address range: 000 to FFFH
Assembly code:
1 Problem statement:
Illustration
Execution of the instruction: MOVWF PORTC
Addressing Modes
Method of specifying of an operand
The operand is a number that follows the opcode MOVLW 0X10 The address of the operand is a part of the instruction MOVWF 0X20 An address is specified in a register (pointer) and the MPU looks up the address in that register
Direct addressing
Indirect addressing
Instruction Format
The PIC18F instruction format divided into four groups
Label
0xF2 Tab
2. Arithmetic Instructions.:
ADDLW K ADDWF f, d SUBLW k SUBWF f,d INCF F DECF F CLRF F SETF F ;Add KH to W ;Add W and f W +f -> d ;Subtract W from constant ;Subtract W from f
ADD instruction
LIST P=18F4520 ;directive to define processor #include <P18F4520.INC>;processor specific variable definitions REG0 EQU 0X20 REG1 EQU 0X30 REG2 EQU 0X40 ORG 00 GOTO MAIN MAIN MOVLW 0x0F MOVWF REG0 MOVLW 0x20 MOVWF REG1 ADDWF REG0,W MOVWF REG2 SLEEP
3. Logic Instruction.:
ANDLW k ;Logical AND with W with K IORLW k ; Logical OR with W with constant XORLW k ; Logical exclusive OR with W with f ANDWF f, d ; Logical AND with W with f IORWF f, d ; Logical OR with W with f XORWF f, d ; Logical exclusive OR with W with
constant
BTFSC file reg, bit ; bit test file reg. skip next instruction
6. Other instructions.:
NOP ; No operation CLRWDT ; Clear watchdog timer SLEEP ; Go into sleep mode
Problem on port:
2. Loop statements.:
INCFSZ f, d
Increment the contents of register f. Store the result in W (if d = 0) or in register f (if d =1). If the incremented value of f = 0, skip the next line of code.
DECFSZ f, d
Decrement the contents of register f. Store the result in W (if d = 0) or in register f (if d =1). If the decremented value of f = 0, skip the next line of code.
BTFSC f, b
Test bit b of register f. If bit b of register f is clear (that is, it equals zero), skip the next line of code.
BTFSS f, b
Test bit b of register f. If bit b of register f is set (that is, it equals one), skip the next line of cod
Loop Example
COUNT1 EQU 0x01 ORG 00 GOTO START ORG MOVLW MOVWF DECFSZ GOTO SLEEP END ;Counter is REG01
START: LOOP1:
0x20 0x05 ;Initialize Counter to 5 COUNT1 COUNT1;Decrement Counter, Skip if 0 LOOP1 ;Done
Nested Loop.:
P18F4520
Timers
Timer0.:
Software selectable operation as a timer or counter in both 8-bit or 16-bit modes Readable and writable registers Dedicated 8-bit, software programmable prescaler Selectable clock source (internal or external) Edge select for external clock Interrupt-on-overflow
Prescaler.:
By default the timer is incremented by one in every instruction cycle. Say that we are using the crystal of 4MHz i.e. timer will increment at instruction cycle rate of 1MHz. So TMR0 will increment in every 1us. So maximum we can make a delay of 255us. To increase this period we use prescaler. Let PS<2:0>=111 Now TMR0 will increase in 256 instruction cycle. i.e. We can produce the delay of 255 * 255us= 65.28ms
Period.:
Equation to calculate TMR0L value for period.: Period = (256 - TMR0)*(4/fosc)*(Prescaler) For example if Period = 1 ms and fosc = 4 MHz and using Prescaler 1:4 1ms = (256 - TMR0)(1us)(1) TMR0 = 6 = 0x06
Timer1.:
Software selectable operation as a 16-bit timer or counter Readable and writable 8-bit registers (TMR1H and TMR1L) Selectable clock source (internal or external) Interrupt-on-overflow Reset on CCP Special Event Trigger Device clock status flag (T1RUN)
Timer2.:
8-bit timer and period registers (TMR2 and PR2, respectively) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4 and 1:16) Software programmable postscaler (1:1 through 1:16) Interrupt on TMR2-to-PR2 match Optional use as the shift clock for the MSSP or PWM module
Timer2 Operation.:
In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4). The value of TMR2 is compared to that of the period register, PR2 on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/ postscaler.
T2CON.:
Timer3.:
Software selectable operation as a 16-bit timer or counter Readable and writable 8-bit registers (TMR3H and TMR3L) Selectable clock source (internal or external) Interrupt-on-overflow Module Reset on CCP Special Event Trigger
Timer3.:
P18F4520
INTERRUPTS
Interrupts.:
Interrupts are situations that the CPU can't predict when they will happen, they can happen any time, so the CPU does not wait for them. So the CPU keeps on doing its normal job unless and interrupt occurs. External interrupts TIMER interrupts Analog to Digital Converter Interrupts Data Interrupts
Interrupts.:
The PIC18F devices have multiple interrupt sources.:
High priority - Vector at 0008h Low priority - Vector at 0018h
High priority interrupt events will interrupt any low priority interrupts that may be in progress.
Timer0 interrupt
Timer0 interrupt
ADC.:
But most of our computer (or Microcontrollers) are digital in nature. They can only differentiate between HIGH or LOW level on input pins. For example: If input is more than 2.5v it will be read as 1 and if it is below 2.5 then it will be read as 0 . So we cannot measure voltage directly from MCUs. To solve this problem most modern MCUs have an ADC unit. In PIC18F4520 there are 13 analog input channels, they are named AN0, AN1 etc.
Specifications of ADCs.:
Most important specification of ADCs is the resolution. This specifies how accurately the ADC measures the analog input signals. Common ADCs are 8 bit, 10 bit and 12 bit. For example: If the reference voltage of ADC is 0 to 5v then 1. A 8-bit ADC will break it in 256 divisions so it can measure it accurately up to 5/256 v= 19mV approx. 2. While the 10-bit ADC will break the range in 5/1024 = 4.8mV approx. So you can see that the 8-bit ADC can't tell the difference between 1mV and 18mV. The ADC in PIC18 are 10-bit.
Reference Voltage.:
The reference voltage specifies the minimum and maximum voltage range of analog input. In PIC 18 there are two reference voltage, one is the Vref- and one is Vref+. The Vref+ and Vref- pins are available in PIN5 and PIN4 of the PIC18F4520 chip.
Acquisition Time.:
When an specific channel is selected the voltage from that input channel is stored in an internal holding capacitor. It takes some time for the capacitor to get fully charged and become equal to the applied voltage. This time is called acquisition time. A safe value is 2.45uS, so acquisition time must be set to any value more than this.
PIC18 ADC.:
The Analog-to-Digital (A/D) converter module has 10 inputs for the 28-pin devices and 13 for the 40/44-pin devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. The module has five registers: 1. A/D Result High Register (ADRESH) 2. A/D Result Low Register (ADRESL) 3. A/D Control Register 0 (ADCON0) 4. A/D Control Register 1 (ADCON1) 5. A/D Control Register 2 (ADCON2)
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Serial
Communication
Serial Communication.:
What a level converter:
RS232 level signals (HIGH=-12V LOW=+12V) from PC TTL level signal (HIGH=+5V LOW=0V) to be fed to MCU
Synchronization.:
Baud Rate.:
As there is no "clock" line so for synchronization accurate timing is required so transmissions are carried out with certain standard speeds. The speeds are measured in bits per second. The speed is also known as baud rate. Some standard baud rates are 1200 19200 2400 38400 4800 57600 9600 115200 ... etc
Transmitting device.:
For example we chose the speed as 9600bps(bits per second). As we are sending 9600 bits per second one bits takes 1/9600 seconds or 0.000104 sec or 104 uS
Receiving device.:
The pins of the Enhanced USART are multiplexed with PORTC. In order to configure RC6/TX/CK and RC7/RX/DT as a USART: bit SPEN (RCSTA<7>) must be set (= 1) bit TRISC<7> must be set (= 1) bit TRISC<6> must be set (= 1)
Registers.:
Transmit Status and Control (TXSTA) Receive Status and Control (RCSTA) Baud Rate Control (BAUDCON)
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CAPTURE/COMPARE/PWM (CCP) MODULES.: A capture, compare, and PWM, module, or CCP for short, is designed into the PicMicro to assist with measurement or control of time based pulse signals, module contains: a 16-bit register which can operate as a Capture register a 16-bit Compare register a 10-bit PWM Master/Slave Duty Cycle register.
Capture Mode.:
In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding CCPx pin. An event is defined as one of the following: every falling edge every rising edge every 4th rising edge every 16th rising edge The event is selected by the mode select bits, CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture is made, the interrupt request flag bit, CCPxIF, is set; it must be cleared in software.
Compare Mode.:
In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin can be: driven high driven low toggled (high-to-low or low-to-high) remain unchanged (that is, reflects the state of the I/O latch) The action on the pin is based on the value of the mode select bits (CCPxM3:CCPxM0). At the same time, the interrupt flag bit, CCPxIF, is set.
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PWM Mode.:
In Pulse Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP2 pin is multiplexed with a PORTB or PORTC data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output.
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