Arithmetic Circuit

ECR 205 Summer 2012 Lecture-7 SECS,IUB

Arithmetic Circuits
Circuits that preform arithmetic operations which are important part of digital design These circuits form the basis for a microprocessor's ALU and commonly used in many other applications Typically operate on binary input vectors, and output a resulting vector

Iterative Combinational Circuits

Arithmetic circuits often use the same subfunction in each bit of position Can design functional block for the subfunction and duplicate it to obtain functional block for an overall function Each subfunction block is referred to as a cell An array of interconnected cells forms an iterative array

Iterative Array Example

Example: n=32 means 64 inputs and 32 outputs 264 truth table rows-impractical!! Iterative array takes advantage of the regularity to make design feasible

Binary Adders
Binary addition is used frequently Similar to decimal addition but with two possible digits: 0 and 1 Example-8 bit addition 01001101 77 +01010110 +86 10100011 163

Half Adder
A half adder generates the sum of two binary digits: 0 0 1 1 x +0 +1 +0 +1 +Y 00 01 01 10 C.S

Half Adder Equation

The half adder can be specified as a truth table and the output equations derived
X Y C S

0
0 1 X X 0 0 1 0 1 1 1

0
1 0 0 1

0
0 0 0 1

0
1 1 1 0 Y 0 X 0 0 X 0 0 1 1

Y 0
Y 1

S X Y XY

C XY

Implementations: Half-Adder
The logic diagram of the half-adder

S X Y

C X Y

Full Adder
A full adder is similar to half adder, but includes a carry-in-bit, Z, from lower stages
Z X +Y CS Z X +Y CS 0 0 +0 00 1 0 +0 01 0 0 +1 01 1 0 +1 10 0 1 +0 01 1 1 +0 10 0 1 +1 10 1 1 +1 11

Full Adder Equation

The Full adder truth table and K-Maps:
S: Z XY 0 X 00 1 0 Y 01 0 1

11
1 0

10

0 1

Z 1

C:
Z

XY
0

X 11 1 1 0 1 10

00 0 1

01

X 0 0 0 0 1 1 1 1

Y 0 0 1 1 0 0 1 1

Z 0 1 0 1 0 1 0 1

C 0 0 0 1 0 1 1 1

S 0 1 1 0 1 0 0 1

0 0

Z 1

S X Y Z X Y Z X Y Z X Y Z C X Y X Z Y Z

Full Adder Equation

The full adder equations can be manipulated:
S X Y Z X Y Z X Y Z XYZ Z ( X Y X Y ) Z ( X Y XY ) Z(X Y) Z(X Y) (X Y) Z C XY XZ YZ XY Z ( X Y ) XY Z ( XY X Y ) XY Z ( X Y )

Full Adder Logic Diagram

X Y Z

S (X Y) Z C XY Z ( X Y )

Binary Ripple Carry Adder

An n-bit parallel adder formed by cascading n full adders Apply all n-bit inputs simultaneously Connect the carry output from one full adder to the carry input of the next The carry propagate through, from the LSB to the MSB

4-Bit Ripple-Carry Binary Adder

B3 A3 B2 A2 B1 A1 B0 A0 C3 C2 C1

FA

FA

FA

FA

C0

C4

S3

S2

S1

S0

Example: 00110 1011 Ai Bi + 0011 1110 Si C i 1 0011

Ci

Ripple-Carry Adders Delays

Ripple-carry adders have long circuit delays The carry has to propagate through many gates until the final result is obtained Each of the full-adders introduce to gatedelays in the carry path Example: for a 16-bit adders, the delay is 32 gate delays(+overhead)

Carry-Lookahead Adders
Define: Carry Generate
Gi Ai Bi
Ci Ai Bi Si C i 1

Must generate carry when A=B=1 Define: Carry Propagate

Pi Ai Bi

01000 0100 + 0100 1000 0100

The carry-out will equal carry-in

01100 Ai 0010 Bi + 0110 Si 1000 C i 1 0110

Ci

Carry-Lookahead Adders
Express the sum(S) and carry(C) in terms of generate/propagate:
S i ( Ai Bi ) C i Pi C i C i 1 Ai Bi C i ( Ai Bi ) Gi C i P

4-Bit Carry-Lookahead Adder

Re-express the carry equations:
Ci 1 Gi Ci P C1 G0 P0 C 0 C 2 G1 P1C1 G1 P1G0 P1 P0 C0 C3 G2 P2 C 2 G2 P2 G1 P1 P2 G0 P2 P1 P0 C 0 C 4 G3 P3C3 G3 P3G2 P3 P2 G1 P1 P2 P3G0 P3 P2 P1 P0 C0

4-Bit Carry-Lookahaead Adder

All carry bits can be calculated straight from the inputs In theory, 3-gate-delays regardless of numbers of bits, at the cost of more complex logic In practice, gates have limited number of inputs For larger adders, cascade 4-bit CLAs and connect to a group lookahead carry unit