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Prof.

David Money Harris


9 July 2010

Jackson Adders 2
Overview
Definitions
Tree Adders
Ling Adders
Jackson Adders
18-bit Jackson Tree
Evaluation Methodology
Preliminary Results

Jackson Adders 3
Addition
Carry Propagate Adder
Inputs: A
N:0
, B
N:1
A
0
= C
in
Outputs: S
N:1
Discard C
out
+
B
N...1
A
N...1
S
N...1
C
in
C
out
Jackson Adders 4
Propagate, Generate, Kill
Oh My!
Bitwise Signals
Generate: G
i:i
= G
i
A
i
B
i
Propagate: P
i:i
= P
i
A
i
+B
i
Also called ~K
i
X
i
A
i
xor B
i
Group Recursion to form prefixes
Propagate P
i:j
= P
i:k
P
k-1:j
Generate G
i:j
= G
i:k
+P
i:k
G
k-1:j
Group generates if upper part generates or upper part
propagates and the lower part generates
Bitwise Sum

S
i
= X
i
xor G
i-1:0

Jackson Adders 5
Higher Valency Groups
Valency-2
Propagate P
i:j
= P
i:k
P
k-1:j
Generate G
i:j
= G
i:k
+P
i:k
G
k-1:j
Valency-3
Propagate P
i:j
= P
i:k
P
k-1:l
P
l-1:j
Generate G
i:j
= G
i:k
+P
i:k
(G
k-1:j
+P
k-1:I
G
l-1:j
)

Valency-4
Propagate P
i:j
= P
i:k
P
k-1:l
P
l-1:m
P
m-1:j
Generate G
i:j
= G
i:k
+P
i:k
(G
k-1:j
+P
k-1:I
(G
l-1:m
+P
l-1:m
G
m-1:j
))


Jackson Adders 6
Tree Adders
How should the recursion be organized?
Jackson Adders 7
Black and Gray Cells
Black cell:
Group G and P
Gray cell:
Group G only
Inverting vs. non
Higher Valency
i:j
i:j
i:k k1:j
i:j
i:j
i:k k1:l l1:m m1:j
i:k k1:j
i:j
G
i:k
P
k1:j
G
k1:j
G
i:j
P
i:j
P
i:k
G
i:k
G
k1:j
G
i:j
G
i:j
P
i:j
G
i:j
P
i:j
(a)
G
i:k
G
k1:l
G
l1:m
G
m1:j
G
i:j
P
i:j
P
i:k
P
i:k
P
k1:l
P
l1:m
P
m1:j
G
i:k
P
k1:j
G
k1:j
G
i:j
P
i:j
P
i:k
G
i:k
G
k1:j
G
i:j
G
i:j
P
i:j
G
i:j
P
i:j
P
i:k
G
i:k
P
k1:j
G
k1:j
G
i:j
P
i:j
P
i:k
G
i:k
G
k1:j
G
i:j
G
i:j
P
i:j
G
i:j
P
i:j
P
i:k
(b)
Odd Rows
Even Rows
Black Cell Gray Cell Buffer
(c)
Jackson Adders 8
Tree Adders

(e) Knowles [2,1,1,1]
1:0 2:1 3:2 4:3 5:4 6:5 7:6 8:7 9:8 10:9 11:10 12:11 13:12 14:13 15:14
3:0 4:1 5:2 6:3 7:4 8:5 9:6 10:7 11:8 12:9 13:10 14:11 15:12
4:0 5:0 6:0 7:0 8:1 9:2 10:3 11:4 12:5 13:6 14:7 15:8
2:0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
1:0 3:2 5:4 7:6 9:8 11:10 13:12
3:0 7:4 11:8 15:12
5:0 7:0 13:8 15:8
15:14
15:8 13:0 11:0 9:0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
(f) Ladner-Fischer
1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14
3:0 5:2 7:4 9:6 11:8 13:10 15:12
5:0 7:0 9:2 11:4 13:6 15:8
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
(c) Han-Carlson (a) Brent-Kung
(b) Sklansky
1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14
3:0 7:4 11:8
15:12
7:0
15:8
11:0
5:0 9:0 13:0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
1:0
2:0 3:0
3:2 5:4 7:6 9:8 11:10 13:12 15:14
6:4 7:4 10:8 11:8 14:12 15:12
12:8 13:8 14:8 15:8
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
15:0
(d) Kogge-Stone
1:0 2:1 3:2 4:3 5:4 6:5 7:6 8:7 9:8 10:9 11:10 12:11 13:12 14:13 15:14
3:0 4:1 5:2 6:3 7:4 8:5 9:6 10:7 11:8 12:9 13:10 14:11 15:12
4:0 5:0 6:0 7:0 8:1 9:2 10:3 11:4 12:5 13:6 14:7 15:8
2:0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
Jackson Adders 9
Higher Valency Trees
Jackson Adders 10
Sparse Trees
Sklansky sparseness 4
Only compute prefixes for every 4
th
column
Precompute 4-bit results for each possible carry in
Select result based on carry (group generate)
2:1
4:1
4:3 6:5 8:7 10:9 12:11 14:13 16:15
8:5 12:9
16:13
16:9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
8:1
12:1 16:1
16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16
18:17
20:17
20:19 22:21 24:23
26:25
28:27
24:21 28:25
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
24:17
28:17
32 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
32
20:1 24:1 28:1 '0'
Jackson Adders 11
Carry Selection

i j ... (a)
+
+
A
i:j
B
i:j
S
i:j
0
1
G
j1:0
(b)
P
1
C
in
S
1
S
2
S
3
S
4
P
4
P
4
P
2
P
2
P
3
P
3
P
1
G
1
P
1
G
1
PG
2
PG
3
(c)
C
in
=
G
j1:0
1 0
1 0 1 0 1 0 1 0
Jackson Adders 12
Ling Adders
Factor some complexity out of first term
Insert it back into sum selection
Remove 1 transistor from critical path

Exploits fact that G
i
P
i
= (A
i
B
i
)(A
i
+B
i
) = G
i


Jackson Adders 13
Ling Equations
Define Pseudogenerate: H
i:j
G
i
+ G
i-1:j
Simpler than G
i:j
= G
i
+ P
i
G
i-1:j
Recreate G
i:j
= P
i
H
i:j
= P
i
(G
i
+ G
i-1:j
) = G
i
+ P
i
G
i-1:j
Define Pseudopropagate I
i:j
P
i-1:j-1
Shifted version of group propagate
Valency-2 recursion is same as PG
H
i:j
= H
i:k
+ I
i:k
H
k-1:j
I
i:j
= I
i:k
I
k-1:j
Sum: S
i
= X
i
xor G
i-1:0
= X
i
xor (P
i-1
H
i-1:0
)
Selection mux: S
i
= H
i-1:0
? [X
i
xor P
i-1
] : X
i

Sum selection
mux chooses S
i
based on late-
arriving H
i-1:j
Jackson Adders 14
Ling Circuits
Simplifies first stage
Compute H
i+1:I
in one swell foop
A
1
B
1
A
2
B
2
A
2
B
2
A
2
B
2
A
1
B
1
A
2
B
2
G
2:1
G
2:1
= G
2
+ P
2
G
1
= A
2
B
2
+ (A
2
+ B
2
)A
1
B
1
H
2:1
= G
2
+ G
1
= A
2
B
2
+ A
1
B
1
A
1
A
2
B
1
B
2
A
2
B
2
A
1
B
1
H
2:1
(a) (b)
Too hard
Easy
Jackson Adders 15
Jackson Adders
Generalized Ling technique
Simplify logic in the prefix tree as well
Use sum selection to reinsert missing terms
Balance logic so both data and select to sum mux are
comparable in criticality
Developed by Jackson and Talwar in 2004
Used in Arithmetica synthesis tool
Parameterized by architecture, valency, sparseness
Reportedly produced superior energy-delay tradeoffs
Burgess09 indicates benefits over standard designs
No comprehensible complete published designs
Jackson Adders 16
Jackson Logic
Define new terms
D: a group generates or propagates a carry

Special case:
B: a group generates a carry in at least one bit

Rewrite group generate:
Group generates if upper part generates or
propagates and either at least one bit of upper part
generates or the low part generates

: : : : 1 : i j i j i j i j i j
D G P G P
+
+ = +
:
j
i j k
k i
B g
=
=

: i i i
D p =
: : : 1: i j i k i k k j
G D B G

( = +

Jackson Adders 17
Reduced Generate
Again,
Rename bracketed term reduced generate R

R
p
has the top p propgate signals stripped out
R
0
i:j
= G
i:j
R
1
i:j
= H
i:j
Jackson consideres p 2
Group generate can be rewritten in terms of R

Computing R prefixes can be easier than G
: : : 1: i j i k i k k j
G D B G

( = +

: : 1 :
p
i j i i p i p j
R B G
+
= +
: : 1 :
p
i j i i p i j
G D R
+
=
Jackson Adders 18
Hyperpropagate
Another term will be useful for recursion: hyperpropagate
Define

Special case for 2-bit groups:
: : 1 :
p
i j i i p i p j
Q P D
+
=
1 2
1: 1: 1: i i i i i i
Q Q P
+ + +
= =
Jackson Adders 19
Jackson Recursions
Valency-2 is no simpler



Valency-3 simplifies R at expense of Q
( )
1
: : : 1:
1
: : : 1:
p p i p k q
i j i k i p k q k j
p p i p k q
i j i k i p k q k j
R R Q R
Q Q R Q
+

+

= +
= +
1 1
: : 1: 1: 1:
1 1
: : 1: 1: 1:
i p i k k p p l l m
i j i k k l p m l j
i p i k k p p l l m
i j i k k l p m l j
R R R Q R
Q Q Q R Q
+ +

+ +

= + +
( = +

total top top mid top mid bot
total top mid bot
G G P G P P G
P P P P
= + +
=
Compare with
total top top bot
total top bot
G G P G
P P P
= +
=
Compare with
Jackson Adders 20
Valency-3 Circuits
Compound gate implementation




Simpler gate implementation
R
total
R
top
R
mid
R
bot
Q
flex
R
top
R
mid
R
bot
Q
f.ex
Q
bot
Q
top
Q
mid
R
flex
Q
top
Q
mid
R
flex
Q
bot
Q
total
R
total
R
top
R
mid
R
bot
Q
flex
Q
total
Q
top
Q
mid
Q
bot
R
flex
Jackson Adders 21
Logical Effort of Valency-3
PG RQ
Compound
RQ
Simpler
G
generate
4 2.67 2.22
G
propagate
1.67 3.33 2.77
P
generate
5 4.33 4
P
propagate
4 4.66 4
Jackson Adders 22
Sum Selection
Select sum based on R
p
i-1:0




Requires p-bit D signal for sum-selection data input
This is the complexity that is factored out of R
D recursion


( )
1:0
1: 1:0
1:0 1:0 1:
i i i
p
i i i p i
p p
i i i i i i p
s x G
x D R
R x R x D



=
=
= +
1
: : 1 : :
p i k p
i j i i p i k i p j
D D R Q
+
+
(
= +

Jackson Adders 23
Prior Work
[Jackson04]
+ Introduced R and Q
+ Showed how to compute a single sum output
- Does not show how to build an entire adder
- Does not include recursions for D, valency-2 R/Q
[Burgess09]
+ Comments on critical path
+ Comparisons suggest benefits of Jackson adder
- Hard to decipher diagram of 24-bit adder
Jackson Adders 24
Example
18-bit Jackson Adder
Sklansky tree with sparseness 2
Valency-2 initial stage (like Ling)
Valency-3 2
nd
and 3
rd
stages
Only 4 levels of noninverting logic
Jackson Adders 25
Initial Stage
Reduced Generate



Hyperpropagate


Also will need g
i
for even bits, p
i
for odd bits, x
i
for all bits
For sum selection logic
1
2 1:2 2 1 2 2 1 2 1 2 2
1
1:0 0 1 1
i i i i i i i i
R g g a b a b
R a a b
+ + + +
= + = +
= +
( )( )
1
2 1:2 2 1 2 2 1 2 1 2 2 i i i i i i i i
Q p p a b a b
+ + + +
= = + +
Jackson Adders 26
Second Stage
Compute 3 and 6-bit group signals
Note potential for sharing common terms
3 1 1 1 1
17:12 17:16 15:14 14:13 13:12
1 1 1 1
15:12 15:14 14:13 13:12
3 1 1 1 1
11:6 11:10 9:8 8:7 7:6
1 1 1 1
9:6 9:8 8:7 7:6
3 1 1 1 1
5:0 5:4 3:2 2:1 1:0
1 1 1 1
3:0 3:2 2:1 1:0
R R R Q R
R R Q R
R R R Q R
R R Q R
R R R Q R
R R Q R
= + +
= +
= + +
= +
= + +
= +
3 2 1 1 1
14:9 14:13 12:11 11:10 10:9
1 1 1 1
12:9 12:11 11:10 10:9
3 2 1 1 1
8:3 8:7 6:5 5:4 4:3
1 1 1 1
6:3 6:5 5:4 4:3
Q Q Q R Q
Q Q R Q
Q Q Q R Q
Q Q R Q
( = +

( = +

( = +

( = +

Jackson Adders 27
Third Stage
Reduced generate signals for all groups
9 3 3 3 3
17:0 17:12 11:6 8:3 5:0
7 1 3 3 3
15:0 15:12 11:6 8:3 5:0
5 1 3 3 3
13:0 13:12 11:6 8:3 5:0
3 3 3 3
11:0 11:6 8:3 5:0
1 1 3 3
9:0 9:6 8:3 5:0
1 1 1 3
7:0 7:6 6:3 5:0
R R R Q R
R R R Q R
R R R Q R
R R Q R
R R Q R
R R Q R
= + +
= + +
= + +
= +
= +
= +
Jackson Adders 28
D Logic
Medium-length groups of D are required for sum selection







Note that D
17:9
depends on R
3
17:12
Hence, arrives at same time as R
9
17:0
( )
3 3 1 1 3 3
17:9 17:15 17:12 14:9 17:17 17:16 16:15 17:12 14:9
1 3
15:9 15:15 15:12 14:9
1 1
13:9 13:13 13:12 12:9
1 1
11:9 11:11 11:10 10:9
9:9 9
7:7 7
1
5:3 5:4 5:3 5 5:4
D D R Q D R Q R Q
D D R Q
D D R Q
D D R Q
D p
D p
D G P p R
( ( ( = + = + +

( = +

( = +

( = +

=
=
= + =
( )
1 1 1
4:3 5:5 5:4 4:3
3:3 3
1:1 1
Q D R Q
D p
D p
( + = +

=
=
Jackson Adders 29
Sum Selection
Sparseness of 2 requires 1-bit ripple from even to odd
( )
( )
( ) ( )
2 2 2 1:0 2 2 1:2 2 1:0
2 1:0 2 2 1:2 2
? :
p
i i i i i i p i
p
i i i i p i
s x G x D R
R x D x


= =
=
( )
( )
( )
( )
( )
2 1 2 1 2 2 2 1:0 2 1 2 2 2 1:2 2 1:0
2 1:0 2 1 2 2 2 1:2 2 1 2
? :
p
i i i i i i i i i i p i
p
i i i i i i p i i
s x g x G x g x D R
R x g x D x g
+ + +
+ +
= + = +
= +
Jackson Adders 30
Prefix Network
0 ***
a1, b1 a2, b2
1
a3, b3 a4, b4
2
a5, b5 a6, b6
3
a7, b7 a8, b8
4
a9, b9 a10, b10
5
a11, b11 a12, b12
6
a13, b13 a14, b14
7
a15, b15 a16, b16
8 ***
a17, b17 a18, b18 a0
A2i
B2i
A2i+1
B2i+1
Buffer
noncritical
logic
x2i+2
x2i+1
g2i+2
p2i+1
A2i+2
B2i+2
Q
1
2i+2:2i+1
R
1
2i+1:2i
R
1
1:0, Q
1
2:1 R
1
3:2, Q
1
4:3 R
1
5:4, Q
1
6:5 R
1
7:6, Q
1
8:7 R
1
9:8, Q
1
10:9 R
1
11:10, Q
1
12:11 R
1
13:12, Q
1
14:13 R
1
15:14, Q
1
16:15 R
1
17:16
0 1 2
R
1
3:0 R
3
5:0 R
1
9:6 R
3
11:6 R
1
15:12 R
3
17:12 Q
1
6:3 Q
3
8:3 Q
1
12:9 Q
3
14:9
i
A2i+2
B2i+2
A2i+1
B2i+1
A2i
B2i
j
R
1
6j+1:6j
Q
1
6j+2:6j+1
R
1
6j+3:6j+2
Q
1
6j+4:6j+3
R
1
6j+5:6j+4
Q
1
6j+6:6j+5
Q
1
6j+8:6j+7
R
1
6j+3:6j R
3
6j+5:6j Q
1
6j+6:6j+3 Q
3
6j+8:6j+3
R
1
6j+3:6j
R
3
6j+5:6j
R
1
6j+1:6j
Q
1
6j+2:6j+1
R
1
6j+3:6j+2
R
1
6j+5:6j+4
Q
1
6j+6:6j+3
Q
3
6j+8:6j+3
Q
1
6j+4:6j+3
R
1
6j+5:6j+4
Q
1
6j+6:6j+5
Q
1
6j+8:6j+7
Notes:
Black cells compute R and Q.
Gray cells compute only R
D network not shown
R
1
7:0 R
1
9:0 R
3
11:0 R
5
13:0 R
7
15:0 R
9
17:0
8
s18
7
s16 s17
6
s14 s15
5
s12 s13
4
s10 s11
3
s8 s9
2
s6 s7
1
s4 s5 s2 s3
s2k s2k+1
R
p
2k-1:0
R
p
2k-1:0
s2k
s2k+1
0
1
0
1
x2k
s1
D2k-1:2k-p
X2k+1
g2k
Jackson Adders 31
Observations
Only 4 levels of noninverting logic
D
17:9
is critical
Too much factored out of R
9
17:0
Could eliminate need by doing a 2-bit ripple into s
18

| |
( ) | |
18 18 17:0
18 17 17 16 17 16 15:0
7
18 17 17 16 17 16 15:9 15:9
7
15:9 15:9 18 17 17 16 16 18 17 17 16
? :
s x G
x g p g p p G
x g p g p p D R
D R x g x g p x x x g
=
= + +
( = + +

= + + + (

Jackson Adders 32
Comparison Methodology
Goal: energy-delay curves for Jackson adders compared
to conventional adders
How can we objectively compare against the best
conventional design?
Technology mapping challenges
Sizing
Gatesizer limitations
SCOT is better, but we only have 130 nm models
Inadequate design effort on conventional cases
Plan: synthesize with Design Compiler
Compare against assign y = a + b;
Jackson Adders 33
Preliminary Results
130 nm Artisan library for
IBM CMOS8sf
1.2 V
FO4 Delay: 55 ps
Fastest designs are 570
ps (10 FO4)
Jackson takes more
energy except at very
long delay
s
18
optimization helps at
fastest delays




Energy-Delay Tradeoffs
0
200
400
600
800
1000
1200
1400
1600
1800
0 0.5 1 1.5 2
Delay (ns)
E
n
e
r
g
y

(
f
J
)
Jackson
Behavioral
JacksonOptS18
Jackson Adders 34
Optimization Ideas
Compare against Design Compiler architectures
Starts with NAND/NOR to compute ~g
i
, ~p
i
Computes x
i
= p
i
* ~g
i
to avoid costly XORs
Appears to use valency-2 Sklansky tree with inverting gates
Final XOR
Logical effort analysis of critical path
Look for areas to reduce effort
Architecture
Valency: consider direct bitwise PG, followed by valency-3 Jackson tree
Sparseness (sparseness 3 in tree above?, sparseness 1)
Sklansky vs. Kogge-Stone
Verilog coding
Does sharing of terms explicitly help or hurt?
Code tuning experiments
Jackson Adders 35
Sun Feedback
Issues raised at Sun review on 9 July 2010
Should we use SCOT to evaluate the effects of
continuous sizing?
Follow SCOT up with SPICE
Start without wire loads, add later
Wire load modeling in Design Compiler
Jackson Adders 36
Short-Term Action Items
Adder modeling (write eqns, code in Verilog, compare to DC)
32-bit Sklansky valency-2 baseline similar to DC
NAND/NOR to form Pbar, Gbar
G * Pbar to form X
Inverting stages of group logic
Final XOR
Does it exactly match DC results?
27-bit Jackson (1-bit, followed by 3 radix-3 stages)
54-bit Jackson (2-bit Ling PG, followed by 3 radix-3 stages)
Explore optimization of 18-bit design
Logical effort analysis of critical path through 18-bit Jackson
Tool to automatically generate energy-delay curves with DC
Tool flow for DC 2010 with placement and expected wire cap
Subversion repository setup
Selection of cell library

Jackson Adders 37
Cell Library
IBM 45 nm partially-depleted SOI 12S ARM Library
sc12_base_v31_rvt_soi12s0_ss_nominal_max_0p90v_125c_mxs.lib
A12TR library with regular V
t
(RVT) transistors
12 track cell height (1.68 m)
Typical operating point: 1.0 V, 25 C
We use worst-case slow-slow, 0.9 V, 125 C library
Use Maxsol (mxs) version for worst-case history effect
1X inverter INV_X1B_A12TR:
Width = 0.38 m
C
in
= 1.6 fF
Intrinsic delay: 16.6 ps rise / 14.1 fall / 15.3 average
Kload: 1.46 ps/pF rise / 1.17 fall / 1.3 average
FO4 delay = 15.3 ps + 1.3 * 1.6 * 4 24 ps
But .lib for 21 ps slew rate, 7.9 fF load suggests
t
pdf
= 17 ps, t
pdr
= 23 ps, t
pd
= 20 ps, t
f
= 13 ps, t
r
= 23 ps
Switching energy: 0.00078 W/MHz 0.8 fJ
equals 0.5 C
in
V
DD
2

Leakage power: 0.1 W (very high!)
Jackson Adders 38
Summary
Jackson adders appear to offer potential benefits
Logical effort
Arithmetica results
Burgess results
Preliminary synthesis results dont yet demonstrate the
advantages
HMC 2010-11 Clay-Wolkin Research goals
Understand Jackson design space
Logical effort analysis of critical path
Develop Jackson adders superior to conventional
Design Compiler results
Jackson Adders 39
References
[Burgess09] N. Burgess, Implementation of recursive Ling adders in CMOS
VLSI, Proc. Asilomar Conf. Signals, Systems and Computers, 2009, pp.
1777-1781.
[Jackson04] R. Jackson and S. Talwar, High speed binary addition, Proc.
Asilomar Conf. Signals, Systems and Computers, 2004, pp. 1350-1353.
[Jackson08] R. Jackson, Data detection algorithms for perpendicular
magnetic recording in the presence of strong media noise, Ph.D. thesis,
Department of Mathematics, University of Warwick, 2008.
[Ling81] H. Ling, "High-speed binary adder," IBM J. Research and
Development, vol. 25, no. 3, May 1981, pp. 156-166.
[Patil07] D. Patil, O. Azizi, M. Horowitz, R. Ho, and R. Ananthraman,
"Robust energy-efficient adder topologies," Proc. Computer Arithmetic
Symp., Jun. 2007, pp. 16-28.
[Weste10] N. Weste and D. Money Harris, CMOS VLSI Design, 4th Ed.,
Boston: Addison-Wesley, 2010.
[Zlatanovici09] R. Zlatanovici, S. Kao, and B. Nikolic, Energy-delay
optimization of 64-bit carry-lookahead adders with a 240 ps 90 nm CMOS
design example, IEEE J. Solid-State Circuits, vol. 44, no. 2, Feb. 2009, pp.
569-583.