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Agenda

Brief tour in RTL synthesis Basic concepts and representations LUT-based technology mapping The chortle algorithm The FlowMap approach

RTL Representation

A structured system: Made upon a set of combinational parts separated by memory elements RTL

Computation:

Performed in the combinational parts

Results

Might be temporarily stored in registers (placed between the combinational blocks)

Clock:

Synchronizes the transfer of data from register to register via combinational parts

Synthesis Goal

RTL synthesis goal: To provide an optimal

for a given hardware platform

RTL Synthesis

Inputs: A number of data path components, Binding of operations to data path components, A controller (FSM) that contains the detailed schedule (related to clock edge) of

computational I/O memory operations

RTL Synthesis

For FPGA, can use existing ASIC RTL synthesis techniques Relatively matured area But must consider: FPGA special circuitry features in logic blocks:

Fast carry chains ( better performance)

Blocks of memory Multipliers

FPGA flexible soft blocks Two stages: 1. Datapath synthesis 2. Control synthesis

Dataflow Graph

Input: DFG or CDFG DFG:

Means to describe a computing task in a streaming mode Operators: nodes Operands: Inputs of the nodes Nodes output can be used as input to other nodes

Data dependency in the graph Given a set of tasks {T1,,Tk}, a DFG is a DAG G(V,E), where

V (= T): the set of nodes representing operators and E: the set of edges representing data dependency between tasks

(b 4ac) b 2a

2

1 2

DFG

Any high-level program can be compiled into a DFG, provided that:

No loops No branching instructions.

Sequencing graph FSMD CDFG (Control DFG)

Datapath Synthesis

Steps: Implement each datapath node with a datapath component Flatten the datapath components to gates

Problems:

Discards information about regularity of design (bit-slice) Usually not possible to rediscover uses of specialized features of the CLBs (e.g., fast carry chain)

Solution:

Preserve special datapath structures

Datapath Synthesis

Technology-independent optimization Very much like ASIC synthesis techniques Not focus of this course:

Just a general taste

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Two-level-logic

X1

*

X2 X3 X2 X4

Products are implemented on the first level and the sum on the second level

Advantages:

*

*

X3

Drawbacks: Bad estimator of complexity during logic optimization Initially developed for PALs and

Two-level logic

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Multi-level-logic

2. Multi-level logic synthesis: Targets multi-level designs

X1 X2 X3

F2

Many Boolean functions on the path from the inputs to the outputs

Appropriate for mask-programmable or field programmable devices Multi-level will therefore be considered in this course

F1

X2 X4 X6 X5 X5

F3

Multi-level logic

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Boolean Networks

Multi-level logic: are usually represented using Boolean

OR OR

networks

A Boolean network: a DAG:

NOR

Node:

an arbitrary Boolean function

AND

Edge:

data dependency between nodes

XOR

NAND

Manipulation

Important factors: memory efficiency

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Synthesis Approaches

Synthesis Approaches: 1. Technology dependent:

Only valid gates (from the target library) are used in the node representation. The design is not tied to any library. A final mapping must be done to the final library. Mostly used

2. Technology independent:

1. All the Boolean equations are minimized, independent of the logic blocks. 2. Technology mapping maps the parts of the Boolean network to LUTs.

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Representation

1. Sum-Of-Products (SOP) 2. Factored Form (FF) 3. Binary Decision Diagram (BDD)

Sum-Of-Products:

Well understood Easy to manipulate Many optimization algorithms available Not representative of the logic complexity

Estimation of progress during logic minimization is difficult

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Representation: FF

Factored form (FF): Defined recursively: (FF = product) or (FF = sum). (product = literal) or (product = FF1*FF2). (sum = literal) or (sum = FF1+FF2).

Example:

c

Few manipulation algorithms.

a b ( d e)

b(d e)

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non-terminal:

Representation: BDD

Variable node:

(for variable xi) Two children low(v) , high(v) Constant nodes: terminal node: value(v) {0,1}

index(v)

{1, ,n}

A + B . C

A+B+C

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Representation: BDD

18

Representation: BDD

BDD Simplification

ABC + AC

19

Representation: BDD

Implementation by MUX

F = ABC +AC

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Node Manipulation

A suitable node representation

Goal:

Generation of an equivalent and cost effective simplified function

28

Decomposition: Take a single Boolean expression and replace with collection of new expressions:

A Boolean function f(X) is decomposable if we can find a

F = A B C + A B D + A' C' D' + B' C' D' F = M N + M' N' M=AB N=C+D

A B F C D F

(12 literals)

(8 literals)

A B C A B D A C D B C D

Before Decomposition

After Decomposition

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Decomposition: Example 2:

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Extraction: Identify common intermediate sub-functions from a set of given

functions.

F = (A + B) C D + E G = (A + B) E' H=CDE F=XY + E G = X E' H=YE X=A+B Y=CD

E A B C D A B C D E

A B F G H C D E X Y F G H

Before Extraction

After Extraction

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Extraction: Example 2:

32

F=AC + AD + BC + BD + E F = (A + B) (C + D) + E

A C A D B C B D E F A B C D E F

Before Factoring

After Factoring

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Substitution:

A function is reduced in complexity by using an additional input that was not previously in its support set.

The transformation requires the creation of a dependency, but it may also lead to dropping others.

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Substitution: Example:

35

Collapsing (Elimination):

The variable corresponding to the vertex is replaced by the corresponding expression. Reverse of substitution. To eliminate levels to meet timing constraints.

36

Collapsing:

Example:

37

References

[Bobda07] C. Bobda, Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications, Springer, 2007. I. J. Teich, Reconfigurable computing design and implementation, Lecture Slides. [Cong06] D. Chen, J. Cong and P. Pan, FPGA Design Automation: A Survey, Foundations and Trends in Electronic Design Automation, Vol. 1, No. 3 (2006) 195330. [DeMicheli94] G. De Micheli, Synthesis and optimization of digital circuits, McGraw-Hill, 1994.

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