EE534

VLSI Design System

Summer 2004

Lecture 7: Static Dynamic CMOS inverter
(CHAPTER 6)
Calculation of Delay times: Average current method

HL avg
OH load
HL avg
HL load
PHL
I
V V C
I
V C
,
) (
,
.
% 50

=
A
= t
LH avg
OL load
LH avg
LH load
PLH
I
V V C
I
V C
,
) (
,
.
% 50

=
A
= t
The average current during high to low transition can be calculated by using the
current values at the beginning and the end of the transition.

| | ) , ( ) , (
2
1
,
% 50
V V V V I V V V Vin I I
out OH in C OH out OH C HL avg
= = + = = =
| | ) , ( ) , (
2
1
,
% 50 OL out OL in C out OL in C LH avg
V V V V I V V V V I I = = + = = =
The average current during low to high transition can be calculated by using the
current values at the beginning and the end of the transition.

Review: Inverter delay, falling
Total fall delay =
(t
1
-t
0
) + (t
2
-t
1
)
(

|
|
.
|

\
|

+

+

= 1
) ( 4
ln
2
) (
, 0
, 0
, 0
, 0 OL OH
n T OH
n T OH
n T
n T OH n
L
PHL
V V
V V
V V
V
V V k
C
t
Review: Inverter delay, rising
Similar calculation as for falling delay
Separate into regions where PMOS is in linear,
saturation
(
(

|
|
.
|

\
|

+

+

= 1
) ( 4
ln
2
) (
, 0
, 0
, 0
, 0 OL OH
p T OL OH
p T OL OH
p T
p T OL OH p
L
PLH
V V
V V V
V V V
V
V V V k
C
t
Review: CMOS inverter actual delay
What if input has finite rise/fall time?not a step pulse
Both transistors are on for some amount of time
Capacitor charge/discharge current is reduced
2
2
2
) ( ) (
|
.
|

\
|
+ =
r
phl phl
t
input step t actual t
2
2
2
) ( ) (
|
|
.
|

\
|
+ =
f
plh plh
t
input step t actual t
Empirical equations:
Review: Propagation delay simulation results
At very short channel width, the delay approaches a limit value of about 0.2nsec
, which is mainly determined by technology-specific parameters, independent
of extrinsic capacitance component.
Review: Inverter delay revisited (Lower V
dd
Increases
Delay)
C
L
* V
dd
I
= T
d
T
d(Vdd=5)
T
d(Vdd=2)
=
(2) * (5 - 0.7)
2
(5) * (2 - 0.7)
2
~
4
I ~ (V
dd
- V
t
)
2
Relatively independent of logic function and style.
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
5.50
6.00
6.50
7.00
7.50
2.00 4.00 6.00
V
dd
(volts)
N
O
R
M
A
L
I
Z
E
D

D
E
L
A
Y

adder (SPICE)
microcoded DSP chip
multiplier
adder
ring oscillator
clock generator
2.0m technology
CMOS Ring Oscillator Circuit
CMOS Ring Oscillator Circuit (cont.)
T=t
PHL1
+t
PLH1
+ t
PHL2
+t
PLH2
+ t
PHL3
+t
PLH3
=2 t
P
+ 2t
P
+ 2t
P
=6t
P
nf
n T
f
p
p
2
1
2
1 1
=
= =
t
t
Calculation of interconnect delay: Switch-level model
(RC delay model)
Model transistors as switches and
resistances
Resistance R
on
= average
resistance for a transition
For NMOS t
phl
:
R
n

R
P

A
A
( )
(
(

|
|
.
|

\
|
+
|
|
.
|

\
|
=
= + = =
= =
CC out CC out
V V
D
DS
V V
D
DS
on
CC out NMOS CC out NMOS on
I
V
I
V
R
V V R V V R R
2
1
2
1
2
1
2
1
) ( ) (
C
L

Switch-level model
Delay estimation using switch-level model (for
general RC circuit):
R
n

C
L

| |
|
|
.
|

\
|
= =
= =
= =
= =
}
0
1
0 1
0 1
ln ) ln( ) ln(


1
0
V
V
RC V V RC t
dV
V
RC
t t t
dV
V
RC
dt
R
V
I
dV
I
C
dt
dt
dV
C I
p
V
V
p
Propagation delay of simple lumped RC network
For fall delay t
phl
, V
0
=V
cc
, V
1
=V
cc
/2
L p plh
L n phl
p
CC
CC
p
C R t
C R t
RC t
V
V
RC
V
V
RC t
69 . 0
69 . 0
) 5 . 0 ln(
ln ln
2
1
0
1
=
=
=
|
|
.
|

\
|
=
|
|
.
|

\
|
=
Standard RC-delay
equations
For long interconnect lines, RC must be distributed to obtain
accurate simulation results
Elmore Delay first order time constant
simple, close approximation of delay
Interconnect delay Elmore Delay
capacitor each by seen resistance
capacitors of number
1
=
=
=

e
=
k
j
p k
all for
k
N
j
j DN
R
N
R C
ij
t
Interconnect Resistance
Resistance is proportional to cross-sectional area
As interconnect scales, increase aspect ratio to maintain
same area.
m
w
l
R
wt
l
A
l
R
sheet wire
O =
= = =
) y resistivit (

Review: Designing Inverters for Performance
Reduce C
L
internal diffusion capacitance of the gate itself
interconnect capacitance
fanout
Increase W/L ratio of the transistor
the most powerful and effective performance optimization
tool in the hands of the designer

Increase V
DD
only minimal improvement in performance at the cost of
increased energy dissipation
Slope engineering - keeping signal rise and fall times
smaller than or equal to the gate propagation delays
and of approximately equal values
good for performance
good for power consumption

CMOS inverter Power Dissipation

Why worry about power? -- Power Dissipation
P6
Pentium
486
386
286
8086
8085
8080
8008
4004
0.1
1
10
100
1971 1974 1978 1985 1992 2000
Year
P
o
w
e
r

(
W
a
t
t
s
)

Lead microprocessors power continues to increase
Power delivery and dissipation will be prohibitive
Source: Borkar, De Intel
Why worry about power? -- Chip Power Density
4004
8008
8080
8085
8086
286
386
486
Pentium
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
P
o
w
e
r

D
e
n
s
i
t
y

(
W
/
c
m
2
)

Hot Plate
Nuclear
Reactor
Rocket
Nozzle
Suns
Surface
chips might become hot
Source: Borkar, De Intel
Chip Power Density Distribution
Power density is not uniformly distributed across the chip
Silicon is not a good heat conductor
Max junction temperature is determined by hot-spots
Impact on packaging, w.r.t. cooling
0
50
100
150
200
250
H
e
a
t

F
l
u
x

(
W
/
c
m
2
)
Willamette Power Distribution
200-250
150-200
100-150
50-100
0-50
Power Map
40
50
60
70
80
90
100
110
T
e
m
p
e
r
a
t
u
r
e

(
C
)
Al-SiC+ Epoxy Die Attach
100-110
90-100
80-90
70-80
60-70
50-60
40-50
On-Die Temperature
CMOS inverter power
Power has three components
Static power: when input isnt switching

Dynamic capacitive power: due to
charging and discharging of load
capacitance

Dynamic short-circuit power: direct
current from V
DD
to G
nd
when both
transistors are on
CMOS inverter static power
Static power consumption:
Static current: in CMOS there is no static current as long as V
in
<
V
TN
or V
in
> V
DD
+V
TP
Leakage current: determined by off transistor
Influenced by transistor width, supply voltage, transistor threshold
voltages
V
DD
V
I
<V
TN
I
leak,n
Vcc
V
DD
I
leak,p
Vo(low)

V
DD
Leakage (Static) Power Consumption
Sub-threshold current is the dominant factor.

All increase exponentially with temperature!
V
DD
I
leakage
Vout
Drain junction
leakage
Sub-threshold current
Gate leakage

Leakage as a Function of V
T
0 0.2 0.4 0.6 0.8 1
VGS (V)
I
D

(
A
)
VT=0.4V
VT=0.1V
10
-2
10
-12
10
-7
Continued scaling of supply voltage and the subsequent
scaling of threshold voltage will make subthreshold
conduction a dominate component of power dissipation.
An 90mV/decade V
T

roll-off - so each
255mV increase in
V
T
gives 3 orders of
magnitude reduction
in leakage (but
adversely affects
performance)
Exponential Increase in Leakage Currents
1
10
100
1000
10000
30 40 50 60 70 80 90 100 110
0.25
0.18
0.13
0.1
Temp(C)
I
l
e
a
k
a
g
e
(
n
A
/

m
)

From De,1999
Dynamic Power Consumption
Vin Vout
C
L
Vdd

Dynamic Capacitive Power and energy stored in the PMOS device
Case I: When the input is at logic 0: Under this
condition the PMOS is conducting and NMOS is in
cutoff mode and the load capacitor must be charged
through the PMOS device.
Power dissipation in the PMOS transistor is given by,
P
P
=i
L
V
SD
= i
L
(V
DD
-V
O
)
The current and output voltages are related by,
i
L
=C
L
dv
O
/dt
Similarly the energy dissipation in the PMOS device can
be written as the output switches from low to high ,





Above equation showed the energy stored in the
capacitor C
L
when the output is high.
2
2
0
2
0
0 0 0 0
2
1
) 0
2
( ) 0 ( ,
2
, ) (
DD L P
DD
L DD DD L P
V
O
L
V
O DD L P
O
V
O L
V
O DD L P
O
O DD L P P
V C E
V
C V V C E C V C E
d C d V C E dt
dt
d
V C dt P E
DD
DD
DD DD
=
= =
= = =
} } } }

v
v
v v v
v
v
Power Dissipation and Total Energy Stored in the CMOS Device
Case II: when the input is high and out put is low:
During switching all the energy stored in the load
capacitor is dissipated in the NMOS device
because NMOS is conducting and PMOS is in
cutoff mode. The energy dissipated in the NMOS
inverter can be written as,


The total energy dissipated during one switching
cycle is,

The power dissipated in terms of frequency can be
written as



2
2
1
DD L N
V C E =
2 2 2
2
1
2
1
DD L DD L DD L N P T
V C V C V C E E E = + = + =
2
DD
L T
T
T
V fC fE P
t
E
P t P E = = =
This implied that the power dissipation in the CMOS inverter is directly
proportional to switching frequency and V
DD
2
Dynamic capacitive power
Formula for dynamic power:

Observations
Does not (directly) depend on device sizes
Does not depend on switching delay
Applies to general CMOS gate in which:
- Switched capacitances are lumped into C
L
- Output swings from Gnd to V
DD
- Input signal approximated as step function
- Gate switches with frequency f
f V C P
DD L dyn
2
=
Not a function of transistor sizes!
Data dependent - a function of switching activity!
Lowering Dynamic Power
P
dyn
= C
L
V
DD
2
f
Capacitance:
Function of fan-out,
wire length, transistor
sizes
Supply Voltage:
Has been dropping
with successive
generations
Clock frequency:
Increasing
Short Circuit Power Consumption
Finite slope of the input signal causes a direct
current path between V
DD
and GND for a short
period of time during switching when both the
NMOS and PMOS transistors are conducting.
Vin Vout
C
L
I
sc
Dynamic short-circuit power
Short-circuit current flows from V
DD
to Gnd when both transistors
are on
Plot on VTC curve:

V
CC

V
CC

V
in

V
out

I
D

I
max

I
max
: depends on
saturation current
of devices
Dynamic short-circuit power
Approximate short-circuit current as a triangular wave
Energy per cycle:
f I V
t t
P
I V
t t t I
V
t I
V E
CC
f r
sc
CC
f r f
CC
r
CC sc
max
max
max
max
2
2 2 2
+
=
+
= + =
I
max
Short Circuit Currents Determinates
Duration and slope of the input signal, t
sc
I
peak
determined by
the saturation current of the P and N transistors which
depend on their sizes, process technology, temperature, etc.
strong function of the ratio between input and output slopes
- a function of C
L
P
sc
= t
sc
V
DD
I
peak
f
01
Impact of C
L
on P
sc
Vin Vout
C
L
I
sc
~ 0
Vin Vout
C
L
I
sc
~ I
max
Large capacitive load


Output fall time significantly
larger than input rise time.
Small capacitive load


Output fall time substantially
smaller than the input rise
time.
I
peak
as a Function of C
L
-0.5
0
0.5
1
1.5
2
2.5
0 2 4 6
time (sec)
x 10
-10
x 10
-4
C
L
= 20 fF
C
L
= 100 fF
C
L
= 500 fF
500 psec input slope

Short circuit dissipation
is minimized by
matching the rise/fall
times of the input and
output signals - slope
engineering.

When load capacitance
is small, I
peak
is large.

P
sc
as a Function of Rise/Fall Times
0
1
2
3
4
5
6
7
8
0 2 4
t
sin
/t
sou
t
V
DD
= 3.3 V
V
DD
= 2.5 V
V
DD
= 1.5V
normalized wrt zero input
rise-time dissipation
When load capacitance
is small (t
sin
/t
sout
> 2 for
V
DD
> 2V) the power is
dominated by P
sc
If V
DD
< V
Tn
+ |V
Tp
| then
P
sc
is eliminated since
both devices are never
on at the same time.

W/L
p
= 1.125 m/0.25 m
W/L
n
= 0.375 m/0.25 m
C
L
= 30 fF
Inverter power consumption
Total power consumption
leak CC
f r
CC CC L tot
stat sc dyn tot
I V f
t t
I V f V C P
P P P P
+
|
|
.
|

\
|
+
+ =
+ + =
2
max
2
Power reduction
Reducing dynamic capacitive power:
Lower the voltage (Vdd)!
- Quadratic effect on dynamic power

Reduce capacitance
- Short interconnect lengths
- Drive small gate load (small gates, small fan-
out)

Reduce frequency
- Lower clock frequency -
- Lower signal activity
f V C P
DD L dyn
2
=
Power reduction
Reducing dynamic capacitive power:
Lower the voltage (Vdd)!
- Quadratic effect on dynamic power

Reduce capacitance
- Short interconnect lengths
- Drive small gate load (small gates, small fan-
out)

Reduce frequency
- Lower clock frequency -
- Lower signal activity
f V C P
DD L dyn
2
=
Power reduction
Reducing dynamic capacitive power:
Lower the voltage (V
DD
)
- Quadratic effect on dynamic power

Reduce capacitance
- Short interconnect lengths
- Drive small gate load (small gates, small fan-
out)

Reduce frequency
- Lower clock frequency -
- Lower signal activity
f V C P
DD L dyn
2
=
Examples
f=500MHz
C
L
=15fF/gate
V
DD
=2.5V
P
dyn
=50W
For a design with I million gate
P
dyn
=50W!
Is this possible in reality? If not why?
P
dyn
=E
dyn
/2t
p
=580W for t
p
=32.5ps
P
dyn
=E
dyn
/2t
p
=155W for f=4GHz(250ps)

Power reduction
Reducing short-circuit current:
Fast rise/fall times on input signal
Reduce input capacitance
Insert small buffers to clean up slow input signals before
sending to large gate
Reducing leakage current:
Small transistors (leakage proportional to width)
Lower voltage
Retrospect on Design Trade-offs
Design trade-offs dance around the
triangle, but still important
Fundamental improvement that
shrinks the triangle:
Scaling in technology
(lithography improvement)
New functionality
New architecture
New algorithms
Good
Fast Cheap
(Lower-power and Robust)
(Short Delay) (Small Layout)