Whats a Hardware Description Language?

Two things distinguish an HDL from, say, C: Concurrency The ability to do several things simultaneously. i.e. different code-blocks can run concurrently Timing Ability to represent the passing of time and sequence events accordingly A powerful feature of the Verilog HDL is that we can use the same language for describing, testing and debugging our system

Basic Verilog with VCS- 1

Simulation Environment
control commands

INPUT
models.v test vectors libraries Assembly/ Microcode Feedback
Basic Verilog with VCS- 2

OUTPUT
Textual messages Simulator Tabular output Graphical waveform Visual drawings

What is Synthesis?
Verilog code:
always @ (A or B or C) begin case (1b1) A: result = 2b00; B: result = 2b01; C: result = 2b10; default: result = 2b00; endcase end

Translation
(& syntax-check)

Generic Boolean (GTECH) netlist

Constraints

Optimization
& Target Library Mapping

Synopsys HDL-synthesis Toolset

Target Technology Netlist

Basic Verilog with VCS- 3

Basic Modeling Structure

Module gate, block, chip, board, system, ... Pins, Interface Levels of abstractions
always @ (posedge clk).... assign #3 out=(sel)?in0:in1;

Ports

Body Instances Concurrent blocks

Multilevel

Basic Verilog with VCS- 4

module test_incrementer; reg clk, inc; wire [11:0] value; declarations initial begin clk =0; forever #20 clk = !clk; //clk gen end incrementer DUT(inc, value,clk); instance port connections

An Example
module incrementer(go, out, clk); input go,clk; output [11:0] out; reg [11:0] out; Procedural block initial out = 0; always @ (posedge clk) if (go) out = out +1; endmodule

always @(value) $display ($time,,"value = %0h",value);

initial concurrent blocks begin #10 inc = 1; // start incrementing #500 inc = 0; // stop incrementing end endmodule
Basic Verilog with VCS- 5

Lexical Conventions

Basic Verilog with VCS- 6

White Space
White space is used to separate words and to enhance readability. Verilog is a free format language White space characters are space, tabs, carriage returns, etc. Verilog ignores these characters except when they separate language tokens.
module pound_one; reg [7:0] a,a$b,b,c; // register declarations reg clk; initial begin clk=0; // initialize the clock c = 1; forever #25 clk = !clk; end /* This section of code implements a pipeline */ always @ (posedge clk) begin a = b; b = c; end endmodule

Basic Verilog with VCS- 7

Single line comments:

Begin with "//" and end with a carriage return May begin anywhere on the line. Multiple line comments: Begin with "/*" and end with a "*/" May begin and end anywhere on the line Everything in between is commented out
module pound_one; reg [7:0] a,a$b,b,c; // register declarations reg clk; initial begin clk=0; // initialize the clock c = 1; forever #25 clk = !clk; end

Comments

/* This section of code implements a pipeline */

always @ (posedge clk) begin a = b; b = c; end endmodule
Basic Verilog with VCS- 8

Coding style tip - Use single line comments for comments. Reserve multi-line comments for commenting out a section of code.

Strings
Strings are enclosed in double quotes and are

specified on one line. Verilog recognizes normal C escape Characters (\t, \n, \\, \",%%).
(prints: tab, new line, \ , , %)

"Scott's module is working just great!" "This format is spaced with a tab \t followed with this" "\n This puts a newline before this string" "Address = %h at time %d"

Quick Reference pg. 26 - text formatting codes

Basic Verilog with VCS- 9

Identifiers
Identifiers are names assigned by the user to Verilog objects such as modules, variables, tasks etc.

Identifiers must begin with an alphabetical character (a-z A- Z _ ) Identifiers may contain alphabetical characters, numerics, underscores and dollar signs (a-z A- Z 0-9 _ $).
module pound_one; reg [7:0] a,a$b,b,c; // register declarations reg clk; initial begin clk=0; // initialize the clock c = 1; forever #25 clk = !clk; end /* This section of code implements a pipeline */ always @ (posedge clk) begin a = b; b = c; end endmodule
Basic Verilog with VCS- 10

Identifiers in this module:

pound_one, a, a$b, b, c, clk,

Escaped Identifiers
The use of escaped identifiers allow any character to be used in an identifier. Escaped identifiers start with a backslash (\) and end with white space. Gate level netlists generated by EDA tools (like DC) often have escaped identifiers Examples: \ab#~*this=or=that \5-6 \bus_a[0] // typical of a Synopsys netlist \bus_a[1]

Basic Verilog with VCS- 11

Case Sensitivity
Verilog is case sensitive (so are Synopsys synthesis tools) Identifiers that do not match in case are considered unique All Verilog key words are in lower case Examples module Module MODULE

// keyword // unique identifier but not keyword // unique identifier but not keyword

Silly example... module MoDule (mODULE, modulE); input ... endmodule //horrible code, but legal

Quick Reference pg. 1 - reserved keywords

Basic Verilog with VCS- 12

Logic values

Verilog has 4 logic Values: 0 zero, low, false, not asserted

1 z or Z x or X

one, high, true, asserted high impedance unknown

Basic Verilog with VCS- 13

Integers & Real Numbers

Verilog numbers may be integers or real numbers. Integers may be sized or unsized. Syntax: where: <size> is the number of bits <base is b or B (binary), o or O (octal), d or D (decimal), h or H (hex) <value> is 0-9 a-f A-F x X z Z ? _ <size>'<base><value>

Examples: 2'b01, 6'o243,

Default radix is decimal 1 1'd1

78, 4'ha,

underscores ( _ ) are ignored (use them as you would commas). 836_234_408_566_343

a "?" is interpreted as Z (high impedance)

2'b?? 2'b101 2'bzz 2'b01, 4'hfcba 4'ha When <size> is less than <value> - the upper bits are truncated.

Basic Verilog with VCS- 14

Integers & Real Numbers -2

When <size> is greater than <value>, and the left-most bit of <value> is 0 or 1,
then zero's are extended to <size> bits. 4'b01 4'b11 4'b0001, 16'h0 4'b0011, 16'h1 16'h0000 16'h0001

When <size> is greater than <value>, and the left-most bit of <value> is an x then the x value is extended to <size> bits 4'bx1 4'bxxx1, 16'hx 16'hxxxx

When <size> is greater than <value>, and the left-most bit of <value> is a z then the z value is extended to <size> bits 4'bz1 4'bzzz1, 16'hz 16'hzzzz

Real numbers may be either in decimal or scientific notation.

Syntax: <value>.<value> or <mantissa>e<exp>

6.439 or 5.3e6

Basic Verilog with VCS- 15

Integers & Real Numbers Examples

3.14 decimal notation

6.4e3 16'bz 83 8'h0 2'ha5 2_000_000 16'h0x0z

scientific notation for 6400.0 16 bit z (z is extended to 16 bits) unsized decimal 8 bits with 0 extended to 8 bits 2 bits with upper 6 bits truncated (binary equivalent = 01) 2 million 16'b0000xxxx0000zzzz

Coding style tip - don't use " ? " in a number to indicate high impedance. It only adds confusion. If you want high impedance use " z "!!

Basic Verilog with VCS- 16

System tasks & functions

Ignored

Specific tasks and functions may be defined by EDA vendors and users to be used as part of the simulator. Begin with the dollar sign ( $ ) The Verilog standard has a number of standard $ defined Users may define their own built in tasks using the Programming Language Interface (PLI)

List of most commonly used built in tasks and functions: $monitor $display $time $stime $stop $finish Continuously monitors listed signals Prints message to the screen function that returns the current simulation time (64-bits) like above, but returns truncated lower 32-bits Halts execution but does not exit Halts execution and exits the simulation

See quick-reference guide pg. 26+27 for examples/syntax

Basic Verilog with VCS- 17

Compiler directives

Synthesizes

Compiler directives cause the Verilog compiler to take special actions Indicated by the grave accent character ( ` ) Directive remains in effect until it is overridden or modified. It is active across modules and files. List of most commonly used compiler directives: `define macro text_string text substitution of text_string for macro `include file_name file inclusion. Another source file is substituted here
`ifdef macro verilog source `else verilog source `endif Conditional Compilation
test_designA.v designA.v `define tpd 5 #`tpd a = 0; #`tpd c = f; . . . designA.v DUT (...); . . . vcs test_designA.v designA.v order is important because of `define

Quick Reference pg. 28+29 - compiler directives

Basic Verilog with VCS- 18

`timescale Compiler directive

Time scales establish the delay time base and precision in Verilog models. `timescale time_unit base / time_precision base

time_unit base:
time_precision base:

sets the time unit for 1 time step ie. What a delay of 1 means sets the precision ie how to round delays

Example: `timescale 1 ns / 100 ps time unit is 1 ns and round to the nearest .1ns By default a time step is unit-less. Once you set a time scale for any one module you must have a time scale set for all modules

Specify a `timescale for each module in your design

Basic Verilog with VCS- 19

Q. Which of the following code fragments (if any) will compile. What is wrong in each case (assume any Verilog syntax we have not covered yet is correct)? A: reg clk, 1a; integer fred; B: a = 0; /* this is a rather b = 0; simple comment */ C: include load_file; // reuse last-weeks code Q. What value is put into register a by each of these assignments? Assume a is 32 bits wide and has a value of unknown before each assignment. a = 32'b0; a = 64'haabbccddeeff0011; a = 16'h3x0; a = 24'b1; a = 16'bz;
Basic Verilog with VCS- 20

Quiz

Verilog Module
module name (port_names);
module port declarations

Modules contain declarations functionality timing

data type declarations procedural blocks continuous assignments user defined tasks & functions primitive instances module instances specify blocks endmodule

syntax: module module_name (signal, signal,... signal ) ;

endmodule

Basic Verilog with VCS- 21

Module Port Declarations

Scalar (1bit) port declarations: port_direction port_name, port_name ... ; Vector (Multiple bit) port declarations: port_direction [port_size] port_name, port_name ... ; port_direction : input, inout (bi-directional) or output port_name : legal identifier port_size : is a range from [msb:lsb] big endian or little endian may be used literal integers or parameters may be used input a, into_here, george; input [7:0] in_bus, data; output [8:31] out_bus; inout [maxsize-1:0] a_bus;

module name (port_names);

module port declarations

data type declarations procedural blocks continuous assignments user defined tasks & functions

primitive instances
module instances specify blocks endmodule

// scalar ports //vectored ports //vectored port //parameterized port

Basic Verilog with VCS- 22

Module Instances

Synthesizes

module name (port_names);

module port declarations

data type declarations procedural blocks continuous assignments user defined tasks & functions primitive instances module instances specify blocks endmodule

A module may be instantiated within another module. There may be multiple instances of the same module. Ports are either by order or by name. Use by order unless there are lots of ports Use by name for libraries and other peoples code (may change) Can not mix the two syntax's in one instantiation

syntax for instantiation with port order: module_name instance_name (signal, signal,...); syntax for instantiation with port name: module_name instance_name (.port_name(signal), .port_name (signal),... );
module example (a,b,c,d); input a,b; output c,d; . . . . endmodule example ex_inst_1(in_1, in_2, w, z); example ex_inst_2(in_1, in_2, , z); // skip a port example ex_inst_3 (.a(w), .d(x), .c(y), .b(z));

Basic Verilog with VCS- 23

Module Hierarchy
A hierarchical path in Verilog is in form of: module_name.instance_name.instance_name top.a.b.c is the path for the hierarchy below.

Synthesizes

top

instance
a b c

module

Basic Verilog with VCS- 24

Quiz
What (if anything) is wrong with the following lines of code?

input
inout

parity, data_bus [7:0];

[variable +2 : variable] port;

output bit, BIT;

module top;
test test_inst_a(into,reg_a,.outof(outof)); test test_inst_b(into,,outof);

Basic Verilog with VCS- 25

Data Types
Three data type classes: Nets Physical connections between devices Registers Storage devices, variables. Parameters Constants
syntax: data_type identifier, identifier... ; or data_type [msb:lsb] identifier, identifier ... ;

module name (port_names);

module port declarations

data type declarations procedural blocks continuous assignments user defined tasks & functions primitive instances module instances specify blocks endmodule

Basic Verilog with VCS- 26

Nets
Connect devices. Are continuously driven by the device that drives them. New values are propagated automatically when the driver changes. wire, tri wor, wand, tri0 tri1 trireg supply0,
Synthesizes Synthesizes

trior triand

Synthesizes

Synthesizes

Synthesizes

supply1

standard basic interconnect wired-OR outputs wired-AND outputs pulls down when tri-stated pulls up when tri-stated stores last value when tri-stated constant 0 or 1

examples: wire a,b; wor [7:0] in_bus; wand [8:31] out_bus;

// scalar wires // wired-OR bus // wired and bus

Coding style tip - Use "tri" instead of "wire" as a visual indicator for more than one driver on a net.
Basic Verilog with VCS- 27

Registers
Storage device (may

represent abstract or real).

May be used as variables. reg integer time real unsigned variable of any size signed 32-bit variable unsigned 64 bit variable signed floating point variable of double precision
Synthesizes

Synthesizes

reg a; reg [7:0] in_bus; integer i, j; time t; real b,c;

// scalar reg variable // vectored reg variable //32 bit signed variables // unsigned 64 bit variable // signed floating point variables

Basic Verilog with VCS- 28