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OBJECTIVE
Main objective of my work is to design a high-speed,low-
power Viterbi Decoder for Trellis Coded Modulation(TCM) systems We are modifying the register exchange method used in current system with the traceback method.
OVERVIEW
Power reduction in VDs could be achieved by reducing the
loop.
PROPOSED TECHNIQUE
The pre-computation architecture incorporated with T-
algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much.
T-algorithm calculates the optimal PM by using
TRACEBACK method.
A VITERBI DECODER
A viterbi decoder uses the Viterbi algorithm for
decoding a bitstream that has been encoded using Forward error correction based on a code. There are other algorithms for decoding a convolutionally encoded stream (for example, the Fano algorithm). Viterbi Decoder is also a parameterizable high performance IP core that performs decoding of the convolutionally encoded data as well as punctured codes.
Functional Diagram
BRANCH METRIC UNIT-A branch metric unit's function is to calculate the hamming distance.
each branch, the comparator compares the two partial metrics, and the selector selects an appropriate branch.
each state. The register records the decoded output sequence along the path starting from the initial state to the final state, which is same as the initial state. The approach may offer a high-speed operation, but it is not power efficient due to the need to copy all the registers in a stage to the next stage.
each state. The register records the decoded output sequence along the path starting from the initial state tothe final state, which is same as the initial state. The approach may offer a high speed operation, but it is not power efficient due to the need to copy all the registers in a stage to the next stage
survivor branch and the flip-flop records 1 (0) if the survivor branch is the upper (lower) path.
through the ram, and tracing a path backwards through the trellis.
This reads the bits out in backwards order.
IMPLEMENTATION TOOLS
VHDL
MODEL SIM XILINX
REFERENCE
[1] High-Speed Low-Power Viterbi Decoder Design for TCM Decoders Jinjin He, Huaping Liu, Zhongfeng Wang, Xinming Huang, and Kai Zhang IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 11, pp. 11721176 January 19, 2011. [2] J. B. Anderson and E. Offer, Reduced-state sequence detection with convolutional codes, IEEE Trans. Inf. Theory, vol. 40,no. 3,pp. 965-972,May 2008. [3] C. F. Lin and J. B. Anderson, M-algorithm decoding of channel convolutional codes, presented at the Princeton Conf. Info. Sci. Syst.,Princeton, NJ, Mar. 2006. [4] F. Chan and D. Haccoun, Adaptive viterbi decoding of convolutional codes over memoryless channels, IEEE Trans. Commun., vol. 45,no. 11,pp. 1386-1400,Nov 2006. [5] S. J. Simmons, Breadth-first trellis decoding with adaptive effort,IEEE Trans. Commun.,vol. 38, no. 1,pp. 3-12, Jan.2004. [6]Bandwidth-efficientmodulations, Consultive Committee For Space Data System,Matera,Italy,CCSDS 401(3.3.6)Green Book,Issue 1,Apr. 2003.