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# 74x181 4-bit ALU

An arithmetic and logic unit (ALU) is a combinational circuit that can perform any of a number of different arithmetic and logical operations on a pair of b-bit operands. The operation to be performed is specified by a set of function-select inputs. Typical MSI ALUs have 4-bit operands and three to five function-select inputs, allowing up to 32 different functions to be performed.

## Logic symbol of74x181

S0 to S3 are selection lines M is mode selection A0-A3,B0-B3 are inputs F0-F3 are outputs Cin is carry input Floyd,7/12/12 Cout Digital Fundamentals, 10th ed is carry

## Functions performed 4-bit ALUs

The 74x381 and 74x382 provide only eight different functions. 74x381 provides group-carry-look ahead outputs where as 74x382 provides ripple carry and over flow outputs

## Floyd,7/12/12 Digital Fundamentals, 10th ed

Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity alu_74x381 is port(s: in std_logic_vector(2 downto 0); a,b: in std_logic_vector(3 downto 0); f: out std_logic_vector(3 downto 0); cin: out std_logic); End alu_74x381; Architecture behavior of alu_74x381 is Begin process (s,a,b) begin case s is when 000=> f <= 0000; when 001=> f <= b-a-1+cin; when 010=> f <= a-b-1+cin; when 011=> f <= a+b+cin;
Floyd,7/12/12 Digital Fundamentals, 10th ed

## when 100=> f <= a xor b; when 101=> f <= a or b;

The 181 and 381 provide group-carry-look ahead outputs that allow multiple ALUs to be cascaded without rippling carries between 4-bit groups. The ALUs use carry look ahead to produce carries internally. G_L and P_L outputs that are carry-look ahead signals for the entire 4-bit group. G_L = (g3+p3.g2+p3.p2.g1+p3.p2.p1.go)

## Floyd,7/12/12 Digital Fundamentals, 10th ed

P_L = (p3.p2.p1.po)

16 bit ALU
When ALUs(74x381) are cascaded, from the each ALU it generates two signals P and G . But for the next stage we need Cin as a input. i.e. we have to generate the carry for the each stage from P and g by using 74x182 as Ci+1 = gi + pi.ci = (gi +pi).(gi+ci). The 74x182 is nothing but look ahead carry circuit used to generate the carries C1,C2,C3 as C1=(g0+p0).(g0+c0) C2=(g1+p1).(g1+g0+p0).(g1+g0+c0) C3=(g2+p2).(g2+g1+p1).(g2+g1+g0+p0). Floyd,7/12/12 Digital Fundamentals, 10th ed

## Logic symbol of 74x182

Floyd,7/12/12 Digital Fundamentals, 10th ed

P0-P3 carry propagation inputs G0-G3 carry generation inputs C0 is carry input C1,C2,C3 is carry outputs G is carry generation output

## Floyd,7/12/12 Digital Fundamentals, 10th ed

Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity alu_16 bit is port(s: in std_logic_vector(2 downto 0); a,b: in std_logic_vector(15 downto 0); f: out std_logic_vector(15 downto 0); cin: out std_logic); End alu_16; Architecture structural of alu_74x381 is Signal g_l,p_l :std_logic_vector(3 downto 0); Signal c4,c8,c12:std_logic; component alu_74x381 is port(s: in std_logic_vector(2 downto 0); a,b: in std_logic_vector(3 downto 0); f: out std_logic_vector(3 downto 0); p,g:out std_logic ; cin: out std_logic);
Floyd,7/12/12 Digital Fundamentals, 10th ed

## End component; component ic_74x182 is

Begin P1: alu_74x381 portmap(f(15 downto 12),p_l(3),g_l(3),s(2 downto 0) ,a(15 downto 12),b(15 down to 12),c12); P2: alu_74x381 portmap(f(11 downto 8), p_l(2),g_l(2), s(2 downto 0) ,a(11 downto 8),b(11 down to 8),c8); P3: alu_74x381 portmap(f(7 downto 4), p_l(1),g_l(1), s(2 downto 0), a(7 downto 4),b(7 down to 4),c4); P4: alu_74x381 portmap(f(3 downto 0), p_l(0),g_l(0),s(2 downto 0), a(3 downto 0),b(3 down to 0),c0); P5: ic_74x182 portmap(c12,c8,c7,p,g,s(2 downto 0), p(3 downto 0),g(3 down to 0),c0); End structural;