--T bistabil s Q i Q' izlazima i mogucnoscu set-a library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.

ALL; entity auditorne is port( T,CP,SET:in std_logic; Q,Qn:out std_logic); end auditorne; architecture Behavioral of auditorne is type stanje is(S0,S1); signal sad_stanje,sljed_stanje:stanje; signal temp:std_logic; begin process(CP,SET) begin if(SET='1')then sad_stanje<=S1; elsif(CP'event and CP='1')then sad_stanje<=sljed_stanje; --ovo je s asinkronim set, ako bi htjeli sinkroni set, prvo bi r adili provjeru CP'event, a zatim, unutar nje bi radili provjeru SET='1'. --Shvatili? Da? Ne? end if; end process; process(sad_stanje,T) begin case sad_stanje is when S0=> temp<='0'; if(T='1')then sljed_stanje<=S1; end if; when S1=> temp<='1'; if(T='1')then sljed_stanje<=S0; end if; end case; end process; Q<=temp; Qn<=not temp; end Behavioral;