B-25 ankit bhardwaj

PRACTICAL 07
Aim:- Write VHDL program to build D,SR, JK, T flipflops using behavioural coding. Verify the
output of each flipflop using respective truth table

SR Flipflop
CODE:-
library IEEE;
use IEEE.std_logic_1164.all;

entity SR_flip_flop is
port(s: in std_logic;
r: in std_logic;
clk: in std_logic;
reset: in std_logic;
q:out std_logic;
qb:out std_logic);
end SR_flip_flop;

architecture behavioural of SR_flip_flop is

begin
process(s,r,clk,reset)
begin
if(CLK='1' and s='0' and r='0') then
q<=reset;
elsif(clk='1' and s='1' and r='1') then
q<='U';
elsif(clk='1' and s='0' and r='1') then
q<='0';
elsif(clk='1' and s='1' and r='0') then
q<='1';
else
q<=reset;
end if;

end process;
end behavioural;
OUTPUT:-

D Flipflop
CODE:-
library IEEE;
use IEEE.std_logic_1164.all;

entity D_flip_flop is
port(D,CLK: in std_logic;
Q: out std_logic);
end D_flip_flop;
architecture behavioural of D_flip_flop is
begin
process(D,CLK)

begin
if(CLK='1') then
Q<=D;
end if;
end process;
end behavioural;

OUTPUT:-

T Flipflop
CODE:-
library IEEE;
use IEEE.std_logic_1164.all;
entity T_flip_flop is
port(T,CLK,RESET: in std_logic;
Q:out std_logic);
end T_flip_flop;
architecture behavioural of T_flip_flop is
begin
process(T,CLK,RESET)
begin
if(CLK='1' and T='0') then
Q<=RESET;
elsif(CLK='1' and T='1') then
Q<=not(RESET);
else
Q<='U';
end if;
end process;
end behavioural;

OUTPUT:-
JK Flipflop
CODE:-
library IEEE;
use IEEE.std_logic_1164.all;

entity JK_flip_flop is
port(J,K,CLK,RESET: in std_logic;
Q: out std_logic);
end JK_flip_flop;
architecture behavioural of JK_flip_flop is
begin
process(J,K,CLK,RESET)
begin
if(CLK='1' and J='0' and K='0') then
Q<=RESET;
elsif(CLK='1' and J='1' and K='1') then
Q<=not(reset);
elsif(CLK='1' and J='0' and K='1') then
Q<='0';
elsif(CLK='1' and J='1' and K='0') then
Q<='1';
else
Q<='U';
end if;
end process;
end behavioural;
OUTPUT:-