Dis Ruffing

HVDC Grid Protection Based on
Fault Blocking Converters
Von der Fakultät für Elektrotechnik und Informationstechnik

der Rheinisch-Westfälischen Technischen Hochschule Aachen
zur Erlangung des akademischen Grades eines
Doktors der Ingenieurwissenschaften
genehmigte Dissertation
vorgelegt von
Philipp Frederic Ruffing, M.Sc.

aus Saarbrücken
Berichter: Univ.-Prof. Dr.-Ing. Armin Schnettler

Prof. Ramon Blasco-Gimenez, Ph.D.
Tag der mündlichen Prüfung: 23. Juli 2020
Diese Dissertation ist auf den Internetseiten der Universitätsbibliothek online verfügbar.
Aachener Beiträge zur HOCHSPANNUNGSTECHNIK
Herausgeber: Univ.-Prof. Dr.-Ing. A. Schnettler
Philipp Frederic Ruffing

HVDC Grid Protection Based on Fault Blocking Converters
ISBN: 978-3-95886-365-1
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Acknowledgement i
Acknowledgement
This work has been created during my time as research associate at the Institute
for High Voltage Technology at the RWTH Aachen University.
My special thanks go to Univ.-Prof. Dr.-Ing. Armin Schnettler, who made this
work possible. His trust placed in me, his constant support, encouragement and
valuable advice have contributed significantly to the success of my work.
I would like to thank Prof. Ramon Blasco-Gimenez, Ph.D. for taking over the
co-supervisor and for his great interest in the topic.
Moreover, I thank my colleagues for our time together at the institute and their
constant support. I express particular thanks to my present and former colleagues
of the team DC Systems for all our technical discussions, which have contributed
to the success of this work. Furthermore, I would like to show my appreciation to
all the students, who supported me with their master and bachelor theses as well
as their work as student research assistants.
In addition, I would like to pay my special regards to my family who enabled and
encouraged my education. I am very grateful for their constant support.
My sincere thanks go to my wife Katharina, who patiently and understandingly
accompanied me on the way to the finished dissertation and in all situations of
life.
Aachen, July 2020

Abstract iii
Abstract
Multi-terminal HVDC systems are envisioned as a technically and economically

promising solution for the large-scale integration of renewable energy sources
into power systems. To limit the impact of contingencies in HVDC networks,
which might transmit several gigawatts of electric power, on surrounding AC
transmission systems, DC faults must be separated quickly and reliably from the
remaining part of the system. Several strategies have been proposed to enable the
fast separation of faulted DC lines, either based on fast DC circuit breakers or
fault-blocking converters, like full-bridge Modular Multilevel Converters.
Due to their high degree of controllability even during fault situations, HVDC
networks based on fault-blocking converters enable a quick de-energisation of the
DC system and hence allow the separation and isolation of a faulted line under
near-zero current and voltage conditions. Consequently, such protection systems
allow the application of fault separation devices with reduced current breaking
requirements compared to full-size DC circuit breakers.
This work evaluates the potential and improves the performance of MTDC
protection systems based on fault-blocking converters. To enhance the speed of
the fault separation process and reduce the requirements on the switchgear during
current interruption, a DC fault control method is developed, which enables the
dynamic adjustment of the DC terminal currents and voltages as well as the
currents flowing into the faulted line. Thereby, the protection system allows the
application of fault separation units with low or even no DC current interruption
capabilities while enabling a fast fault separation. To facilitate a quick recovery
of the DC grid voltage and its power flow, restoration methods for monopolar and
bipolar HVDC networks are examined and refined.
Based on the definition of functional requirements, including requirements on
interoperability and extensibility, as well as quantifiable performance indicators,
the entire process from fault detection to system recovery is assessed in the
relevant network and circuit configurations. A qualitative comparison with
protection systems based on fast DC circuit breakers located at every line end of
an HVDC network indicates that investigated protection system can be a
competitive solution depending on the network’s size and the requirements of the
surrounding AC systems. Finally, the thesis gives first results on the application
of protection strategies based on fault-blocking converters in extended HVDC
grids.
Table of Contents v
Table of Contents
Acknowledgement .............................................................................................. i
Abstract ............................................................................................................. iii
1 Introduction ............................................................................................. 1
1.1 Motivation of the topic ...................................................................... 2
1.2 State of knowledge ............................................................................ 4
1.2.1 HVDC Network and Circuit Topologies................................ 4
1.2.2 DC Fault Handling with VSCs............................................... 6
1.2.3 Multi-Terminal HVDC Network Protection Philosophies ..... 9
1.2.4 Fault Handling in HVDC Networks with Fault-Blocking
Converters ............................................................................ 11
1.3 Objectives and Investigative Approach ........................................... 15
2 Physical and Technological Considerations ........................................ 19

2.1 Analytical Description of the MMC ................................................ 19
2.1.1 Converter Current Dynamics ............................................... 21
2.1.2 Converter Energy Dynamics ................................................ 23
2.1.3 DC Voltage Dynamics ......................................................... 26
2.2 Protection Algorithms for MTDC Networks ................................... 26
2.2.1 Fault Detection ..................................................................... 27
2.2.2 Fault Localisation ................................................................ 28
2.3 Circuit Breakers and Switchgear ..................................................... 29
2.3.1 HVDC Circuit Breakers ....................................................... 29
2.3.2 Conventional AC Circuit Breakers ...................................... 32
2.3.3 Disconnecting Switches ....................................................... 34
2.4 Pole Voltage Balancing in HVDC Systems .................................... 34
vi Table of Contents
3 Requirements and Evaluation Criteria................................................ 37

3.1 Functional Requirements................................................................. 37
3.2 Identification of Key Performance Indicators ................................. 40
4 HVDC Network and Component Modelling ....................................... 45

4.1 Test Network ................................................................................... 45
4.2 Converter Stations ........................................................................... 48
4.3 Transmission Lines ......................................................................... 51
4.4 Fault Separation Units ..................................................................... 52
4.4.1 DC Circuit Breakers............................................................. 52
4.4.2 AC Circuit Breakers............................................................. 53
4.5 Voltage Balancing Equipment ........................................................ 55
4.6 Busbar Design, Protection and Communication System ................. 55
4.7 Wind Power Plants .......................................................................... 57
5 Converter Controls ................................................................................ 59

5.1 Current Controllers (Inner Loops)................................................... 60
5.1.1 AC Current Control.............................................................. 60
5.1.2 Internal Current Control Loop ............................................. 63
5.1.3 DC Current Control Loop .................................................... 64
5.2 Reference Controllers (Outer Loops) .............................................. 65
5.2.1 Converter Energy Balancing ................................................ 66
5.2.2 DC Reference Controls ........................................................ 67
5.2.3 Grid Forming Control .......................................................... 69
6 MTDC Fault Separation Strategy ........................................................ 71

6.1 DC Fault Control for Fault-Blocking Converters ............................ 71
6.1.1 DC Current Limitation ......................................................... 72
6.1.2 DC Fault Control Methods................................................... 75
6.1.3 Analysis of the DC Fault Control Methods.......................... 78
Table of Contents vii
6.2 Analysis of Fault Separation Units.................................................. 81

6.2.1 Requirements on FSUs ........................................................ 81
6.2.2 Low-Voltage and -Energy DC Circuit Breakers .................. 83
6.2.3 Conventional AC Circuit Breakers ...................................... 89
6.3 HVDC Grid Restoration .................................................................. 97
6.3.1 Analysis of the DC voltage restoration ................................ 97
6.3.2 Dynamic Braking Systems ................................................... 99
6.3.3 AC-Side Grounding and Zero-Sequence Control .............. 100
6.3.4 Converter Controlled Rebalancing..................................... 101
6.3.5 Comparison of the Voltage Restoration Methods .............. 105
7 System Impact ...................................................................................... 109

7.1 Performance Evaluation ................................................................ 109
7.2 Network Extension ........................................................................ 113
7.3 DC-FRT Requirements on Surrounding Networks ....................... 115
8 Conclusion and Further Research Needs .......................................... 119

References ...................................................................................................... 124
List of publications......................................................................................... 137
List of abbreviations....................................................................................... 139
Appendix ........................................................................................................ 141
Introduction 1
1 Introduction
In recent years, the electric power generation and power transmission has started
to change drastically. The desire to reduce the depletion of fossil fuels and phase-
out nuclear power plants along with the growing importance of sustainability and
environmental awareness cause a shift from traditional to modern and renewable
power generation with a low carbon footprint [IPC14, IPC18].
The United Nations Framework Convention on Climate Change formulated the
goal to hold “the increase in the global average temperature to well below 2°C
above pre-industrial levels and to pursue efforts to limit the temperature increase
to 1.5°C above pre-industrial levels, recognizing that this would significantly
reduce the risks and impacts of climate change” [UNa15]. Consequently,
industrialised countries have to drastically reduce their greenhouse gas emission
[IPC18] and several countries have formulated the objective to increase their
share of renewable energy sources (RES) in energy consumption significantly by
2030:
x China: 35 % share of RES by 2030 [Nat18]
x European Union: 32 % share of RES by 2030 [Eur18b]
x India: 40 % share of electric power installed capacity from non-fossil fuel
based energy resources by 2030 [UNF15]
To meet these objectives, a significant increase in wind and photovoltaic power
generation is envisaged world-wide within the next decades [IRE15, Gos17,
REN17]. Especially in Europe, offshore wind power plants (WPP) are key RESs
for this purpose [REN17]. In 2018, Europe’s wind power generation capacity has
increased to more than 18.5 GW [Win19b], while it is envisioned to increase to
230 – 450 GW by 2050 [Eur18a, Win19a]. This transition from conventional
power generation based on fossil fuels and nuclear reactors to RESs causes
enlarged distances between production and consumption of the electrical energy
[ENT18]. Moreover, the increasing risk of volatile supply and unplanned, i.e.
weather related, power shortages require an increase in the grid interconnection
capacity to ensure the system’s stability [Eur14, Her16]. Accordingly, the
European transmission grid needs significant reinforcements within the next
decades [ENT18].
Voltage source converter (VSC) based high voltage direct current (HVDC)
systems, which allow a flexible and efficient bulk power transmission over long
2 Introduction
distances, have become a reliable technology for new grid reinforcements [Dor16,
CIG17b, ENT18, NEP19]. Particularly for the connection of offshore WPPs,
HVDC connections are technically advantageous and economically viable, often
even for relatively short distances [CIG17b]. In addition, VSC HVDC systems
are able to supply ancillary services to adjacent AC grids, such as reactive power
and frequency control as well as power oscillation damping [Dor16, Sha16].
Consequently, VSC HVDC transmission is considered as a key solution for future
extensions of today’s power systems to enable a vast integration of RES [Her16].
Several point-to-point links, which interconnect countries, couple asynchronous
zones and connect offshore WPPs to shore, have been built during the last decade
[CIG18b]. Due to the rising maturity of the technology and the need to increase
operational flexibility, multi-terminal DC (MTDC) networks are planned as key
elements in future transmission grids, such as the Zhangbei grid in China or the
German Ultranet (including the A North extension) [Pan18, NEP19]. With the
Zhoushan and Nan’ao schemes in China, the first VSC MTDC systems with three
and five terminals are in operation [NRE14, Bor15]. In addition to relatively small
MTDC networks, several initiatives combining transmission system operators
(TSOs), vendors, academia and environmental NGOs, envision meshed HVDC
networks as a technically and economically feasible solution for the vast
integration of RES [TWE13, e-H15, Fri18, Cut18]. In particular in northern
Europe, meshed offshore DC grids are considered for the integration of offshore
wind energy as well as interconnection of different countries and synchronous
zones [PRO17a, Bes18].
1.1 Motivation of the topic
Regardless of the technological, operational and economic drivers for MTDC

networks, several fundamental challenges – especially regarding the protection of
MTDC systems – need to be overcome [Kon15, Dor16]. The safe and reliable
handling of DC-side short-circuit faults is essential for the integration of HVDC
networks. However, the absence of natural zero-current crossings and the rapid
increase of fault currents, which can lead to the destruction of semiconductor
based HVDC grid components, makes the fault handling in HVDC systems much
more challenging than in HVAC systems [CIG17a, Let19]. Contrary to the
protection of AC networks, for which standards have been elaborated over
decades, there is no dominating technology for the protection of HVDC networks
and the standardisation process has only just started [Let19].
The current strategy for DC-side fault handling in existing VSC based HVDC
systems is to shut down the entire system by opening the AC-side circuit breakers
Introduction 3
[Her16, Tan07]. If this concept is applied to a DC grid and the separation of a

faulted line is required, disconnectors at the ends of the affected line can only be
opened after the fault currents in the network decay to values close to zero and
the grid is fully de-energised [Tan07]. Depending on the network configuration
and the fault type, this process may take a few hundred milliseconds to seconds
[Tan07, PRO17b]. However, due to high reliability requirements on MTDC
systems, a long-term loss of the entire DC network might not be acceptable.
Consequently, this concept is unlikely to be sufficient for DC grids [Abe17,
PRO17b]. To reduce the loss of power transmission capacity and thereby the
effects of DC contingencies on the transient stability of adjacent AC networks, a
reliable, fast and selective separation of faulted DC lines, as depicted in
Figure 1-1, is required [Abe17, CIG17b]. Moreover, the protection system of
HVDC grids connected to islanded AC networks, such as offshore WPPs, must
support that the components of these AC networks can ride through DC grid faults
without a long-term disconnection of their generation units, e.g. wind turbines
[CIG15].
Figure 1-1: Selective separation of a faulted line in a MTDC network

From an operational perspective, it would be desirable to install fast DC circuit
breakers (CBs) at each line end of a DC network – similar to AC transmission
systems – and thereby limit the impact of DC faults. Moreover, protection systems
based on fast DC CBs permit the use of commercially attractive fault-feeding
converters – e.g. half-bridge (HB) based modular multi-level converters (MMC)
– in MTDC systems. However, most of these DC circuit breaker configurations
require large current-limiting inductors, which can be in the order of tens to
hundreds of millihenry, to protect themselves and other grid components (e.g. the
converters) against high fault currents [Kon15, CIG17a, PRO17b, Bra19]. Due to
the component costs of DC CBs as well as the costs associated with the weight
and volume of breakers and their reactors, a selective protection system of highly
meshed DC networks, which requires a large number of DC CBs (e.g. at least 16
DC CBs for the four terminal network depicted in Figure 1-1), may become a
significant part of the total installation and maintenance costs [Ngu15, Jov18].
Particularly the installation of DC CBs and inductors on offshore platforms might
4 Introduction
be very expensive, since the platform costs highly correlate with their weight and
volume [PRO17a].
On the contrary, fault-blocking converters (FBCs), which are able to interrupt and
control fault currents, e.g. full-bridge (FB) MMCs, mixed stack1 MMCs and the
alternative arm converter (AAC), are gaining more attention in the recent past
[Mer10, Sta14, Jud18, Ngu19]. In case of a DC fault, these converters prevent a
fault current contribution from the AC to the DC system. After a transient
discharge of the line capacitances into the fault location, the currents within the
DC network quickly decay to values close to zero. The resulting residual currents
can then be interrupted by switches located at the line ends [Pet16, CEN18]. On
the one hand, the switches need to interrupt residual DC currents and withstand a
transient interruption voltage (TIV). On the other hand, they have to isolate the
faulted line from the rest of the grid. Due to the significantly reduced requirements
on switching devices and no or only a very limited need for line inductors,
converter stations based on this concept are expected to have a lower footprint
compared to the combination of fault-feeding converters with fast DC CBs
[Kon11, Jov18].
This work aims to investigate and enhance the applicability of converters with
fault-blocking and controlling capability in combination with residual current
breaking devices for the protection of multi-terminal and meshed HVDC systems.
1.2 State of knowledge
To evaluate the requirements on MTDC protection systems it is essential to have

a deep understanding of the impact of faults on HVDC networks and their
components. More specifically, the status of research regarding MTDC protection
systems based on FBCs is analysed and pending issues are deduced.
1.2.1 HVDC Network and Circuit Topologies
There are different network and circuit topologies as well as types of transmission
lines under consideration for future HVDC systems, which have fundamental
influences on the characteristic system behaviour under DC faults [Her16,
CEN18]. Since the specific design of a network depends on technical and
economical as well as on regulatory conditions, the different options need to be
1
Hybrid or mixed stack MMCs consist of a combination of HB- and FB-SMs
Introduction 5
considered in the design and the evaluation of HVDC protection strategies

[PRO17b, Let19].
Figure 1-2 (left) provides an overview of the major network topologies – point-
to-point links, radial networks and meshed networks. In contrast to point-to-point
systems, in which a permanent DC line fault causes an outage of the entire DC
pole2, MTDC networks might require the selective separation of faulted lines or
zones to ensure a continued operation of the remaining DC network. Thus, fault
separation units (FSUs) need to be located at every line end (cf. Figure 1-2 (left))
or at the boundaries of the zones, which are to be separated [CEN18].
Independent of the grid topology, HVDC systems are classified into two main
circuit configurations: Monopole and bipole – illustrated in Figure 1-2 (right).
The monopole configuration is subdivided in the symmetric and asymmetric
monopole. While the asymmetric monopole is effectively grounded at one of the
DC conductors, the symmetric monopole is isolated on the DC side [CEN18]. A
bipole with dedicated metallic return (DMR) comprises two asymmetric
monopoles, which have a common effectively grounded return conductor. In case
of a single pole DC fault, the unaffected pole can be operated as an asymmetric
monopole, ensuring a redundancy of 50 % of the rated transmission capacity. A
bipole HVDC network without a DMR is called rigid bipole. In this case, the
midpoint of the network is effectively grounded at one station and floating at the
other stations [CEN18].
Symmetrical Monopole
Asymmetrical Monopole
Bipole with Dedicated Metallic Return
Rigid Bipole
Point-to-Point Radial MTDC Meshed MTDC
System Network Network
Fault Separation Units
Figure 1-2: DC network (left) and circuit topologies (right)

In contrast to pole-to-pole faults, which lead to high fault currents with steep
increases regardless of the DC system’s grounding, the characteristic behaviour
of single pole-to-ground faults strongly depend on the configuration. Pole-to-
2
The entire link in case of a monopole and the affected pole in case of a bipole system
6 Introduction
ground faults in DC grids, which are effectively grounded on the DC side, e.g.
bipole systems with DMR, will cause fault currents similar to pole-to-pole faults
in monopole systems, due to the low-impedance of the fault current path [Let14,
CEN18]. The prospective fault current is significantly lower for the same pole-
to-ground fault in a symmetric monopole system, since the fault current path has
a much higher impedance. However, the isolated neutral point of a symmetric
monopole system may lead to overvoltages on the unaffected pole of up to twice
of the nominal voltage, whereas the affected pole is completely discharged
[Dan18, Bra19]. Especially during the recovery of the DC grid, which commences
after the fault has been separated, this unbalance between the conductors has to
be considered. Since the circuit topology and the earthing of a HVDC network
have a fundamental influence on possible fault currents, transient overvoltages
and the grid recovery, the different circuit configurations have to be considered
in the design and analysis of DC protection systems [Dan18, Ruf19b, Wan19].
Future HVDC networks can comprise both overhead line (OHL) and underground
cable segments. In Europe, however, they will be predominantly based on power
cables, due to the public objection against new OHL corridors, the integration of
offshore wind energy and the interconnection of countries located around the
North and Baltic Seas [Sta14]. In other regions, such as China, OHLs are
considered as primary option for new HVDC corridors [Gos17]. The type of the
transmission line has a fundamental impact on a network’s behaviour during DC
fault situations, since the characteristic impedances of both transmission line
types differ from each other. In addition, the DC fault handling requirements may
vary between the two transmission types, e.g. the capability to automatic re-
closure sequences in OHL sections [Rus14, Dor16, Pan18].
1.2.2 DC Fault Handling with VSCs
In the beginning of VSC-based HVDC transmission the prevailing topologies

were two-level and other low-level converters. However, the complex design of
transistor-based valves, which have to be able to withstand hundreds of kilovolts,
as well as the disadvantageous behaviour of low-level VSCs during DC faults,
impeded the application of HVDC systems based on these converters [Sha16].
The Modular Multilevel Converter, depicted in Figure 1-3, overcomes these
limitations. Since its first commissioning in the Transbay Cable Project in 2010,
the MMC or alterations of this converter type is the choice of technology for VSC-
based HVDC systems across all manufactures [Wes10, Dor16].
Introduction 7
DC PoC P
SM1 SM1 SM1 LDC,T

Half-Bridge SM
SM2 SM2 SM2
SM3 SM3 SM3
SMn SMn SMn
AC PoC
Larm Larm Larm
Larm Larm Larm Full-Bridge SM

SM1 SM1 SM1
SM2 SM2 SM2
SM3 SM3 SM3
SMn SMn SMn LDC,T
DC PoC N
Figure 1-3: Modular Multilevel Converter with half- and full-bridge submodules [Sha16]
An MMC consists of six identically constructed converter arms, connecting the
phases of the AC system with either the positive (P) and the negative (N) pole of
the DC point of connection (PoC). Each arm comprises a string of n submodules
(SM) and an arm inductance Larm, which is required for the converter control and
current limitation. To protect the converter against surge currents, inductors LDC,T
can be implemented at the DC terminal. The sinusoidal step voltage of each arm
is created by inserting or bypassing the SM capacitors using bipolar switching
devices – usually Insulated Gate Bipolar Transistors (IGBTs). On the AC side,
the converter is typically connected to the AC-PoC via a transformer, which
adjusts the voltage levels and provides a galvanic isolation between the converter
and the AC system. Besides the reduced stresses on the converter’s components,
the MMC design allows an independent control of its active and reactive power.
Hence, the converter can supply ancillary services to the AC system like a static
synchronous compensator (STATCOM) [Les03, Jov15, Sha16].
Regarding their DC fault handling capabilities, MMCs can be classified into two
major groups: Fault-feeding and fault-blocking converters.
Fault-Feeding Converters (FFC)
All presently installed MMC-HVDC systems are based on half-bridge (HB)

submodules, which comprise two IGBTs with antiparallel diodes and a capacitor
(cf. Figure 1-3). These SMs are solely able to bypass or insert their capacitors
with positive polarity. During a low-impedance DC fault the IGBTs of HB-SMs
are usually blocked as soon as the fault is detected to prevent an uncontrolled
discharge of the capacitors and protect them against overcurrents [Jov15]. Even
8 Introduction
though the IGBTs are blocked, their anti-parallel diodes will conduct in case of a
DC undervoltage and the converter behaves like an uncontrolled diode rectifier
[Sha16]. Thus, the AC networks will feed a DC fault via the HB-MMCs. A
consequence from converter blocking is the loss of its controllability and hence
its reactive power support to the AC grid [Dor16]. Since the converter is not able
to limit or interrupt DC fault currents by itself, AC circuit breakers on the AC-PoC
or DC circuit breakers on the DC-PoC need to open in order to protect the
system’s components and extinguish the fault current [CIG18a].
Fault-Blocking Converters
An alternative to fault-feeding converters (e.g. HB-MMC) is the usage of

full-bridge (FB) based FBCs [Pet16, Jov18]. Since FB submodules comprise two
additional IGBTs (cf. Figure 1-3 – full-bridge SM), they can insert their
capacitors both with positive and negative polarity and are therefore able to block
fault currents [Sha16]. The most established FBC is the FB-MMC with its first
application in the German Ultranet project [Rus14, Sta14]. In addition, other
converter configurations have been proposed, which allow the blocking of DC
fault currents, but have reduced operational losses, such as mixed stack MMC
configurations [Jud18] or the Alternative Arm Converter [Cha16, Mer10].
Additionally, due to their capability to insert submodule capacitors with negative
polarity, most FBCs are capable of controlling their DC output current even
during fault situations. Thus, these converters can control their fault current
contribution to values very close to zero [Dor16, Sha16]. A major advantage of
controlling DC fault currents instead of blocking all power electronic devices is
the uninterrupted reactive power controllability of the converter in STATCOM
mode [Dor16]. Several methods were proposed to control DC fault currents using
FBCs. These methods, created primarily for the fault control in point-to-point
systems, are based on the control of DC current and/or the DC voltage at the
DC-PoC [Kar15, Cha16, Lin17, Pet18, Wen19, Ruf19a].
Contrary to fast DC CBs, FBCs can solely limit, control and interrupt the power
flow between the AC and DC systems in case of a fault, but cannot separate a
faulted line in a meshed HVDC network. Nevertheless, fault current blocking or
an active fault-current-zero-control can reduce the currents and voltages in the
DC networks to values close to zero. Hence, FSUs3 designed for the interruption
of residual currents can separate the faulted line from the remaining grid, as
illustrated in Figure 1-4 [Cha16, Dor16, Pet16, Jov18, Ruf18]. After the
3
In the context of HVDC grids, these FSUs are also often called DC high-speed switches (HSS)
[CIG17a, CEN18].
Introduction 9
separation of the faulted line, the healthy part of the network recovers the DC
voltage and resumes normal operation. Hence, the FSUs have to isolate the faulted
line prior to the restoration. The current interruption requirements on FSUs highly
depend on the required fault separation time and the time it takes to create near-
zero current and voltage conditions. To enable a fast fault separation, it might be
necessary to interrupt residual DC currents, which can result from the discharge
of the capacitive grid components. Until now no comprehensive analysis on the
requirements on FSUs and potentials to reduce these requirements is available.
uDC Fault Detection
FSU
FBC iDC
uDC FSU t
iDC iDC
Open FSU
iDC*= 0 uDC*
PI
uDC t
Figure 1-4: DC fault control scheme [Ruf19a]
1.2.3 Multi-Terminal HVDC Network Protection Philosophies
Until today, there is no standard protection strategy for HVDC networks. The
method of fault separation and the resulting protection philosophy is selected
project specifically and depends among others on the number of nodes and the
size of the HVDC network. The key objectives of HVDC grid protection, which
are the same as from AC protection systems, are to ensure human safety and the
safety of the system’s components as well as to ensure a secure operation of the
power system [Akh14, Her16, CEN18, CIG18a].
In HVDC systems the speed of the protection is of special importance.
Particularly due to the limited overcurrent capacity of the power electronic
components used in the converters and DC CBs, faults must be detected and
protective actions must be initiated within a few milliseconds [Buc14, Jov15,
Her16]. Accordingly, the requirements on DC protection algorithms and fault
handling methods differ significantly from existing requirements on AC network
protection [Her16].
The main difference between the protection of future MTDC networks and
today’s point-to-point systems is the need for a fast separation of faulted DC lines.
Especially for DC grids which transmit several gigawatts of power, a long-term
outage of the system can endanger the stability of surrounding AC systems
[Abe17, Zho18]. This is of special importance, if the lost transmission capacity
10 Introduction
of a DC grid towards a country or synchronous zone exceeds the network’s

permitted maximum loss of infeed defined in the national grid codes and causes
a critical frequency deviation [Abe17] – e.g. a power loss of more than 3 GW to
the Continental European or 1.8 GW to Great Britain’s transmission grid
[ENT16b, Nat17].
Even though the requirements for HVDC protection systems to quickly separate
faulted lines have similarities to line protection in AC transmission systems, the
protection strategies can differ significantly from one another. The main
difference is in the definition of the protection zone in which protective actions
are taken to separate a faulted line. A protection zone is defined as a part of a
network with a common response to faults [CEN18]. In AC grids each line has
its own protection zone. Hence, only the CBs at each line end are allowed to
operate to separate the fault. For DC grids the definition of the protection zones
depends on the selected fault separation concept and the size of the network.
In case every line is a single protection zone, as shown in Figure 1-5 (left), fast
DC CBs located at every line end have to separate the faulted line from the
remaining network. The protective actions need to be fast enough to limit the
voltage collapse to the protection zone and ensure that no adjacent device leaves
its normal operation mode [CEN18]. Since solely the corresponding CBs are used
for the fault separation, HB-based fault-feeding converters are typically
associated with such DC CB-based protection strategies.
Protection Zone: DC Line Protection Zone: DC Grid
fast protection & protection separation

DC CB separation zone FFC FSU zone zone FBC
uDC voltage on healthy lines uDC voltage on healthy lines
voltage on faulted line voltage on faulted line

t t
Figure 1-5: Separation of a faulted DC line in case the protection zone is solely the affected
line (left) or the entire grid (right) (based on [CEN18]); Components with protective
actions are in grey
Introduction 11
On the contrary, a protection zone can comprise several lines or even an entire
DC network, as depicted in Figure 1-5 (right). In this case, protective actions limit
the propagation of the fault to the boundaries of the protection zone and FSUs
associated to the faulted line separate the fault. A prominent example of such a
protection system is the HVDC grid protection based on FBCs, which is the focus
of this work. In case of a DC fault, the FBCs stop its propagation to the
surrounding AC networks and support the de-energisation of the protection zone.
The separation and isolation of the faulted line is realised under near-zero voltage
and current conditions by FSUs located at every line end. After the isolation of
the faulted line, the healthy part of the DC network recovers its DC voltage and
resumes normal operation [CEN18, Let19].
According to the extent to which a HVDC grid is de-energized the different
protection strategies can be classified into three groups: Either solely the faulted
line, a part of the network or the entire network are de-energised prior to the
isolation of the faulted line4 [CIG18a].
To assess the effects of different DC protection concepts independently from their
implementation, the impacts of DC contingencies on the secure operation and the
stability of surrounding networks must be evaluated. DC contingencies mainly
influence the stability of AC systems by the amount and the duration of the
resulting power outage as well as the loss of ancillary services provided by the
converters, such as reactive power control [Abe17]. Therefore, HVDC fault
separation concepts can be classified based on the impact of DC contingencies on
each AC-PoC and DC-PoC, which is defined in Table 1-1 [CEN18]. For the
interoperability of existing AC grids and HVDC grids protected by FBCs, whose
transmission capacity towards an AC grid exceeds the maximum permitted loss
of infeed, it must be ensured that the protection complies with the concept of
temporary stop P.
1.2.4 Fault Handling in HVDC Networks with Fault-Blocking Converters
Even though FBC-based protection strategies gained more attention in the recent
past, several issues have not been analysed or discussed in sufficient detail. To
deduce the objectives of this work, an overview of the fault handling process is
presented. Afterwards, the state of research regarding the individual steps of the
protection strategy and its effects on adjacent AC networks are evaluated.
4
These three groups are often characterised as selective, partially selective and non-selective fault
separation concepts [CIG18a]. Since every protection system needs to be selective by definition
[CEN18], this wording is not used within this work.
12 Introduction
Table 1-1: Classification of the impacts of DC contingences on the DC networks AC-PoCs

and DC-PoCs (based on [CEN18])
Fault separation concepts Definition
Continued operation The active (and reactive) power at the PoC exchange must be
controllable at all times. To fulfil this criterion the entire fault
(Transient stop) clearing process, including restoration, must be completed before it
can be measured at the affected PoC, e.g. for an AC-PoC in less
than one cycle of its fundamental frequency. Hence a transient stop
could be considered as continued operation as well.
Temporary stop P A DC fault causes only temporary interruption in the exchange of
solely active or active and reactive power. This interruption must
Temporary stop P&Q be short enough to prevent the transmission system from entering
into alert or emergency state.
Permanent stop P A DC fault causes a long-term interruption in the exchange of
active or active and reactive power. This is either tolerated by the
Permanent stop P&Q affected transmission system or the transmission system is allowed
to enter into alert, emergency or blackout state.
A generic fault clearing process for FBC-based HVDC protection systems is

depicted in Figure 1-6. After a fault occurs in the DC network, the DC voltage
collapses and electromagnetic travelling waves propagate throughout the DC
system. Specific intelligent electronic devices (IEDs), which are designed for the
processing of travelling wave phenomena, detect the fault and initiate the fault
current reduction process of the converters. This can either be a passive, e.g.
converter blocking, or an active fault current reduction process, e.g. the control
of the converter’s DC output current to zero. Simultaneously, the separation
devices associated with the faulted line are selected by a fault localisation logic.
As soon as their opening conditions are fulfilled, the FSUs separate the faulted
part from the healthy part of the DC network. After a successful separation and
the fulfilment of the restart conditions, the DC grid voltage and the power flow
are restored [Dor16, Pet16].
Fault Separation Power Flow Recovery Protection IED
• Detection
• Localisation
Fault Propagation • Trip Fault Control
Fault Detection • Trip FSU opening
Fault Localisation • Initiate Restoration
Fault Current Reduction
Control Unit
Open Fault Separation Unit FSU
• DC Fault Control
Wait for Restart Signal
Grid Restoration FSU
tf tdet tloc tsep trst
Figure 1-6: Generic fault handling process of an FBC-based protection systems [Pet16]
Introduction 13
Fault Detection and Discrimination
Several fast and selective protection algorithms for HVDC networks were
developed and validated in Electro Magnetic Transient Programs (EMTP) and
hardware-in-the-loop (HIL) simulations [Let16, Jah17, CIG18a]. Moreover, some
of these algorithms are already applied in existing HVDC systems. The focus of
research regarding protection algorithms for MTDC networks is, however, on
protection concepts in which every protection zone comprises a single separation
zone, like in DC grids protected by fast DC CBs at every line end (cf. Figure 1-5).
Based on these algorithms, fault detection and discrimination methods for DC
grids based on FBCs can be established. It is shown that based on a combination
of single-ended fault detection and double-ended discrimination methods, a
selective fault discrimination can be established for protection systems based on
FBCs, even if no line inductors are installed in the DC network [Pet16, Lin17,
Jov18]. Since state-of-the-art detection and localisation algorithms are sufficient
for the design of the FBC-based strategy, no further research need has been
identified.
Fault Current Reduction
Within FBC-based HVDC systems, active fault control methods can be used to
limit rising fault currents and reduce them to a value close to zero. Proposed DC
fault control methods are developed for point-to-point systems [Wen16,
Lin17Lin17, Pet18Pet18]. Even though studies for the separation of faulted line
segments in MTDC networks utilizing FBC-based protection systems have
already been presented in the literature, the applied DC fault control methods are
adopted from point-to-point systems [Cha16, Jov18, Wen19] or are not discussed
[Dor16, Pet16, Dan18]. However, fault controls specifically designed for MTDC
networks with FBCs can increase the applicability of such concepts by reducing
the overall fault separation time.
Fault Separation Units
Another unresolved issue is the identification and analysis of appropriate FSUs

for FBC-based protection systems. Since the residual fault current can comprise
a DC component, the application of FSUs with DC current interruption
capabilities might be required [Ruf18, Let19]. After current interruption, the
switches must provide an insulation capability against the full nominal DC
voltage. Most studies apply generic DC-HSSs, which are represented by idealised
14 Introduction
or simplified switching devices5 [Cha16, Pet16, Dan18]. Moreover, the

applicability of full-scale mechanical DC circuit breakers with a reduced energy
absorption capability is proposed [Jov18]. Nevertheless, there is no systematic
method for the identification of requirements on the FSUs. Based on these
requirements, appropriate FSU concepts and suitable switchgear technologies
particularly fitted to the needs of FBC-based protection systems have to be
identified or developed and evaluated in a comprehensive analysis. To reduce the
requirements on the FSUs, the protection strategy and the DC-side fault control
should be aligned with the FSU concept.
System recovery
A key part of the overall MTDC fault handling process of FBC-based protection
systems is the grid restoration and power flow recovery, which commences after
fault separation [Cha16, Dan18]. Especially in HVDC networks in symmetric
monopole configuration, which are characterised by an isolated neutral point,
pole-to-ground faults can cause a persistent imbalance between the affected and
unaffected poles, even after fault clearing, as illustrated in Figure 1-7 [Dan18].
Consequently, the pole voltages must be re-balanced during grid restoration.
While most studies focus on faults in low-impedance grounded networks or pole-
to-pole(-to-ground) faults due to the more critical fault currents, it is essential to
consider both, the effect of high and low-impedance fault current loops in the
design of a HVDC protection strategy.
Pole-to-Ground Fault Pole-to-Pole-to-Ground Fault
Fault inception Fault inception Faulted pole
uDC Fault separation uDC Fault separation Healthy pole
Normal operation
voltage band
DC voltage restoration t t
DC voltage restoration
Pole voltage re-balancing
Figure 1-7: Pole-voltages in case of pole-to-ground and a pole-to-pole-to ground fault in a

DC network in monopole configuration
The imbalance can be eliminated by short-circuiting both DC conductors, which
can be realised by short-circuiting the FBCs or by so-called DC choppers [Cha16,
5
Typically, simplified FSU are represented by an ideal switch with a defined current interruption
capability and opening time.
Introduction 15
Dan18]. Whereas the first method results in a temporary stop in the reactive power
control of the FBC, the second method requires additional equipment. Hence,
appropriate recovery methods need to be established and a comprehensive
analysis on the grid recovery in different grid configurations has to be conducted.
Impact on surrounding AC grids
An HVDC protection system should ensure the secure operation of the power
system, in which it is embedded, during DC contingences. A key aspect for the
evaluation of fault separation concepts is the impact of DC contingencies on
adjacent AC networks, as defined in Table 1-1. A comprehensive analysis of a
fault separation concept cannot be done in a single network, but must consider
various grid structures, e.g. different network (radial or meshed) and circuit (e.g.
high-impedance grounded symmetric monopolar or effectively grounded bipolar
systems) topologies and different transmission line technologies (underground
cables or overhead lines).
Moreover, the impact of fault separation concepts on islanded generation units
connected to a single HVDC converter, like offshore WPPs must be considered.
For today’s WPPs, which are connected to shore via cable-based point-to-point
HVDC links, DC faults result in a disconnection of the generation units. However,
future WPPs connected to shore via MTDC networks must be able to ride through
DC faults similar to AC faults in onshore networks to avoid long-term losses of
the wind power infeed [CIG15]. While the impact of FBC-based protection
systems on islanded generation units has not been studied in previous
contributions, it is crucial to identify DC-FRT requirements on such generation
units. Moreover, the compliance of the protection system with FRT capabilities
of generation units like WPPs has to be demonstrated.
1.3 Objectives and Investigative Approach
The aim of this work is to evaluate the potential and enhance the performance of
a MTDC protection strategy based on FBCs, which enables the fast separation of
faulted lines or zones in multi-terminal HVDC systems. Compared to the use of
fault-feeding converters with fast DC CBs, this protection concept is intended to
reduce the requirements on the DC switchgear, while ensuring a fast restoration
of the DC grid voltage and the active power transmission. Based on the analysis
of the state of knowledge the following challenges are identified as relevant for
the improvement and the detailed analysis of the protection system:
16 Introduction
x MTDC fault control – A fault control concept is required, which is

adjusted to the needs of FBC-based MTDC protection systems, reduces
the overall fault separation time and reduces the requirements on the
FSUs.
x Fault separation units – Technologies suitable for the separation of a
faulted line in FBC-based protection systems need to be identified.
Therefore, requirements on the FSU must be elaborated. Based on these,
the application of existing technologies must be evaluated and new
concepts, which are particularly designed for FBC-based protection
systems, need to be developed.
x Grid restoration – Methods for a fast restoration of the affected (part
of the) DC network after fault separation need to be developed. This
includes the adjustment of the protection strategy to different network
and circuit configurations.
x System Impact – A comprehensive analysis of the protection strategy
is required to assess its applicability to future MTDC systems. Therefore,
the entire process from fault detection to system recovery must be
investigated in the relevant network and circuit configurations.
Moreover, the impact on the AC systems surrounding the DC network,
like AC transmission systems and islanded generation units, like
offshore WPPs, must be identified.
To achieve these objectives, this thesis follows the procedure shown in
Figure 1-8. First, the relevant considerations regarding the converter and fault
controls, switchgear suitable as FSUs, MTDC protection algorithms as well as
DC voltage balancing equipment are analysed. Based on this analysis, the
requirements on MTDC protection systems based on FBCs are deduced. To
develop targeted improvements on the strategy and to enable an objective
evaluation, Key Performance Indicators (KPIs) are elaborated. In addition, the
investigation framework, comprising relevant network scenarios, are identified.
Within this framework, relevant component models, including HVDC converter,
FSU, transmission line and WPP models are developed and the model
parametrisations are presented.
Subsequently, the identified measures for improvements are elaborated and the
FBC-based MTDC protection strategy is defined in detail. The developed strategy
is then evaluated based on EMT simulations in a variety of network and fault
scenarios. For a comprehensive evaluation, different relevant variations are taken
into consideration. This includes different network designs (i.e. radial or meshed),
Introduction 17
different grounding and circuit configurations (i.e. symmetric monopole or bipole

system with DMR).
Finally, the applicability of the FBC-based protection system of future MTDC
networks, including its interoperability with islanded generation units, like WPPs,
and its extensibility, is evaluated and discussed based on the defined KPIs. This
comprises a qualitative comparison of the proposed strategy to fast DC CB-based
strategies.
Goal of the dissertation
Evaluation of the potential and advancement of a fault separation strategy based on fault blocking
converters, which enables a fast separation of faulted lines in multi-terminal HVDC systems
Technological considerations Evaluation criteria

Fault-blocking MTDC protection
converters algorithms Definition of Definition of
functional performance
Switchgear for fault Voltage balancing requirements indicators
separation equipment
Elaboration of a converter control system

adjusted to the needs of fault-blocking converters
Development and enhancement of the protection strategy’s building blocks
DC fault controls Fault separation unit Grid restoration
Evaluation
System impact & Interoperability & Qualitative comparison with
performance evaluation extensibility other strategies
Figure 1-8: Methodology of the thesis

18 Introduction
Physical and Technological Considerations 19
2 Physical and Technological Considerations
The development of an FBC-based protection system and derivation of an adapted

converter control – including the DC fault control concepts – requires an
analytical description of the MMC as well as the deduction of simplified, but
adequate converter models. For that, existing options regarding the detection of
DC faults and localisation of the faulted line within a protection zone need to be
analysed. To identify switchgear suitable for the separation and isolation of
faulted lines within FBC-based protection systems existing switchgear
technologies have to be discussed regarding their applicability and constraints.
Since pole-to-ground-faults can result in a persistent imbalance between the pole
voltages in monopolar DC networks, balancing technologies must be identified
and discussed regarding their applicability in the FBC-based protection strategy.
2.1 Analytical Description of the MMC
The analytical description of the MMC is based on the dynamic system equations
derived from Figure 2-1. The phases of the AC system are denoted with
݅ = {a, b, c} and the variables of the upper and lower phase arms are denoted
k = {u, l}. An expression which is valid for both the upper and lower arms is
denoted with the subscript u,l. On the DC network’s side of the DC-PoC the
positive pole and negative pole are denoted with the subscripts P and N.
Depending on the number of levels, the MMC permits a fine adjustment of the
arm and hence, the AC and DC voltages at the corresponding PoCs. Based on the
switching state S ‫{ א‬-1, 0, 1} of each SM, the voltages of the individual SM
strings (cf. Figure 1-3) are defined in (2.1) and (2.2):
NSM NSM
eu,i = ෍ Su,i,n ∙ uc,u,i.n , (2.1) el,i = ෍ Sl,i,n ∙ uc,l,i.n , (2.2)

n=1 n=1
where NSM is the number of SM per converter arm and uc the SM’s individual
capacitor voltage. Even though the SM string voltages comprise a discrete number
of NSM + 1 levels, eu,i and el,i can be considered continuous variables for the
analytical description of the MMC considering a sufficient number of SMs.
Consequently, the converter’s SM can be treated as controlled voltage sources for
the derivation of the system equations, as shown in Figure 2-1 [Har13, Hah18].
The arm inductors are represented by the arm inductances Larm. The resistances
Rarm represent the ohmic losses of these inductors and the power electronic
components of each arm. Hence, Rarm usually varies depending on the operating
conditions. For the analytical description, however, it is assumed to be constant.
The transformer is represented by the resistances RT and the inductance LT.
Additionally, current limiting inductors, represented by LDC,T and RDC,T are
located between the arms and the DC-PoCs. The DC system is represented by an
equivalent capacitor CDC and a number NL of DC lines (L1..Ln) with the
corresponding currents iP,L,n and iN,L,n.
Energy Exchange Total Converter Energy Exchange

with AC System Energy Balancing with DC System
Total Stored Energy
DC-PoC-P iP,L,1
idc,u
iP,L,2
Converter Internal
Energy Balancing LDC,T RDC,T iP,L,n
eu,a eu,b eu,c
iu,a iu,b iu,c CDC udc,P

uu,i
Rarm Rarm Rarm
AC-PoC Larm Larm Larm
LT RT iac,i
uac,i uac2,i
Rarm Rarm Rarm
Larm Larm Larm
ul,i CDC udc,N
il,a il,b il,c
el,a el,b el,c
iN,L,1
LDC,T RDC,T
iN,L,2
idc,l
DC-PoC-N iN,L,n
Figure 2-1: Equivalent circuit diagram of the MMC for the derivation of the dynamic
equations
The additional nomenclature corresponding to the equivalent circuit diagram
presented in Figure 2-1 is defined as follows:
udc,k & idc,k DC pole voltages and currents (usually idc = idc,u = idc,l)
uk,i & ik,i arm voltages and currents
iac,i AC phase currents
uac,i & uac2,i prim. and sec. side AC voltages (phase-to-ground)
2.1.1 Converter Current Dynamics
For the derivation of the dynamic relationship between the individual currents and
voltages of the MMC, the SM of each arm can be presented by an ideal voltage
source [Hah18]. The dynamic relationship between the AC and DC voltages is
given by Kirchhoff's second law in (2.3), (2.4) and (2.5) [Har13].
didc,P diu,i
udc,u +RDC,T ∙idc,P +LDC,T – eu,i – Rarm ∙ iu,i – Larm = uac,i (2.3)
dt dt
didc,N dil,i
– udc,l –RDC,T ∙idc,N –LDC,T + el,i +Rarm ∙ i୪,i + Larm = uac,i (2.4)
dt dt
diac,i
uac,i – iac,i ∙ RT – LT = uac,i (2.5)
dt
Within the following analytical description, an even DC voltage distribution
between the upper and lower arms (udc,u = udc,l = udc/2) as well as equivalent DC
currents on both poles (idc,u = idc,l = idc) are assumed. Respectively adding (2.3)
and (2.4), subtracting (2.5) and applying Kirchhoff’s law of current
(iac,i = il,i – iu,i), equation (2.6), which describes the AC-side dynamics, is
obtained.
Larm diac,i el,i – eu,i Rarm
൬LT + ൰∙ = – uac,i – ൬RT + ൰ ∙ iac,i (2.6)
2 dt 2 2
= Lac = eac,i (2.7) = Rac

By combining the arm and transformer inductances and resistances to Rac and Lac
and substituting the relationship between the upper and the lower arm voltages
with the AC equivalent voltage eac,i the dynamic behaviour of the AC side can be
expressed with (2.8), which shows that the AC dynamics solely depend on AC
variables [Har13, Hah18].
diac,i
Lac ∙ = eac,i – uac,i – Rac ∙ iac,i (2.8)
dt
Subtracting (2.3) from (2.4) results in (2.9), which is independent from any AC
variables.
d
Larm ൫i + i ൯ = udc,u + udc,l – ൫eu,i + el,i ൯ – Rarm ൫iu,i + il,i ൯ (2.9)
dt u,i l,i
= udc = 2ediff,i
Substituting the sum of the arm currents and arm voltages in (2.9) by the
difference current idiff,i and difference voltage ediff,i, which are defined in (2.10)
and (2.11), results in (2.12).
iu,i + il,i eu,i + el,i
idiff,i = (2.10) ediff,i = (2.11)
2 2
d udc didc ediff,i
Larm idiff,i = + RDC,T ∙idc +LDC,T – – Rarm idiff,i (2.12)
dt 2 dt 2
The subtraction of the DC component from the difference current results in the
so-called circulating current (CC) icc,i, which is caused by inner voltage
differences among the individual phases and defined in (2.13) [Har13]. If the
energy stored in the converter is well distributed across the individual phases, the
DC current components of each phase is a third of the DC current.
Correspondingly, the difference between the DC voltage and difference voltages
can be expressed by the voltage ecc,i, defined in (2.14).
idc
icc,i = idiff,i – idc,i ≈ idiff,i – (2.13)
3
edc
ecc,i = ediff,i – (2.14)
2
where edc is the equivalent DC voltage generated by converter’s SM strings.

Hence, (2.12) can be separated into its CC and DC components resulting in (2.15)
and (2.16) respectively.
d
2Larm
i = – ecc,i – 2Rarm icc,i (2.15)
dt cc,i
2 d 2
൬2LDC,T + Larm ൰ idc = udc – edc – ൬2RDC,T + Rarm ൰ idc (2.16)
3 dt 3
= Ldc = Rdc
The equations (2.8), (2.16) and (2.15) result in three independent models – AC,
CC and DC, which are given in αβ0 stationary reference frame in (2.17) – (2.19)
and illustrated in Figure 2-2.
d
Lac i = – Rac ∙ iac,αβ + eac,αβ – uac,αβ (2.17)
dt ac,αβ
d
2Larm icc,αβ = – 2Rarm icc,αβ – ecc,αβ (2.18)
dt
d
Ldc i = – Rdc idc + udc – edc (2.19)
dt dc
AC Model CC Model DC Model
uac,i eac,i idc

ecc,i
icc,i edc
2Rarm Rdc Udc

2Larm Ldc
Lac Rac iac,i
Figure 2-2: Schematic representation of the three MMC models

Based on (2.7), (2.11) and (2.14), the sum of the inserted SM voltages can be
expressed with (2.20) and (2.21) [Ant09].
edc edc
eu,i = – eac,i + ecc,i (2.20) el,i = + eac,i + ecc,i (2.21)
2 2
2.1.2 Converter Energy Dynamics
For the derivation of the three converter current models the SM string of each arm
has been regarded as an ideal voltage source neglecting the energy stored within
the SM capacitors and the corresponding SM voltages. This however, is only true
if the capacitor voltages of the SMs are within their operation limits. The energy
management is therefore essential for the operation of the converter and forms the
link between the individual current models. The total energy stored in each
converter arm Ei,k is on the one hand defined by the integral of current and voltage
and on the other hand by the energy stored within each SM, as shown in (2.22)
N
1
Ei,k = න ei,k ∙ ii,k dt , (2.22) Ei,k = ෍ CSM ∙ u2c,i,k,n , (2.23)
2
n=1
where CSM is the SM capacitance and uc,i,k,n are the individual capacitor voltages.
As long as the energy stored within each arm is well distributed over the
capacitors, its energy can be expressed by (2.24).
1
∙ NSM ∙ CSM ∙ uത 2c,i,k
Ei,k = (2.24)
2
Subtracting (2.22) from (2.24) results in (2.25), which describes the dynamic
relation between the average capacitor voltage and the arm currents and voltages.
2
uത c,i,k = ඨ න ei,k ∙ ii,k dt (2.25)
NSM ∙ CSM
The energy stored within the converter and its SM depends on the power
difference between the AC and DC side and the losses of the MMC, as shown in
(2.26) [Sam16, Hah18]. Again, assuming an ideal distribution of the stored energy
across all arms and submodules, the energy balance is directly linked to the
average capacitor voltage as shown in (2.27).
EMMC = න൫pac – pdc – ploss ൯dt (2.26)
1
uത c = ඨ න൫pac – pdc – ploss ൯dt (2.27)
3 ∙ N ∙ CSM
For a stable operation of the converter, not only the total stored energy EMMC but
also the energy stored within each arm must be constant over time. According to
(2.22), the rate of change of the stored energy within each arm corresponds to the
power flow through the converter arms. Hence, (2.28) and (2.29) form the central
equations for the deduction of the current components relevant for the converter’s
internal energy balancing [Ant09, Sam16, Hah18].
iac,i udc
pu,i = iu,i ∙ eu,i = ൬idiff,i + ൰∙ቀ – eac,i ቁ (2.28)
2 2
iac,i udc
pl,i = il,i ∙ el,i = ൬idiff,i – ൰∙ቀ + eac,i ቁ (2.29)
2 2
While the sum EΣ,i of the energy stored within the upper and lower arms –
typically called horizontal balancing – describes the energy balance between the
phases, their difference EΔ,i – usually referred as vertical balancing – describes
the balancing between the upper and the lower arms. Hence, for an even
distribution of the MMC’s stored energy, the average of the differentiations of
(2.30) and (2.31) must be zero over time.
pu,i + pl,i udc 1

pΣ,i = = idiff,i ∙ – iac,i ∙ eac,i (2.30)
2 2 2
udc
pΔ,i = pu,i – pl,i = –2idiff,i ∙ eac,i + iac,i ∙ (2.31)
2
For the analysis of the impact of the different current components on the energy
balance of the MMC, (2.30) and (2.31) are transformed from natural abc to fixed
αβ0 coordinates by applying Clark’s transformation [Sha16]. Both, the sum and
the difference power comprise direct and sinusoidal components. Since purely
sinusoidal components have no impact on the long-term energy balancing, they
are not relevant for the following analysis [Kol14, Leo17]. The resulting average
power in αβ0 reference frame is given by (2.32) - (2.34). The total energy
balancing of the converter is expressed by the zero component, which depends,
as already indicated in (2.26), on the power exchange between the AC and the DC
side. The energy transfer between the phases arises from individual DC current
components of the phases [Kol14, Leo17, Hah18].
udc udc
pത Σ,α = i = i (2.32)
2 diff,α,DC 2 dc,α
udc udc
pത Σ,β = i = i (2.33)
2 diff,β,DC 2 dc,β
udc 1 p p
pത Σ,0 = idiff,0 + ൫uac,α iac,α +uac,β iac,β ൯ = – dc + ac (2.34)
2 4 6 6
The resulting average αβ0 difference components are presented in (2.35), (2.37)
and (2.39). Since the voltages of these terms only comprise AC components
oscillating with the fundamental frequency fN, the difference power can be
controlled via a three-phase current with the same rotating angle as the AC grid
voltage θN = 2πfNt. A transformation into positive and negative sequence
components (using the rotational matrix R(θN) and R-1(θN)) reveals that the
positive sequence component of the difference current only impacts the energy
difference between the sum of the upper and the sum of the lower arms, while the
negative sequence can be used to control the energy differences within the
individual phases (cf. (2.36), (2.38) and (2.40)) [Kol14, Hah18].
–
pത Δ,α = – uac,α idiff,α + uac,β idiff,β (2.35) pത Δ,α = – uො ac መidiff,α (2.36)
–
pത Δ,β = uac,α idiff,β + uac,β idiff,α (2.37) pത Δ,β = – uො ac መidiff,β (2.38)
+
pത Δ,0 = – uac,α idiff,α – uac,β idiff,β (2.39) pത Δ,0 = – uො ac መidiff,α (2.40)
Consequently, the total, the horizontal and the vertical energy balancing can be
controlled via independent current components. Moreover, the equations (2.26)
and (2.34) show that the total converter energy can be controlled either via the
AC or the DC side.
2.1.3 DC Voltage Dynamics
To simplify the DC dynamics, the DC network can be represented by a

concentrated capacitor, as shown in Figure 2-1 [Sam16, Hah18]. Accordingly, the
DC dynamics can be described by (2.41).
NL NL
dudc Pdc
Cdc =idc – ෍ idc,L,y = – ෍ idc,L,y , (2.41)
dt udc
y=1 y=1
where NL is the number of DC lines connected to the DC-PoC of the converter. A

common operation mode of VSCs is to control the DC voltage via the active
power at the AC-PoC [Hah18]. By Inserting (2.27) into (2.41), it is shown in
(2.42) that the DC dynamics however not only depend on the active power, but
also on the change of the stored energy within the converter.
NL
dudc Pac duത 2c
Cdc = – 3NCSM – ploss – ෍ idc,L,y (2.42)
dt udc dt
y=1
2.2 Protection Algorithms for MTDC Networks
Fault detection and localisation algorithms for P2P and MTDC networks have
been extensively studied [Let16, CIG18a] and are partially already applied in
existing HVDC systems [Let19]. The focus regarding the development of
protection algorithms for MTDC networks, however, is on protection schemes in
which every protection zone in a DC network comprises a single separation zone,
like in DC networks protected by fast DC CBs at every line end.
Within the FBC-based protection system studied in this work, a protection zone
typically comprises several fault separation zones. Hence, the applicability of
existing protection algorithms on the FBC-based protection system is discussed.
Contrary to the fault discrimination in DC networks based on protection zones
comprising of a single separation zone, e.g. in case of a protection system based

on fast DC CBs at every line end, the fault discrimination in protection systems
comprising several separation zones, like the FBC-based protection system
studied within this work, can be separated into two main categories [Ruf19a]:
x Fault detection: As for any protection system, every fault must be
detected by IEDs associated with the protection zone. The detection
must initiate fault handling actions, which ensure both human and
component safety and prevent protection actions from surrounding
protection zones [CEN18, CIG18a].
x Fault localisation: To separate a fault from the remaining transmission
system, the faulted segment, which is a part of the affected protection
zone, e.g. the faulted line, must be identified.
Moreover, protection algorithms can be categorised into single-ended and
double-ended methods. While single-ended methods rely solely on local
measurements, double-ended methods utilise measurements or information
extracted from a different location in the system [Jah17, CIG18a].
To identify a suitable fault discrimination concept for the FBC-based protection
strategy, functional requirements are summarised and relevant algorithms are
analysed.
2.2.1 Fault Detection
Among others, the functional requirements upon fault detection algorithms are
[CEN18, CIG18a]:
x Selectivity: The algorithm must detect all faults within its protection
zone. Moreover, the detection must not trip during non-fault situations
and external faults.
x Speed: The algorithm must be fast enough to prevent damage to any
equipment and ensure human safety. Additionally, it shall initiate
measures to avoid a voltage collapse of any neighbouring protection
zone.
x Reliability: To ensure the systems safety, HVDC protection systems are
associated with high requirements on reliability. Hence, a loss of
communication must not result in an undetected fault.
To fulfil the requirement on speed and reliability, only single-ended,
communication-less algorithms are typically considered for the fault detection in
HVDC systems [CIG18a]. If the DC network only comprises a single protection

zone these requirements could be fulfilled using a simple undervoltage protection.
However, purely undervoltage based approaches cannot fulfil the requirement on
selectivity in HVDC networks composed of multiple protection zones. Most
single-ended fault discrimination methods analyse the rate-of-change-of-voltage
(ROCOV) or current (ROCOC) changes at a particular point in the DC network.
In order to enable a discrimination between internal and external faults, the
protection zone boundaries require an inductive termination [Let16, CIG18a].
To account for the direction of the fault, which is required to discriminate between
different protection zones, a directional derivative method is typically integrated
into the fault detection. An example of a directional derivative algorithm is given
in (2.43) [CIG18a, Let18].
du di
duthr < – Zc , (2.43)
dt dt
where Zc is the characteristic impedance of the transmission line and duthr is the
threshold of the derivate detection algorithm.
2.2.2 Fault Localisation
After the detection of the faulted zone, the zone which is to be separated from the
remaining network must be localised6. Similar to the fault detection, the
discrimination between different separation zones can be realised using
single-ended algorithms in combination with an inductive termination at the end
of each separation zone, e.g. at each line end.
Nevertheless, both human and component safety are already provided by the
protection scheme of the affected protection zone, which is tripped via the fault
detection. Hence, FBC-based protection strategies allow to reduce the
requirements on speed and reliability on the fault localisation compared to the
fault detection, allowing the application of double-ended, communication-based
methods, like a differential line current protection. Since a differential line current
protection detects a fault by the comparison of the current quantities measured at
each end of the corresponding transmission line7, double-ended fault localisation
systems do not require the inductive termination of the line ends and thereby
6
In case the protection zone only comprises a single separation zone, the fault localisation is obsolete,
e.g. for a DC network protection system unitising fast DC-CB at every line end (cf. Figure 1-5).
7
For the comparison of the currents measured at each line end, the propagation delay caused by the
traveling wave time and the communication system has to be taken into account.
reduce the losses and space requirements of the protection scheme [Jov18]. In
addition, the differentiation between line and busbar faults is typically realised
using a busbar current differential protection [CIG18a].
2.3 Circuit Breakers and Switchgear
The uninterrupted controllability of the DC current and voltage of FBCs, even

during DC fault situations, enables the application of switchgear which is
typically not foreseen for HVDC fault current interruption [Jov18, Ruf19a]. For
the identification of suitable FSU, existing switchgear technologies are analysed
regarding their applicability to the protection strategy. For the analysis of the
work, these switchgear technologies are separated into three categories:
x DC CBs: Circuit breakers with DC current interruption capabilities
x AC CBs: Circuit breakers without DC current interruption capabilities
x DS: Disconnecting switches without AC and DC current interruption
capabilities
2.3.1 HVDC Circuit Breakers
The proposed DC CB technologies range from concepts purely based on power

electronic switches (solid-state CB) [San14] to mechanical CBs based on resonant
branches [Tok17], including hybrid schemes comprising both mechanical and
semiconductor switches [Häf11], as shown in Figure 2-3. Although only a small
number of HVDC circuit breakers are already in operation in HVDC networks,
prototypes of the CB technologies have been tested and are expected to perform
according to their specifications [Let19, Jov19].
Solid-State DC CB Hybrid DC CB Mechanical DC CB
Nominal current path Current interruption path Energy absorption path
Figure 2-3: Schematic representation of a solid-state, a hybrid and a mechanical (active

current injection) DC CB
Despite the vast number of proposed concepts, the majority of the high voltage
DC CBs comprise common building blocks independent of the CB type and
follow a similar operation logic, which is illustrated in Figure 2-4 [CIG17a]:
1. Tripping: The protection IED detects the fault and sends the tripping
order to the corresponding DC CB.
2. Current commutation: After receiving the tripping order, the breaker
commutates the current from the nominal to the energy absorption path,
which typically consists of a surge arrester (SA) bank. During the
commutation phase, the voltage across the CB rises to the peak transient
interruption voltage (TIV). Contrary to the transient recovery voltage
(TRV) associated with AC CBs, the TIV is created by the DC CB itself,
while the TRV is a result of the imposed system voltage after current
interruption. Since the TIV acts as a counter voltage to the driving
electromagnetic force (EMF) of the fault current path, the current starts
to decrease. At this point in time, the CB separates the fault and the
system, even though the fault current is not yet interrupted.
3. Current suppression: The counter voltage generated by the SA
suppresses the fault current to a residual current level. To suppress the
fault current, the SA is typically design to provide a counter voltage of
USA,r = 1.5 UDC,n [CIG17a].
4. Current interruption: Finally, a residual current breaker, which
typically is a fast mechanical CB, interrupts the leakage current of the
SA and ensures a galvanic isolation of the fault and the remaining
system.
uCB
iDC
LCB
uemf
t
1 2 3 4
Figure 2-4: Schematic representation of the DC fault current interruption process [CIG17a]
Because of the absence of natural current zero crossings (CZC), a synthetic zero
crossing must be generated to commutate the current from the main to the energy
absorption path. The current commutation can be either achieved by generating a
counter voltage in the commutation path, as it is done in solid-state and hybrid
DC CBs, or by the injection of an external current, as it is done in mechanical DC

CBs like active and passive resonant CBs [CIG17a].
To limit the rate-of-rise of the fault current and thereby the maximum interruption
current Iint, DC CBs are typically implemented into DC systems in combination
with fault current limiting reactors8. Depending on the CB’s opening speed and
current interruption limits, these high-energy air-cored inductors can range from
a few ten up to a few hundred millihenry and hence add to the losses as well as
the weight and volume associated with the protection scheme [CIG17a]. In case
DC CBs are used to interrupt residual DC currents, fault current limiting reactors
might not be required, since the CBs only interrupt the fault current after it is
reduced to near-zero conditions [Jov18, Ruf19a].
Another key design factor of DC CBs, which contributes to the costs and the
footprint of the CB, is the energy absorption capability, which can be in the order
of tens of megajoules for full-size DC CBs [CIG17a]. The energy dissipation in
the CB’s SA during a current interruption process is given in (2.44) [CIG17a].
Δtc
ESA = න uSA ൫iSA ሺtሻ൯ ∙ iSA ሺtሻ dtǡ (2.44)
0
where Δtc is the current suppression time. Assuming a constant SA voltage during
the interruption process and the TIV being 1.5 times larger than the rated DC
voltage, the current suppression time can be simplified to (2.45) [Jov18]:
Iint ∙ LCB 2 ∙ Iint ∙ LCB
Δtc ≈ = ǡ (2.45)
USA,TIV – UDC UDC
where Iint is the interruption current at the beginning of the suppression phase.
Moreover, if this difference between the TIV and the EMF does not decrease
during the interruption process, (2.45) defines the maximum current suppression
time for a given combination of the path inductance LCB and the current peak Iint.
Again, assuming a constant difference between the TIV and the EMF, the energy
absorption requirement of a DC CB’s SA can be described solely by the
maximum path inductance LCB and the maximum current Iint at the beginning of
the suppression phase, as shown in (2.46) [Jov18]:
Δtc
Iint ∙ USA,r 3 2
ESA,max = න uSA ሺtሻ ∙ iSA ሺtሻ dt ≈ ∙ Δtc,max = ∙ LCB ∙ Iint (2.46)
0 2 2
8
The room required for two 75 mH reactors in a 900 MW / ±320 kV MMC is approximately
25 m × 15 m × 10m [Sha16]
2.3.2 Conventional AC Circuit Breakers
Contrary to HVDC CBs, which are a relatively young switchgear technology,

CBs for HVAC applications are standardised components which are widely used
in power grids over decades and produced in high volumes. Moreover, the weight
and volume associated with AC CB is relatively small compared to most DC CB
concepts.
Therefore, if AC CBs can guarantee a fast interruption of residual fault currents,
they might be an attractive FSU option in FBC-based protection systems. Since
the current interruption conditions can, however, differ from the interruption
conditions in AC systems, the current interruption processes of the most common
AC CB technologies, i.e. vacuum and SF6-based gas CBs, must be analysed and
requirements need to be deduced.
SF6-Circuit Breakers
Sulphur hexafluoride (SF6) based CBs are widely used in high-voltage systems
due to the outstanding dielectric properties of SF6. The CBs are based on the
principle of arc quenching by cooling the arc with an SF6 gas flow. Close to
(natural) current zero crossing, little energy is injected into the arc and its channel
reduces to a thin plasma thread, which quenches at the CZC. The subsequently
occurring TRV stresses the gas in the switching gap, which causes a post-arc
current through the still hot and conductive gas channel. During this post arc
phase the power fed into the plasma must be smaller than the cooling power of
the gas flow to prevent a thermal break-down. During the subsequent dielectric
phase, the TRV across the switching gap increases. Hence, the dielectric
withstand capability of the gas must recover fast enough to prevent a dielectric
break-down of the CB [Sme15].
The TRV occurring after current interruption can be increased by an arc extinction
prior to the natural CZC. This so-called current chopping causes the remaining
magnetic energy stored in the network’s inductances to discharge via its stray
capacitances. The current chopping value highly depends on the type of CB and,
for gas CBs, the parallel capacitance of the switching gap. The maximum current
chopping of a specific SF6-CB is typically in the range of ich,SF6 = 4…20 A
(assuming a parallel capacitance in the range of Cp = 10 nF) [Sme15].
In case an AC CB shall be applied as FSU in DC grids without additional
circuitries (like a resonant branch and a surge arrester), it has to interrupt residual
fault currents, which might comprise a DC component. This imposes the
additional requirement on the CB to create a counter voltage. The counter voltage
of an AC CB is the voltage drop across the switching gap – the arc voltage uarc,
which is the product of the plasma resistance and the corresponding current
[Sme15]. Since the arc voltage depends of the CB’s cooling power, it depends on
the type and the design of the CB. While self-blast CBs require a fault current to
build up pressure and cool the arc, puffer CBs mainly rely on the mechanical
actuators to build-up the pressure for cooling. The puffer type is also usually used
for resonant DC CBs based on SF6-CBs [Nak01, CIG17a]. For small DC currents,
arc voltages in the range of uarc = 8 kV have been measured in SF6-based puffer
CBs used in metallic return transfer breakers [Nak01].
For switching applications with rated (AC-RMS) voltages up to Ur = 245 kV the
CB typically comprises a single switching chamber, while for applications with
higher rated voltages several switching chambers are usually connected in series
[Sme15].
Vacuum Circuit Breakers (VCB)
While arcs in SF6-CBs are based on a gas plasma occurring during the switching
process, arcs in vacuum chambers (typically with p ≤ 10-5 mbar) are based on
metal vapor. After a CZC, the metal vapor arc quickly diffuses and its charge
carriers are drawn to the metal shields of the chamber, enabling a fast dielectric
recovery of the switching gap [Sme15]. The arc voltage of VCBs is significantly
lower than the arc voltage of SF6-CBs (in the order of a few ten volts) [Sme15].
The quenching capability of a VCB depends on the characteristics of the specific
CB. Its thermal breaking capability is typically defined by the maximum
acceptable rate-of-change-of-current (ROCOC) during a CZC, which usually is
in the range of diCZC,crit/dt = 150..1000 A/μs [Hel96]. In practice, VCBs also
experience current interruptions prior to corresponding natural CZCs. While
chopping values in VCBs used to be relatively high, the values in modern VCBs
are similar to those of SF6-CBs (ich,VCB = 2..10 A) [Sme15].
While standard VCBs are available with a nominal voltage of Ur,VCB = 72.5kV,
first VCBs with nominal voltages of up to Ur,VCB = 145 kV have been proposed
[Sme15, Hei18b].
Dielectric Withstand Capability
All CBs in HVAC applications must be able to withstand TRVs within the
standardised IEC TRV envelopes, illustrated in Figure 2-5 [IEC18]. Since there
is no such standard for DC applications, the dielectric withstand capabilities of
AC CBs in the non-standard condition of a residual fault current interruption in
DC systems, the existing AC IEC TRV envelopes are used as a first indicator for
a successful current interruption.
u u
uc
uc
u1
t3 t t1 t2 t
Figure 2-5: Standardised IEC TRV envelopes for CBs with a rated voltage Um < 100 kV
(left) and for CBs with a rated voltage Um ≥ 100 kV (right) [IEC18]
2.3.3 Disconnecting Switches
Disconnecting switches are used in HVDC applications to disconnect a circuit or

equipment as well as in HVDC switchgear to interrupt small leakage currents and
isolate two separated circuits. While standard disconnectors operate in the range
of a few seconds, technologies based on electromagnetic Thompson actuators,
like the Ultra-Fast Disconnector (UFD) can be applied if a rapid isolation of two
circuits is required [Ska13, CIG17a]. Prototypes of this switch are able to isolate
a DC voltage of uUFD = 320 kV within approximately topen = 2 ms [Ska13]. As
with standard disconnectors, the safe current interruption capability of UFDs is
very limited, i.e. iUFD,int < 1 A [Ska13].
2.4 Pole Voltage Balancing in HVDC Systems
Due to the isolated neutral point of monopolar DC networks, a single pole-to-

ground (PG) fault can result in a persistent shift of the neutral point by the nominal
voltage of the effected pole and hence a persistent overvoltage on the unaffected
pole of up to twice the nominal voltage, as shown in Figure 2-6 [Wan19].
In case of a PG fault in an HVDC system protected by fast DC CBs at every line
end, the pole voltage starts to shift directly after fault inception. Once the DC CBs
separate the fault, the pole voltage imbalance decays due to a compensating
current flowing via the high-impedance grounding of the DC network [Wan19].
Even though, FBCs can quickly suppress their fault current contribution after fault
inception and control the DC pole-to-pole voltage during DC faults, the de-
energisation of a single pole results in an imbalance of the pole voltage prior to
the grid voltage restoration. Once the fault is separated both poles are charged
symmetrically, resulting an overvoltage on the healthy pole [Cha16, Dan17].
Analogues to the DC CB case this pole voltage imbalance slowly decays – over
several sounds to minutes – due to compensating current flowing via the high-
impedance grounding path.
Protection based on fast DC CBs Protection based on FBCs
Fault inception Fault inception Faulted pole

uDC Fault separation Fault separation Healthy pole
uDC Normal operation
voltage band
t t
Pole voltage re-balancing Pole voltage re-balancing
Figure 2-6: Schematic representation of the DC pole voltage profiles during a pole-to-
ground fault in HVDC systems protected by fast DC CBs (left) and FBCs (right)
Consequently, pole re-balancing is a necessary step to protect the grid’s
components against temporary overvoltages and to restore the system to normal
operation. There are two main counter measures to these overvoltages: dynamic
braking systems (DBS) – also know as DC choppers – or AC-side grounding
schemes permitting zero-sequence currents, as illustrated in Figure 2-7 [Sha16,
Wan19].
DC-PoC
SM1 SM1 SM1

SM2 SM2 SM2
SMn SMn SMn TDBS,P (a) Dynamic
AC-PoC
RDBS Braking System
LZ RDBS
High Impedance SM1 SM1 SM1
RZ SM2 SM2 SM2 TDBS,N
Star Point Reactor
SMn SMn SMn
(b) Zig-Zag
Transformer
Figure 2-7: DBS circuit with lumped braking resistors [Wan19]

DBS are typically installed in DC systems connecting offshore wind farms to
enable a fault-ride-through (FRT) of the HVDC system and the wind turbines
during faults in the onshore AC transmission grid [CIG14, Sha16]. Moreover,
they can be applied to limit and thereby re-balance the DC voltage pole voltages
in both protection systems [Cha16, Wan19].
Alternatively, to the application of DBSs, DC pole re-balancing can be realised

via a low-impedance zero-sequence current path on the AC side of the converter.
Typical schemes providing a zero-sequence grounding are star point reactors,
zig-zag grounding transformers or the application of Yy-type converter
transformers with a tertiary-delta winding [Wan19]. In contrast to DBSs, which
do not consume power while they are turned off, most zero-sequence grounding
schemes consume apparent power in case they comprise a residual positive
sequence current path. Due to its high positive sequence impedance, the zig-zag
grounding transformer provides a good trade-off between power consumption and
low zero-sequence impedance [Wan19].
An option which can only be applied in DC grids comprising FBCs is to discharge
the healthy pole through the fault location by temporarily bypass all the
converter’s submodules. Therefore, both poles can be short-circuited via the arm
inductors of the converter. To limit the converter currents, the converter switches
between bypass and blocking mode similar to a DBS [Dan17]. The major
advantage of this method is that no additional equipment is required to facilitate
a balanced voltage restoration. The uncontrolled operation of the FBC, however,
results in a temporary stop in the reactive power support to the AC system.
Requirements and Evaluation Criteria 37
3 Requirements and Evaluation Criteria
Both for the development and for the evaluation of the protection strategy it is
essential to have a clear definition of the requirements and the evaluation
procedure. Therefore, functional requirements must be identified and suitable
performance indicators need to be defined.
3.1 Functional Requirements
Beside the general requirements on any grid protection system, to ensure human
and component safety as well as a stable operation of the overall power system,
the protection system has to comply to various functional requirements to allow
the integration of HVDC networks protected by FBCs into existing AC
transmission systems and to enable the interoperability with existing equipment.
AC Transmission System Compliance
To enable the integration of HVDC networks into the existing AC transmission

infrastructure, they need to comply with the fault separation concept Temporary
Stop P at all AC-PoCs to prevent the AC system from entering into alert state
(cf. Table 1-1) [CEN18]. Since the protection strategy first de-energises the
protection zone to create near-zero current and voltage conditions for the fault
separation, the healthy part of the protection zone, which can be the entire HVDC
network, must be restored within the Critical Time to Return to Operation of the
surrounding AC transmission system(s) [CEN18]. Moreover, the permanent loss
of transmission capacity must comply with the permissible loss-of-infeed of the
corresponding synchronous zone. To avoid impermissible frequency deviations,
the time of the temporary stop as well as the amount of lost power has to be
limited. These values will, however, depend on several impact factors, like the
current interruption capabilities of the FSUs as well as the network and circuit
topology. The tolerable amount and the maximum duration of a temporary power
loss depends on the strength of the connected AC system and might also depend
on the specific connection point. Contrary to the maximum permissible loss-of-
infeed, a maximum short-time loss-of-infeed or similar is not quantified in
standards or grid codes yet [PRO17b, PRO19].
Since this work does not comprise stability investigations of specific AC

transmission grids, generic but quantifiable performance indicators are required
which allow the high-level evaluation of the interoperability of the protection
system with specific AC transmission systems.
As FBCs can continuously ride through DC faults, without an interruption of their
controllability, a Temporary Stop Q shall be avoided at all PoCs at any time.
Selectivity and Extensibility
In FBC-based protection systems, the faulted zone, which is to be separated,

typically differs from the protection zone, which is defined in HVDC grids as
“physical part of a HVDC Grid System with a common response to DC faults”, as
illustrated in Figure 3-1 [CEN18]. In case of a DC fault, the faulted line or zone
shall be separated fast and selectively, while the healthy part of the protection
zone shall quickly resume normal operation. If a temporary stop of the entire DC
grid is not tolerable for the surrounding AC systems, it must be possible to
separate the DC grid into several protection zones, each complying to the
definition of the Temporary Stop P [CEN18]. Hence, it needs to be ensured that
a DC fault within one protection zone does not cause protective actions in
adjacent protections zone. Accordingly, the FBCs must be able to take protective
actions and support the fault separation within their protection zone and must be
able to ride through faults of adjacent protection zones.
DC Grid Voltage Profiles
u Separation Zone
t
u Protection Zone
Healthy Grid
t
u Healthy Grid
Separation zone
Protection action associated with the separation zone t
Protection zone
Protection action associated with the protection zone Normal Operation Voltage
Figure 3-1: Impact of a DC fault on the HVDC grid voltage in the separation zone, the
affected protection zone and an adjacent protection zone
Interoperability
To allow a wide range of applications for protection strategy, it must comply with
different network and circuit configurations, i.e. radial and meshed MTDC system
in symmetric monopole and bipole configuration.
Since an important application for MTDC systems is the integration of remote
RES, i.e. offshore WPPs or PV farms, an additional requirement to the FBC-based
MTDC protection systems is the interoperability with islanded generation units
solely connected to one HVDC converter of a MTDC network. In case of a
temporary discharge of the HVDC network caused by a DC fault, it must be
ensured that the generation units can ride through the DC fault and resume normal
operation after fault separation.
Component Stresses
All components of the DC grid must be able to withstand the potential stresses
during the fault separation and grid restoration process. This includes HVDC
converters, the protection equipment, like the applied FSUs, and the transmission
line. To ensure that the converters are not stressed beyond their limits, feasible
protection limits have to be defined and the protection strategy as well as the
converter control has to comply with these limits.
Moreover, it is essential for the evaluation of the protection system to assess the
stresses imposed on the FSUs and develop protection strategies which are
adjusted to their needs and ensure their safe operation, i.e. by defining safe
opening criteria.
As cables based on cross-linked polyethylene (XLPE) insulation materials are
typically used for VSC-HVDC applications the protection system must not
impose impermissible stresses on such cable insulation. At the present, the
electrical field stresses caused by voltage transient with reversed polarity are
considered critical for XLPE insulations of cables and their accessories. To
account for these stresses, XLPE cables are typically tested according to CIGRE
recommendations, which have been adopted in the IEC standard 62895 (for rated
voltages up to Udc,r = 320 kV) [CIG12, IEC17]. With respect to voltages
transients and polarity reversals, the specifications include superimposed opposite
polarity switching and lightning impulse tests. As the protection strategy needs to
comply with state-of-the-art transmission line systems, it shall comply with the
defined test requirements.
3.2 Identification of Key Performance Indicators
To assess an HVDC grid protection strategy, quantifiable values reflecting its

performance need to be defined. These KPIs shall enable the evaluation and
comparison of a wide set of MTDC protection strategies. Moreover, the KPIs
shall reflect the impact of a protection strategy on the HVDC network operation
and the stress of its components as well as its impact on surrounding AC
transmission networks and islanded generation units, like offshore WPPs.
HVDC Grid Constraints
As shown before, the fault clearing process in DC networks can be separated into
two phases [CEN18]:
1. The duration between fault inception and the separation of the faulted
zone from the healthy HVDC network.
2. The duration between fault separation and recovery of the HVDC
network to normal operation conditions.
The operational status of an HVDC grid is associated with the DC grid voltage,
as illustrated in Figure 3-2 (left) [CIG16]. Consequently, a protection zone, which
was affected by a DC fault, is considered as recovered once the DC voltages (pole-
to-ground) within the entire zone resume within its minimum and maximum
operating voltage UDC,min and UDC,max, as illustrated in Figure 3-2 (right) [CEN18,
CIG18a].
Temporary HVDC Grid Voltage Profile Voltage Profile at a DC node
u* u* Fault Voltage
UDC,max inception restoration
UDC,max
UDC,min UDC,min
t t
Transients Recovery Normal Operation Δ‫ݐ‬sep Δ‫ݐ‬U,90 Δ‫ݐ‬U,rst

*: Pole-to-Ground Voltage
Figure 3-2: Temporary DC voltage profile for HVDC grids (left) [CEN18, CIG18a] and
DC voltage restoration process within a protection zone based on FBCs (right) [CEN18]
At the time of publication of this work, there are no standards regarding the
voltage limits in DC systems [PRO19, Dan20]. In AC systems the bus voltage is
often considered as restored once it has reached 90 % of the pre-fault voltage
[ENT16a, Dan20]. Thus, a ± 10 % voltage band is applied to characterise the
voltage restoration of a zone within DC networks [Ber20, Dan20].
Consequently, the following KPIs are used for the evaluation of the impact of a
protection strategy on the DC grid:
Δ‫ݐ‬sep: Fault separation time – Time until all relevant FSUs are opened and
the faulted line or zone is separated (cf. Figure 3-1).
Δ‫ݐ‬U,rst: Voltage restoration time – Time until the DC voltage is restored
within its normal operation limits at all DC nodes (here within ± 10 %
of the nominal DC voltage).
Δ‫ݐ‬U,90: Voltage restoration time to 90 % – Time until the DC voltage is
restored to the minimum DC operation voltage for the first time after
fault separation, i.e. to 90 % of the nominal DC voltage. While ΔtU,rst
strongly depends on the converter controls and the coordination
between the converters in the grid, e.g. due to DC voltage droop
settings, ΔtU,90 mainly depends on the line capacitance of the total
protection zone and the converter ratings [Cha16].
AC Grid Constraints
The maximum loss-of-infeed constraints, which are defined in the national grid
codes, specify the permanent loss-of-infeed. A fault in an HVDC grid system
might however cause a short-term but energy imbalance in AC systems connected
to the DC grid, which is higher than the tolerable permanent loss-of-infeed. This
temporary energy imbalance can have a severe influence on the stability,
especially on the transient and the frequency stability, of AC transmission systems
[Abe17, Gon18, Zho18]. However, it is not the objective of this work to analyse
the impact of short-term power imbalances on different AC transmission systems.
Hence, simple and generic but relevant KPIs are required to assess the influence
on DC contingencies to AC transmission systems.
Similar to the voltage restoration, the active power can be regarded as restored at
a PoC, if the instantaneous active power settles within a predefined tolerance band
around the post-fault steady-state active power9, as depicted in Figure 3-3 (left).
As there is no standard defining the active power restoration in HVDC networks
9
Before any re-dispatch actions are executed.
at the time of publication of this work [PRO19, Dan20], a tolerance band of

± 10 % of the rated active power of a converter is used for the evaluation of the
power restoration time [Ber20, Dan20]. Since a fault in a meshed DC network
can be separated from the remaining system without a long-term loss of a
converter, it is possible to re-establish the pre-fault power flow after fault
separation as long as no line or converter is overloaded (cf. Figure 3-3 (a)). On
the contrary, a permanent fault in a radial network causes the long-term outage of
a converter station and accordingly changes the amount of transmitted power at
the AC-PoCs, as shown in Figure 3-3 (b). Hence, the KPI is defined based on the
active power set-points after fault separation.
Power Restoration Time Transient Energy Imbalance
P Active power tolerance P Energy

band (e.g. ± 10 %) Imbalance
(a)
t t
Fault Active power Fault Active power
inception recovery inception recovery
P Active power tolerance Energy

P
band (e.g. ± 10 %) Imbalance
(b)
t t
Fault Active power Fault Active power
inception recovery inception recovery
Figure 3-3: Active power restoration process (left) and energy imbalance (right) (a)
without a change in the active power set-point and (b) with a change in the active power
setpoint [Dan20]
However, the power restoration time cannot be directly linked to the stability of
power systems connected to the HVDC grid. The impact of DC faults on the
frequency stability of a power system can be assessed by the rate of change of
frequency (ROCOF) [Abe17, Zho18, Dan20]:
dωel PG – PL ΔP
= = ǡ (3.1)
dt 2 ∙ Hsys 2 ∙ Hsys
with ωel being the system’s angular frequency, Hsys the inertia time constant of the
whole power system and PG and PL being generated and consumed power within
the system. The energy imbalance can therefore be used as generic KPI to
evaluate the impact of temporary DC contingences on the AC transmission
system’s frequency disturbance. To simplify the evaluation of the energy
imbalance the corresponding KPI is defined here as the energy imbalance
between fault inception and active power restoration (cf. Figure 3-3 (right)).
tP,rst
ΔE = න PPreFlt – Pሺtሻ dt (3.2)
tflt
With PPreFlt being the active power exchanged between a converter or an entire
DC network and an AC system prior to fault inception.
In addition to the loss of active power transmission capability, the loss of the
STATCOM functions of a converter can have an impact on the local voltage
stability of the AC system [Abe17, Cha18]. Hence, the reactive power restoration
time is used as an KPI similar to the active power restoration time. To summarise
the AC system related KPIs:
‫ݐ‬P,rst: Active power restoration time – Time until the active power is
restored within a tolerance band to its post fault steady state value, e.g.
± 10 % of the rated converter power.
‫ݐ‬P,90: Active power restoration time to 90 % – Similar to the voltage
restoration, the KPI defines the time until the active power of a
converter is restored to the lower limit of the tolerance band for the
first time after fault separation, i.e. to 90 %.
ΔE: Transient energy imbalance – Difference of transferred energy from
normal to DC fault operation between fault inception and active power
restoration.
HVDC Network and Component Modelling 45
4 HVDC Network and Component Modelling
To assess the FBC-based protection system regarding its performance, the impact
on the network’s components and the effect on surrounding transmission systems
needs to be analysed, e.g. using comprehensive EMT simulations. The system and
component models are implemented in the simulation environment
PSCAD|EMTDC™ [Man18a]. The simulation time step is varied between
Δt = 0.5…20 μs depending on the requirements of the component models.
4.1 Test Network
To evaluate the FBC-based protection system, a test network reflecting various

HVDC grid configurations and the associated challenges is shown in Figure 4-1.
The intention of this test network is to provide a high degree of flexibility and to
enable a comprehensive analysis of the protection strategy within one system.
Therefore, it comprises two sub-networks: a meshed and a radial MTDC network.
Depending on the objective of the investigations, both sub-networks can be used
individually or as an interconnected network. The test network serves for both the
foreseen improvements of the MTDC protection strategy as well as for its
evaluation. Based on the state of knowledge, the following variations are
identified as particularly relevant and are considered in the test cases of the thesis:
x Network configuration (radial and mesh)
x Circuit configuration and grounding (sym. monopole and bipole)
x Characteristics of the connected AC networks, i.e. AC transmission grids
and islanded collector networks (i.e. WPPs)
x Type of transmission line (OHL and underground cable)
x Type of fault and fault resistance
The meshed sub-network comprises two onshore (C1 & C2) and two offshore
converter stations (C3 & C4). It consists of a three-terminal mesh between the
corresponding terminals T1, T2, T4 and a point-to-point connection between T1
and T3. The radial sub-network consists of two onshore converters (C5 & C6)
and one offshore converter station (C8) which are radially connected via a DC
hub (terminal T7). The line L35 between the DC terminals T3 and T5, which is
connecting the two sub-grids, is only included in the system in case the
interconnection of both networks is investigated. This test network comprising
both sub-grids is named as extended MTDC network and both sub-grids are
defined as one protection zone (PZ) (cf. section 3.1): The meshed sub-network is
named PZ1 and the radial sub-network is named PZ2.
As a base case for the majority of the investigations and for the development of
the protection strategy, the network is configured as symmetric monopole and
only comprises cables as transmission lines. However, for the comprehensive
analysis of the protection strategy, a bipole configuration (with DMR) is taken
into account for the examination of the grid restoration and the KPI analysis. To
analyse the applicability of the protection system on OHL-based transmission
systems, line L12, which represents the connection between two onshore stations,
is exemplary substituted by an OHL.
T1 T3
AC1 150 km OWP3
Meshed MTDC Network
C1 C3
400 kV 1200 MW 800 MW 66 kV

350 km
T2 T4
AC2 OWP4
C2 100 km C4
400 kV 800 MW 1200 MW 66 kV

200 km
T5
AC5
C5
Radial MTDC Network
T7 T8
400 kV OWP8
800 MW
C8
T6 100 km
AC6 66 kV
1200 MW
C6
400 kV 400 MW
C: Converter AC: AC Network

T: HVDC Terminal OWP: Offshore WPP collector network
Figure 4-1: MTDC test network including a meshed and a radial MTDC network with an
exemplary power flow scenario
In line with state-of-the-art offshore HVDC systems, which comprise XLPE
cables, the nominal DC operating voltage is set to Udc,N = ± 320 kV and the
normal operation voltage range is defined as Udc,NO = [0.9; 1.1] p.u. The converter
station settings are summarised in Table 4-1.
The onshore converter station (C1, C2, C5 & C6) are connected to AC
transmission systems. The offshore converter stations C3, C4 and C8 are
connected to an offshore AC transmission system, which is fed by a WT collector
grid. The voltage ratings of the AC systems are summarised in Table 4-2. In the
base case, the offshore collector networks are simplified by Thevenin sources (cf.
section (4.7)). For the analysis of the interoperability between the FBC-based
protection strategy and the FRT capabilities of offshore WTs, a detailed
representation of the WPP is considered (cf. section 4.7)
Table 4-1: Converter station settings
Converter Station Parameter Setting
Rated power Sr 1265 MVA
Rated active power Pr 1200 MW
Rated reactive active power Qr 400 Mvar
Table 4-2: AC system voltage ratings

Onshore AC transmission network UAC,on 400 kV (L-L, rms)
Offshore AC transmission network UAC,off 155 kV (L-L, rms)
Offshore AC collector network UAC,coll 66 kV (L-L, rms)
The converters’ active power control modes and the corresponding reference
values for the three different DC grid configurations are presented in Table 4-3.
Table 4-3: Base case active power control modes and reference values for the different test
network configurations
Meshed Network Radial Network Interconnected Network
Setting Reference Setting Reference Setting Reference
C1 Udc ± 320 kV Vdc ± 320 kV
C2 P 800 MW P 800 MW
C3 P - 800 MW P - 800 MW
C4 P 1200 MW P 1200 MW
C5 Udc ± 320 kV P 1000 MW
C6 P 1200 MW P 1200 MW
C7 P - 800 MW P - 800 MW
To test the impact of DC contingencies on the reactive power support of the

onshore converters to the AC transmission system, the onshore converter stations
(C1, C2, C5 & C6) operate in reactive power control mode (Q control). In the
base case scenarios, in which the simulated WPPs are simplified using Thevenin
equivalent voltage sources, the offshore converter stations (C3, C4 & C8) operate
in AC voltage control mode (UAC-control). If the detailed offshore WPP model is
used, the offshore converter stations are set to Grid Forming Control (GFC)
mode.
The evaluation of the protection strategy is based on a systematic variation of
fault scenarios within the DC network. For each line both pole-to-ground10 (PG)
and pole-to-pole-to-ground (PPG) faults in the beginning (0%), middle (50%) and
end (100%) are considered for the assessment of the protection strategy.
Moreover, different fault-to-ground resistances are considered in the analysis:
RF,PG = [0.1 Ω; 20 Ω]11. The fault resistance between two DC poles is assumed to
be RF,PP = 0.01 Ω.
4.2 Converter Stations
Within this work, FBC-based DC protection schemes in monopole and bipole

network configuration are evaluated. The detailed schematics of the
corresponding converter stations are shown in Figure 4-2.
Each converter is represented by a Type 4 – Detailed Equivalent Circuit Model.
The individual capacitors and power electronic components of the SM are not
explicitly represented, but modelled as a Thévenin equivalent, which reduces
computational effort. Additionally, each converter arm comprises a lumped arm
inductance and lumped arm resistance representing the ohmic losses of the arm
inductor and the SM’s power electronic devices12. Since the model is
mathematically equivalent to an MMC model with linear switches it is well suited
for fault studies [CIG14]. The key parameters of the monopolar and bipolar
converters are summarised in Table 4-4.
The SM design is based on 3.3 kV IGBT modules with a rated repetitive peak
collector current ICRM = 3 kA [Inf19]. Correspondingly, the average capacitor
voltage is set to uc,nom = 1.9 kV. The steady-state capacitor voltage ripple of the
SM capacitors is typically kept within a uc,Δ = ±10 % tolerance band. Therefore,
the energy stored in each converter is set to EMMC = 30 kJ/MVA [Jac10, Sha16].
10
Due to the symmetric design, only ground faults of the positive pole are considered regarding pole-
to-earth faults.
11
These values are used for the performance analysis of the protection strategy and may therefore
differ from statistical values.
12
The IGBT switching behaviour and the corresponding losses as well as snubber circuits and parasitic
effects of the semiconductors are not considered in the type 4 model.
monopolar converter station

converter DC-PoC
transformer star-point
AC-PoC
reactor
arm surge arresters
SM1 SM1 SM1

AC surge DC pole DC surge SM2 SM2 SM2
arresters inductors arresters
SMn SMn SMn
arm inductors
bipolar converter station
converter
transformer DC-PoC
SM1 SM1 SM1

AC-PoC SM2 SM2 SM2
SMn SMn SMn
AC surge DC pole DC surge

arresters inductors arresters
Figure 4-2: Schematics of the converter stations in monopole and bipole configuration
The converter valves are connected to the AC-PoC via a three-phase Y-∆
transformer with a grounded star point on the grid side. The transformer
parameters are adapted from a CIGRÉ benchmark model [CIG14]. The detailed
transformer parameters are presented in Table 4-5. To limit the current rise during
DC faults, the valves are connected to the DC-POC via the lumped reactances
Ldc,T. To protect the converters against transient overvoltages, surge arresters (SA)
are implemented at both PoCs and within the converter as shown in Figure 4-2.
The protection level of the AC, DC and mid-point SAs is set to up = 1.8 p.u., with
iSA(up) = 1 kA. The protection level of the arm surge arresters is set to
up = 1.7 p.u., with iSA(up) = 1 kA [Wen18]. The detailed SA characteristic is given
in Appendix A.1. Since DC networks in symmetric monopole configuration are
not effectively grounded on the DC side, a high-impedance star-point reactor with
is implemented at all onshore converter stations with Lstar = 5000 H and
Rstar = 5 kΩ [CIG14].
Table 4-4: Converter specification

Parameter Monopole Bipole
Nominal active power Pr 1200 MW 600 MW
Nominal reactive power Qr ± 400 MVAr ± 200 MVAr
Nominal DC voltage udc,nom 640 kV 320 kV
Nominal DC current idc,nom 1.875 kA
Nominal AC voltage – converter side uac,2 350 kV
Arm inductor Larm 50 mH 25 mH
Resistance of the arm inductor Rarm 100 mΩ 50 mΩ
DC terminal inductor Ldc,T 40 mH
Number of SM per arm NSM 350 175
Submodule capacitance CSM 8.8 mF
SM on resistance13 RSM,on 3.2 mΩ
Nominal SM voltage uc,nom 1.9 kV
Maximum SM voltage uc,max 3.3 kV
Maximum arm current iarm,max 0.9 ∙ ICRM,IGBT = 2.7 kA
Table 4-5: Converter Transformer specification

Parameter Monopole Bipole
Rated power SXFO,r 1265 MVA 1265 MVA
Nominal AC primary voltage – onshore grid uac,1,nom 400 kV 400 kV
Nominal AC primary voltage – offshore grid uac,1,nom 155 kV 155 kV
Nominal AC secondary voltage – converter side uac,2,nom 350 kV 166 kV
Leakage reactance (base SXFO,r) XXFO 0.18 p.u.
Copper losses (base SXFO,r) PXFO,cu 0.002 p.u.
Eddy current losses (base SXFO,r) PXFO,eddy 0.0003 p.u.
To ensure a safe converter operation, a converter internal emergency protection

comprising a valve overcurrent as well as a submodule over- and undervoltage
protection is implemented in the control model. The threshold value for the
overcurrent protection is set to Iarm,thres = 0.9 ∙ IIGBT,CRM of the repetitive peak
collector current of the submodule IGBTs. The normal operation capacitor
voltage thresholds are set to uC,SM = [1.3 2.5] p.u. of the nominal submodule
capacitor voltage. Once one of these values is exceeded for more than
ΔtESOF = 100 µs, the converter emergency switch-off (ESOF) is triggered and the
blocking of all IGBTs as well as the opening of the AC-side circuit breaker is
initiated [PRO17b].
13
Assuming that the ohmic losses of the IGBTs and the diodes are in the same range, the equivalent
SM resistance of each arm is set to RSM,arm = 4 ∙ NSM,arm ∙ 0.8 mΩ (at Tjunction = 125°C) [CIG14, Inf19].
4.3 Transmission Lines
For an accurate representation of the travelling wave characteristics during DC

line faults, the Frequency Dependent (Phase) model, also known as Universal
Line Model, is used for modelling of the transmission lines [Mor99].
Generic line setups are based on state-of-the-art 320 kV HVDC transmission line
data [Wag16, Sco19]. Figure 4-3 illustrates the cable trench and OHL tower
geometries used for the symmetric monopole and the bipole system
configurations.
G
0.5 m 0.5 m 10.5 m

1.5 m
5.2 m 10.8 m
<c <c <c 11 m

P
27.3 mm Conductor (Stranded Copper) 6.5 m 7.8 m M N

Inner Semiconductor*
50.3 mm Insulator (XLPE)
Outer Semiconductor* 28.7 m 50.2 m
53.2 mm Sheath (Lead Alloy)
55.7 mm Insulator (PE)
60.7 mm Armour (Steel)
64.7 mm Insulator (PP)
* Thickness of the semiconductor layers: 1.5 mm
Figure 4-3: Cable trench and OHL tower geometries for the symmetric monopole and the
bipole system configuration [Wag16, Sco19]
The 320-kV HVDC cables are based on copper core conductors with cross
sections of Acore = 2,200 mm² with a core resistivity of ρcore = 1.72∙10-8 Ωm14. The
cable screen is made of lead alloy with ρscreen = 2.1 ∙10-7 Ωm. The relative
permittivity of the inner insulator made of cross-linked polyethylene (XLPE) is
set to εr,XLPE = 2.5 whereas the relative permittivity of the of the high-density
polyethylene (PE) sheath insulator and the outer polypropylene (PP) insulator are
both set to εr,PE = εr,PP = 2.3. The relative permeability of all inner layers is set to
µ = 1 [Mar10, Maz13]. Offshore cables typically comprise an additional steel
armouring (ρarmour = 1.8∙10-7 Ωm and µ = 10) which is coated by an additional
insulating layer [Mar10, Maz13]. Assuming a regular grounding of the cables’
armour and sheath, their concentric conductors are eliminated mathematically in
14
To account for the stranded conductors, the copper resistivity used in the EMT model is increased
to ρcore,EMT = 2.2∙10-8 Ωm.
the simulation software. While the cable model used for symmetric monopole
system configurations comprises two cables located 0.5 m apart from each other,
the model for bipole configurations comprises all three cables, with the metallic
return conductor M located between the P and N conductor.
The OHL conductors are modelled according to a 4-bundle steel-reinforced
aluminium conductors (Al/St 265/35), whereas the ground wires are modelled
according to Al/St 240/40 conductors [Wag16]. The ground is represented as
frequency-dependent conductivity in both models. For the cable model, the
complex ground impedance integral is solved with a direct numerical integration,
while for the OHL model it is solved using the Deri-Semlyen approximation. The
soil is modelled with a constant resistivity of ρsea = 1 Ωm in case of the sea cable
and ρland = 100 Ωm for the OHL [Mar10].
4.4 Fault Separation Units
Based on the analysis of existing switchgear technologies, which could be applied

as FSUs in MTDC networks protected by FBCs, DC CBs with reduced DC
voltage and energy absorption ratings and conventional AC CBs have been
identified as possible options.
4.4.1 DC Circuit Breakers
Even though many different DC CB technologies could be applied as FSU, like

pure solid state, hybrid or mechanical breakers, from a grid perspective they can
be summarised by a generic approach, which emulates the DC CB counter voltage
as well as the current interruption behaviour [PRO20]. The building blocks of the
model, which is shown in Figure 4-4, are:
Main and commutation path: The main and commutation paths are
summarised by an ideal switch with parallel snubber circuit and stray
inductances. To represent the internal current commutation time of different
DC CB technologies a variable delay time ΔtCB,com is added to the model
[CIG17a]. The current commutation representing common DC CB
technologies are given in Figure 4-4.
Energy absorption path: The absorption path is modelled by SA, which
provides the transient interruption voltage (TIV) across the DC CB and
absorbs the stored residual energy. The peak TIV is typically set to
uCB,TIV = 1.5 p.u. [Häf11, Jov19]. The SA characteristics are given in
Appendix A.1.
Isolation: To isolate the faulted line and to interrupt a SA leakage currents, DC

CB model comprises a fast disconnecting switch which is triggered
subsequently to the DC CB. After an opening time delay of ΔtFD,open an ideal
switch is opened, if the current iFD is smaller than the interruption capability
of the disconnector, e.g. iFD < 0.5 A.
Fast DC Circuit Breaker

Disconnector uCB energy absorption path
main path and commutation path
busbar DC line
terminal terminal
iFD iCB
iFD < ich, FD Current Commutation Time
DC-CB Type ΔtCB,com
wait(ΔtFD,O) wait(ΔtCB,O) Solid-State 0.2 ms
Hybrid 2 ms
trip FD trip CB Mechanical (Active Resonant) 8 ms
Mechanical (Passive Resonant) 20 ms
Figure 4-4: Generic DC circuit breaker model; Within the model, the opening time delay
is equivalent to the current communication time (ΔtCB,O = ΔtCB,com) [PRO20]
4.4.2 AC Circuit Breakers
AC CBs can be modelled in EMT programs by a dynamically changing resistance

or conductance, which is calculated based on the arc voltage and current, as
illustrated in Figure 4-5 [Wal13, Buc14]. Current chopping is considered in the
model by an ideal switch with a defined current chopping capability ich. To
account for the CB opening, which comprises the actuation and the contact
separation time, a delay of topen,CB is used. Subsequently to the opening of the AC
CB a fast disconnector (FD) designed for HVDC applications isolates the faulted
line from the remaining, healthy DC network. The FD is parametrised according
to an ultra-fast disconnector used in hybrid DC CB applications [Ska13].
Thermal and dielectric break-downs are not directly considered within the model.
Hence, the ROCOC and the TRV occurring during current interruption process
are monitored and compared with standard dicrit/dt values and the corresponding
IEC TRV envelopes during the post processing [IEC18].
Fast AC Circuit Breaker

busbar Disconnector uCB DC line
terminal terminal
uarc
iFD iCB Rarc

uarc arc
iFD < ich, FD iCB < ich,CB
iCB model
wait(ΔtFD,O) wait(ΔtAC,O)
trip FD trip CB
Figure 4-5: AC circuit breaker model

SF6-CBs can be modelled in EMT programs by a dynamically changing resistance
or conductance, which is calculated based on the arc voltage and current. Classical
arc models for AC applications are Cassie’s and Mayr’s arc models [Wal13]. The
arc conductance depends on the power supplied to and extracted from the arc by
cooling and radiation. While Cassie’s arc model is well suited during high
currents, Mayr’s arc model is applicable for small arc currents (plasma
temperatures below 8000 K). Within FBC-based protection schemes, SF6-CBs
used as FSUs only have to interrupt residual currents. Hence, the arc voltage is
modelled using Mayr’s arc model, which is presented in (4.1) [Nak01, Wal13].
dgm gm ‫ݑ‬arc ∙ iarc
= ൬ – 1൰ , (4.1)
dt τm Pc
where gm is the arc conductance, τm the arc time constant, Pc the cooling power,
uarc the arc voltage and iarc the arc current. The cooling power is defined as a
function of the initial cooling power constant P0 and the current and the arc time
as a function of the arcing time constant τ0 and gm of a specific CB [Nak01]:
Pc = P0 ∙ iaarc (4.2) τm = τ0 ∙ gbm (4.3)
To limit the arc voltage for very small currents (i.e. iarc < 100 A) a seamless
transition to a constant voltage model is implemented. The maximum arc voltage
of the constant voltage model is based on real measurements of the corresponding
SF6-CB model. To account for different opening times, the time is varied between
Δtopen,SF6 = 20...40 ms [CIG17a].
Since the arc voltages of VCBs are negligible compared to the DC pole voltages
(even during the fault control process), the arc voltage is not considered within
the model (uarc = 0 V). While the opening time of standard VCBs based on coil
spring actuators is in the range of Δtopen,VCB = 30 ms [CIG17a], the application of
high-speed electro-mechanical actuators can reduce the opening time to
approximately Δtopen,VCB = 8 ms [Jov18, Jov19]. To account for both options, the
opening time is varied between these values within the analysis of this work.
4.5 Voltage Balancing Equipment
HVDC networks with an isolated neutral point, i.e. networks in symmetric

monopole configuration, require schemes for the re-balancing of their pole
voltages in case of single pole-to-ground faults (cf. section 2.4). Based on the
assessment of existing balancing schemes for HVDC networks applying fault-
feeding converters, i.e. HB-MMCs, dynamic braking systems are considered as
balancing option of the DC-side whereas zig-zag grounding transformers are
considered as balancing option on the AC side of the converter (cf. Figure 2-7).
In case voltage balancing schemes are integrated into the protection system, they
are located at the converters C1, C2, C5 and C6, which are representing onshore
stations. The parameters of the balancing schemes are given in Table 4-6.
Table 4-6: Model parameters of the DBS and zig-zag grounding transformer [Wan19]
Dynamic Braking System Setting Zig-Zag Grounding Transformer Setting
Braking resistor RDBS 171 Ω Rated power Sn 3 MVA
Maximum DBS current IDBS,max 2 kA Leakage impedance LZ 0.1 p.u.
Proportional control gain KP,DBS 0.5 Neutral resistor RZ 200 Ω
High 1.1 p.u.
Hysteresis
Low 1.05 p.u.
PWM frequency fPWM 2 kHz
4.6 Busbar Design, Protection and Communication System
Figure 4-6 illustrates the architecture of the DC terminals, used within this work.
Each DC terminal comprises voltage and current sensors at each line end and
between the busbar and the converter station15, which are used for fault detection
and the fault localisation (the identification of a faulted line). To respect the low-
pass characteristics and other non-ideal characterises of measurement units,
15
All line currents are measured from the busbar to the line, while the terminal current is measured
from the converter station to the busbar.
third-order Butterworth low-pass filters (LFP) and a distortion with a white noise
is added to the sensor model, as shown in Table 4-7 [CIG18a, Tün20]. If double-
ended protection methods are applied, the relevant measurements and signals of
the line ends are sent to the two corresponding line ends.
Dispatch
Controller
Protection IED Optic Fibre Communication Protection IED

to IEDs at adjected line ends
fault detection fault detection
fault localisation fault localisation
FSU control S2 FSU control
grid restoration grid restoration

FSU12
V V
Control Unit Control Unit
FSU14 FSU14
V V V V V V
S1 S4
Terminal Measurements FSU13 FSU34
V V V V
FSU Control
(& Measurements)
Line Measurements S3
Figure 4-6: DC terminal layout

Moreover, the model comprises a central dispatch controller. Within this work,
the communication between the individual terminals and the dispatch controller
as well as the communication between the IEDs at different line ends is realized
via the shortest path along the DC cables utilising optic glass fibre cables. The
communication infrastructure is emulated in the EMT model by time delays
accounting for the communication velocity of state-of-the-art optical fibre
technology, i.e. vcom = 200 m/µs, and signal processing delays, i.e.
∆tcom,proc = 500 µs [CEN18].
Table 4-7: Sensor model characteristic [Sch11, CIG18]
Parameter Voltage Sensors Current Sensors
Butterworth LPF cut-off frequency fu,dc,c, = 10 kHz fi,dc,c, = 10 kHz
Amplitude of white noise δu,dc = 0.4% δi,dc = 0.1%
Within this work’s implementation of the protection strategy, the IEDs located at
each terminal are used for directing the induvial components. Therefore, the IEDs
comprise the four major functionalities:
Fault Detection: Since all converters have to limit their fault current
contribution to values close to zero, every converter has to detect a DC fault
as fast and reliably as possible. Hence, a single-ended voltage derivative
du/dt protection in combination with an undervoltage protection is
implemented at each converter terminal [Ruf19a]. The parameters of the
fault detection algorithms are given in Table 4-8.
Fault Localisation: The location of the fault is not required instantaneously,
since the line current control algorithm and the tripping of the FSUs is only
activated after the reduction of the fault current and the DC grid voltage.
Hence, a simple double-ended line current differential protection can be
used to identify the faulted line without a compromise in safety [Jov18,
Ruf19a]. An advantage of this fault localisation principle in contrast to
single-ended methods is that no current limiting inductors are required at the
line ends. Within this work, the fault localisation process is imitated by fault
detection. The parameters of the differential current protection algorithm are
given in Table 4-8.
FSU Control: In addition to fault detection and discrimination, the IEDs
supervise and trip the FSUs.
Restoration: After the separation of the faulted line, the DC grid voltage and
the active power flow has to be restored. This process is initiated by the
dispatch control, which sends the restart signal to the individual converters
and IEDs after it receives an open status from all relevant FSUs.
Table 4-8: Protection settings
Fault Detection Criteria Fault Localisation Criteria
Undervoltage Udc,T ≤ 0.75 p.u. Fault Detection true
Voltage derivative ∆udc,T/∆t ≥ 1 p.u./ms Differential Current idiff ≥ 1.5 p.u.
Hold time ∆thold = 25 µs Hold time ∆thold = 25 µs
4.7 Wind Power Plants
In recent years, type 4 wind turbine generators (WTG) comprising full-rated

back-to-back converters have become the dominant technology in the wind
industry due to their high degree of controllability. Accordingly, the

interoperability analysis between the developed DC protection system and
(offshore) WPP are conducted with a collector grid model comprising three
aggregated 400 MW WPPs each representing 50 type 4 WTGs. The WTGs are
connected to an HVDC station by two transformers and three AC cables, as
illustrated in Figure 4-7. Contrary to the HVDC cables, the relatively short AC
cables of the offshore WPP are modelled by PI sections with: RPI = 10 mΩ/km,
LPI = 0.3 mH/km and CPI = 0.4 μF/km. In line with the HVDC transformers
presented in Table 4-5, all transformers are modelled with leakage inductances of
LXFO = 0.18 p.u.
The WTG model comprises a wind turbine model, including a pitch controller, a
permanent magnet generator, a machine- and a grid-side converter connected via
a DC capacitor and an grid-side low-pass filter [Man18b]. Due to the inertia of
the rotating turbine mass, WTGs are unable to reduce their active power during
an AC-FRT. To fulfil today’s FRT requirements, a DC-side chopper is part of the
WTG, which prevents the DC voltage from rising by dissipating the generated
power which cannot be transferred to the AC grid [Her16].
420 MVA
66 kV/0.69 kV
400 MW
4 km
1265 MVA 1265 MVA
G
350 kV/155 kV 155 kV/66 kV
400 MW
8 km 3 km
G
HVDC VSC 400 MW

6 km
G
WT Chopper
Figure 4-7: Offshore wind power plant model

The WTG parameters and controls are adopted from [Man18b] and scaled to fit
the WTG rating of 8 MW. The generator-side WTG converter controls the active
power, while the grid side converter controls the DC voltage and the AC voltage
by a cascaded current-vector control in a dq frame rotating with the angular speed
of the grid ωg and its d-axis aligned with the grid voltage vector. To prevent
overcurrents within the converters, the converter currents are limited, i.e. to
Imax = 1.1 p.u. in the dq frame with a priority given for reactive power. Moreover,
the AC output voltage of the grid-side converter is limited to UAC,WTG = 1.15 p.u.
As, WTG are typically operated in grid following mode, a phase-locked-loop
(PLL) is used to track the phase angle θg(t) of the grid voltage vector. The detailed
model parameters are given in Appendix A.3.
Converter Controls 59
5 Converter Controls
In case of a DC fault, FBCs have to dynamically limit their fault current

contribution, support the fault separation and afterwards quickly restore the DC
voltage as well as the power flow. During such dynamic events, the converter
needs to maintain its internal currents and voltages within their operation limits
to avoid an emergency switch-off. Hence the converter control must allow a high
degree of controllability of the individual voltage and currents, have a fast
dynamic response and a good disturbance rejection. Moreover, a control concept
for the independent AC, the CC and the DC models presented in Figure 2-2 as
well as suitable controller parameters are required.
A well-established, dynamic and stable method to control VSCs, in particular
MMCs, is a cascaded vector control [CIG14, Leo17, Hah18, Wen19]. Within this
approach current controllers form the inner control loops, which manage the
currents and ensure that the converter current limits are respected. The
corresponding reference current controllers manage the total and intra-arm energy
balancing of the converter, the power exchange between the AC and DC side and
quantities like the DC voltage. As defined in (2.20) and (2.21) the three reference
voltages generated by the current controllers define the arm reference voltages
eu,i* and el,i*. Using a modulation algorithm, e.g. the nearest level modulation
(NLM), which defines the number of submodules to be inserted and a capacitor
balancing algorithm (CBA) to ensure an even distribution of the energy stored
within the capacitors of each arm, the reference voltages are transformed into the
firing signals for the IGBTs [CIG14]. Figure 5-1 illustrates a high-level overview
of the MMC controls and summarises the individual components of the three
current control loops.
The converter control levels are usually implemented on digital signal processors
(DSP) with sampling rates TC in the order of a few tens of microseconds, while
the lower or SM control level is implemented on field-programmable gate arrays
(FPGA) with much smaller sampling times. For the design of the upper level
controllers – the current and reference current controllers – the transition from the
arm reference voltages eu,l* to the actual arm voltages eu,l is typically smaller that
the time required for one computation step and hence can be approximated as a
delay of one computational time step TC [Sha16].
While the upper level converter controls, which enable a dynamic control of the
FBC during DC faults, are developed within this work, the NLM and CBA are
directly adopted from literature [Hei18a]. Whereas the deduction of the control
concept and its parameterisation is presented within the following, the per unitised
control parameters applied in the simulation model are given in Table A-3.
Outer Loops Inner Loops Submodule MMC/Plant
Management
SM1 SM1 SM1
idc * DC edc * eu* SM2 SM2 SM2
• DC Voltage CBA
Current
• Converter Energy &
Control NLM SM3 SM3 SM3
• Active Power SMn SMn SMn
• DC Voltage
• Converter Energy iac * AC eac *
Current
• Reactive Power Control
• AC Voltage SM1 SM1 SM1
icc * ecc * el* CBA SM2 SM2 SM2
• Horizontal Balancing CC
Current &
SM3 SM3 SM3
• Vertical Balancing Control NLM
SMn SMn SMn
Converter Control Level (DSP) SM Control Level (FPGA)
Figure 5-1: Overview of the MMC control
5.1 Current Controllers (Inner Loops)
In steady-state, the AC and CC model only comprise of rotating voltage and

current vectors, while the DC model only comprises direct components. A
common and robust converter control method is a cascaded current vector control
based on proportional-integral (PI) controllers [Teo11, CIG14]. However, since
PI controllers are inherently incapable of tracking sinusoidal reference values
without amplitude and phase error, they are not directly applicable for the AC and
CC controls [Teo11, Sha16]. To overcome these limits and to improve harmonic
disturbance rejection, the vectors abc, which are rotating with the angular speed
ω, can be transformed into equivalent stationary vectors in a dq reference frame
rotating with ω, using park’s and clark’s transformation matrices [Tdq0] & [Tαβ0]
[Teo11]. Alternatively, rotating vectors can be directly controlled with
proportional-resonant (PR) controllers tuned to the angular speed ω of the rotating
vectors. The developed control comprises both approaches.
5.1.1 AC Current Control
AC grid controllers of VSCs are typically implemented in a dq frame rotating

with the angular speed of the grid ωg and its d-axis aligned with the grid voltage
vector. Thereby, the reference current component iac,d* is used to control the active
power whereas the reference current component iac,q* is used to control the
reactive power exchange between the converter and the grid. The tracking of the
grid frequency ωg can be realised by a three-phase synchronous phase locked loop
(PLL). The PLL algorithm used within this work is implemented in a decoupled
double synchronous reference frame (DDSRF), which allows an accurate grid
synchronization even under unbalanced grid faults [Teo11]. The detailed
implementation of the PLL is provided in Appendix A.4.
The AC model defined in (2.8) transformed into a dq reference frame rotating
synchronously with the AC grid are expressed in (5.1) and (5.2).
diac,d 1
– ωg iac,q = ൫eac,d – uac,d – Rac ∙ iac,d ൯ (5.1)
dt Lac
diac,q 1
+ ωg iac,d = ൫eac,q – uac,q – Rac ∙ iac,q ൯ (5.2)
dt Lac
Consequently, the d- and q-component of the AC current can be controlled with

individual PI controllers, as shown in Figure 5-2. For an independent control of
the d- and the q-component, the dependence of (5.1) from the iac,q and (5.2) from
iac,d is compensated by a feed-forward decoupling. In order to improve the
dynamic response and the rejection of grid disturbances, an AC grid voltage feed-
forward is used [Teo11]. To enhance the performance under unbalanced
conditions, the AC currents are also controlled in the DDSRF enabling a separate
control of their positive and negative sequence [Teo11, Sha16].
In addition to the controller and the AC plant, the dynamic response of the
modulation and different non-compensable dead times, like the digital
computation dead time, have to be considered for the controller design. The dead
times caused by the modulation and firing of the SM can be conservatively
approximated by one DSP control sample step (TM ≤ TC). Various other smaller
dead times, like communication and sensor delays as well as the analogue/digital
(AD) conversion can be summarised within the computational delay TC [Sha16].
To reject high-frequency disturbances, the measurements are typically filtered
using low-pass filters with a filter time constant TLPF. Assuming an ideal
decoupling of the d and q control loop as well as an ideal compensation of the AC
voltage uac,dq by the corresponding feed-forward terms16, the detailed AC current
16
Due to the delay times caused by the computational time step, modulation and measurement filters
a complete decoupling and compensation cannot be achieved. Consequently, they are regarded like
external disturbances [Hah18].
control loop comprises the AC controller, the AC plant model, computational and
modulation delays as well as measurement filtering [Hah18].
AC current Computational Time AC plant

‫ݑ‬ୟୡǡୢ Step & Modulation ‫ݑ‬ୟୡǡୢ
controller
‫כ‬
݁ୟୡǡௗ ݁ୟୡǡୢ ͳ
‫כ‬
݅ୟୡǡୢ ‫୍ܭ‬ǡ୍ୟୡ ݅ୟୡǡୢ
‫୔ܭ‬ǡ୍ୟୡ ൅ ݁ ି௦்ి ݁ ି௦்౉
‫ݏ‬ ܴୟୡ ൅ ‫ܮݏ‬ୟୡ
݅ୟୡǡୢ ߱୒ ‫ܮ‬ୟୡ ߱୒ ‫ܮ‬ୟୡ

Decoupling
݅ୟୡǡ୯ ߱୒ ‫ܮ‬ୟୡ ߱୒ ‫ܮ‬ୟୡ
‫כ‬
݁ୟୡǡ୯ ݁ୟୡǡ୯ ͳ
‫כ‬
݅ୟୡǡ୯ ‫୍ܭ‬ǡ୍ୟୡ ݅ୟୡǡ୯
‫୔ܭ‬ǡ୍ୟୡ ൅ ݁ ି௦்ి ݁ ି௦்౉
‫ݏ‬ ܴୟୡ ൅ ‫ܮݏ‬ୟୡ
‫ݑ‬ୟୡǡ୯ ‫ݑ‬ୟୡǡ୯
Meas.
݁ ି௦்ి
filtering
Figure 5-2: Block diagram of the AC current control loop

For the derivation of suitable control parameters, all non-compensable dead times
and filter time constants of the control loop are summarised to Td,Iac in (5.3).
Td,Iac = 2TC + TM + TLPF,ac ≤ 3TC + TLPF,ac (5.3)
Linearizing this time delay through a first-order Taylor approximation, the

open-loop transfer function of the system is defined by (5.4) [Hah18].
1ൗ
KS Rac
GP,Iac ሺsሻ = =
(1 + sTN,Iac ) ∙ (1 + sTd,Iac ) ቀ1 + s Lac ቁ ∙ ൫1 + sT (5.4)
Rac d,Iac ൯
The main objective of the current controllers is a dynamic and stable reference
tracking. Since the plant can be characterised as an PT2-system, the modulus
optimum method17 can be applied for the deduction of control parameters
optimised for the task of reference tracking. Assuming the time constant of the
plant being larger than the sum of the time delays (Lac/Rac > Td,Iac), the PI control
parameters are given in (5.5) and (5.6) [Hah18, Wen19] 18.
17
The symmetrical optimum method or the modulus optimum method are common and proven methods
for the tuning of PI controllers of VSCs, in particular MMCs [Baj08, Hah18, Wen19].
18
All PI controllers comprise an output saturation with an anti-windup function, i.e. a back-calculation
anti-windup, in order to limit their input and output values [Sha16, Wen19].
TN,Iac Lac KP Rac

KP,Iac = = (5.5) KI,Iac = = (5.6)
2KS Td,Iac 2Td,Iac TN,Iac 2Td,Iac
Equation (5.7) summarises the resulting closed-loop transfer function and its first-
order approximation, which is used for the control parameter design of the
corresponding reference controllers.
1 1 1
GC,Iac (s) = -1 = 2 ≈ (5.7)
1+ GO,Iac (s) 1 + s2Td,Iac + s2 2Td,Iac 1 + s2Td,Iac
To increase the RMS value of the secondary AC voltage while maintaining the
peak value, a third harmonic injection is applied subsequently to the AC current
control [CIG14]. Hence, the converter can transfer more power with the same
component voltage ratings.
5.1.2 Internal Current Control Loop
According to (2.35) – (2.40), the inner currents are used for the internal energy
balancing between the converter arms. Since the energy between the phases
moves via the individual DC components of the phases and the energy between
the upper and the lower arms moves via a negative sequence current alternating
at ωg (cf. section 2.1.2), a direct control in the stationary αβ0 reference frame is
preferable [Leo17, Hah18]. In order to accurately track the sinusoidal reference
values of the vertical balancing, a resonant controller tuned to the first harmonics
is added to the control. To suppress the higher order harmonic currents resonant
controllers tuned to the second and third harmonic are added to the control
[Leo17]. Figure 5-3 presents the overall control loop of the CC current control.
Again, delays accounting for the digital control (computation time step), the
modulation and the measurement filters are considered in the control loop.
Analogous to (5.3), all delays are combined to a single time delay Td,Icc for the
control parameter design.
Td,Icc = 2TC + TM + TLPF,cc ≤ 3TC + TLPF,cc (5.8)
Based on (2.15) and the first-order approximation of the system’s delays, the
open-loop transfer function of the CC current model is given in (5.9).
1
KS
2Rarm
GP,Icc ሺsሻ = = (5.9)
(1 + sTN,Icc ) ∙ (1 + sTd,Icc ) ቀ1 + s Larm ቁ ∙ ൫1 + sT
Rarm d,Icc ൯
The PI gains KP,Icc and KI,Icc are tuned equivalent to the AC current control using
the modulus optimum method, as shown in (5.10) [Hah18]. The corresponding
resonant controllers are tuned according to (5.12) and (5.13) [Sha16].
TN,Icc Larm KP,Icc Rarm
KP,Icc = = (5.10) KI,Icc = = (5.11)
2 ∙ KS ∙ Td,Icc Td,Icc TN,Icc Td,Icc
Kh1,cc = 2ωh1 KP,cc (5.12) Kh2,cc = 2ωh2 KP,cc (5.13)
The resulting closed-loop transfer function and corresponding first-order

approximation of the CC control loop is given in (5.14).
1 1 1
GC,cc (s) = ≈ 2 ≈ (5.14)
1 + G-1
O,cc (s) 1 + s2Td,Icc + s2 2Td,Icc 1 + s2Td,Icc
CC current
controller
Computational Time
‫୍ܭ‬ǡ୍ୡୡ Step & Modulation CC plant
‫כ‬
‫୔ܭ‬ǡୡୡ ൅
݅ୡୡ ‫ݏ‬ ‫כ‬
݁ୡୡ ݁ୡୡ ݅ୡୡ
ͳȀʹ
݁ ି௦்ి ݁ ି௦்౉
ଶ ܴୟ୰୫ ൅ ‫ܮݏ‬ୟ୰୫
‫ܭ‬୰௛ǡ୍ୡୡ ȉ ‫ݏ‬
෍
‫ݏ‬ଶ൅ ݄߱௛ ଶ
௛ୀଵ
Meas.
݁ ି௦்ి
filtering
Figure 5-3: Block diagram of the CC current control loop
5.1.3 DC Current Control Loop
Analogous to the AC current control, Figure 5-4 illustrates the DC current control
with its plant based on (2.16). Since the DC current can be directly controlled
using a PI controller, no reference frame transformation is needed.
DC current Computational Time
‫ݑ‬ୢୡ ‫ݑ‬ୢୡ
controller Step & Modulation DC plant
‫כ‬ ‫כ‬
݅ୢୡ ݁ୢୡ ݁ୢୡ ݅ୢୡ
‫୍ܭ‬ǡୢୡ ͳ
‫୔ܭ‬ǡୢୡ ൅ ݁ ି௦்ి ݁ ି௦்౉
‫ݏ‬ ܴୢୡ ൅ ‫ܮݏ‬ୢୡ
Meas.
݁ ି௦்ి
filtering
Figure 5-4: Block diagram of the DC current control loop

Again, all non-compensable delays are summarised in Td,Idc, as defined in (5.15).

Td,Idc = 2TC + TM + TLPF,dc ≤ 3Ts + TLPF,dc (5.15)
Consequently, the transfer function of the DC current model GP,dc(s) can be
approximated by (5.16). The corresponding control parameters derived with the
modulus optimum method are given in (5.17) and (5.18) [Hah18].
1ൗ
KS Rdc
GP,dc ሺsሻ = =
(1 + sTN,Idc ) ∙ (1 + sTd,Idc ) ቀ1 + s Ldc ቁ ∙ ൫1 + sT (5.16)
Rdc d,Idc ൯
TN,Idc Ldc KP,Idc Rdc

KP,Idc = = (5.17) KI,Idc = = (5.18)
2 ∙ KS ∙ Td,Idc 2Td,Idc TN,Idc 2Td,Idc
Analogous to (5.7), (5.19) summarises the closed-loop transfer function of the DC

current controller and its first-order approximation.
1 1 1
GC,Idc (s) = -1 = 2 ≈ (5.19)
1 + GO,Idc (s) 1 + s2Td,Idc + s2 2Td,Idc 1 + s2Td,Idc
5.2 Reference Controllers (Outer Loops)
For a stable operation of the MMC, all SMs have to be sufficiently charged and
the energy stored within the MMC needs to be well balanced across and within
the arms. According to section 2.1.2, the energy balancing can be separated into
three parts: The total, the horizontal and the vertical energy balancing [Kol14,
Sam16, Hah18]. Since DC faults are symmetric loads, the implementation of the
inter-arm balancing controllers is not presented in detail. In the control model, the
horizontal and vertical balancing controllers are implemented and parameterised
similar to the literature [Hah18]. The parameters of the reference controllers are
summarised in the Appendix A.5 in Table A-3. The total energy balancing of the
converter is directly impacted by DC faults and therefore discussed.
In addition to the control of the energy stored within the converters, the MMCs
must ensure a stable DC voltage, or in other words balance the energy stored
within the DC network. Other important reference controls, which are presented
in detail, are the AC power controls.
5.2.1 Converter Energy Balancing
The energy stored within the converter and its SMs can be controlled via the
difference between the AC and the DC power (cf. (2.26)) [Hah18, Wen18]. Since
either the AC or the DC side is typically used to control the active power transfer
or the DC voltage, the other side must ensure that the average capacitor voltage
is within its limits. Hence, the control model of this work comprises both an AC
and a DC total energy balancing (TEB) PI controller. The corresponding block
diagram based on the relationship between the average SM voltage, the AC and
DC power given in (2.27) and the first-order approximations of the current
controllers given in (5.7) and (5.19) is illustrated in Figure 5-5. Additionally to
the plant and the current controllers, the control loop comprises a time delay
accounting for the measurement input AD conversion and an LPF [Sam16,
Hah18].
DC Energy Balancing Control
Disturbance Plant
Converter energy DC current
ܲ୪୭ୱୱ
control (DC side) control loop
‫כ‬ ݅ୢୡ ܲୢୡ
݅ୢୡ ͳ ͳ
‫୍ܭ‬ǡ୉ୢୡ
‫୔ܭ‬ǡ୉ୢୡ ൅
‫ݏ‬ ͳ ൅ ‫୍ܶݏ‬ୢୡ ͵‫ܥ‬ௌெ ܰ‫ݏ‬
ܲୟୡ ‫ݑ‬ௗୡ ܲୟୡ
AC Power
‫ݑ‬ୢୡ
Feed Forward
uത c
uത cଶ
AC Energy Balancing Control
Disturbance Plant
‫ݑ‬ଶ Converter energy AC current
ܲ୪୭ୱୱ
control (AC side) control loop
‫כ‬ ݅ୟୡǡୢ ܲୟୡ
݅ୟୡǡୢ ͳ ͳ
‫୍ܭ‬ǡ୉ୟୡ
‫୔ܭ‬ǡ୉ୟୡ ൅
‫ݏ‬ ͳ ൅ ‫୍ܶݏ‬ୟୡ ͵‫ܥ‬ௌெ ܰ‫ݏ‬
ଷ
ܲୢୡ ଶ
‫ݑ‬ୟୡ ,d ܲୢୡ
DC Power ͵
Feed Forward ʹ ‫ݑ‬ୟୡǡୢ
Meas.
݁ ି௦்ి
filtering
Computation time step
Figure 5-5: Block diagram of the total converter energy balancing control loops
Analogous to the controller parameter design of the current controllers the non-
compensable delays and filter time constants are combined to one first-order
element with the corresponding time constant Td,Eac and Td,Edc defined in (5.20)
Td,Eac = 2Td,Iac + Tc + TLPF,c ≤ 7Ts + 2TLPF,ac + TLPF,c (5.20)
Td,Edc = 2Td,Idc + Tc + TLPF, ≤ 7Ts + 2TLPF,dc + TLPF,c (5.21)

Under the assumption that the DC voltage is controlled to the DC reference
voltage by an adjacent MMC (udc = Udc,r) and a stiff AC voltage (uac,d = Uac,d,r),
both systems can be characterised by IT1-elements, as shown in (5.22) and (5.23).
KS 3ൗ U
GP,Eac ሺsሻ = = 2 ac,d
sTN,Eac ∙ (1 + sTd,Eac ) s3NCSM ∙ ൫1 + sTd,Eac ൯ (5.22)
KS Udc
GP,Edc ሺsሻ = = (5.23)
sTN,Edc ∙ (1 + sTd,Edc ) s3NCSM ∙ ൫1 + sTd,Edc ൯
A common PI tuning method for the control of IT1-systems is the symmetrical
optimum method [Hah18, Wen19]. For a fast but also robust control system, the
phase margin is set to φPM = 60°19. The resulting control parameters for the AC
and the DC converter energy controllers are given in (5.24) – (5.27).
TN,Eac 2NCSM KP,Eac
KP,Eac = = (5.24) KI,Eac = (5.25)
aKS Td,Eac aUac,d Td,Eac a2 Td,Eac
TN,Edc 3NCSM KP,Edc
KP,Edc = = (5.26) KI,Edc = (5.27)
aKS Td,Edc aUdc Td,Edc a2 Td,Edc
5.2.2 DC Reference Controls
DC Voltage Control
According to (2.41) and (2.42) the DC voltage can be controlled via the DC
current and respectively via the DC power. Thus, the DC voltage can be either
controlled directly via the DC side or via the AC side. Even though a DC voltage
control via the AC side is a common approach also for MMCs, it results in a
complex control loop, since the DC voltage is not only controlled via the AC
current control, but also via the DC-side converter energy balancing.
Consequently, a direct DC voltage control via the DC current loop, which does
not comprise an energy control in its control loop, gives a better dynamic response
19
A phase margin of φPM = 60° corresponds to a = (sin(φPM)+1)/(cos(φPM)) = 3.75
[Hah18]. Hence, the latter control option is used within this work and the
corresponding controller design is presented in the following.
Figure 5-6 illustrates the DC voltage control loop based on (2.16) and (2.41). The
current controller and the DC current model are represented with the first-order
approximation derived in (5.19). The currents of the line connected to the
DC-PoC defined in (2.41) are regarded as disturbance terms.
Disturbance Plant
௡
DC voltage DC current ෍ ݅௅ǡଵ௜

control control loop ௜ୀଶ
‫כ‬ ‫ݑ‬ୢୡ
݅ୢୡ ͳ ݅ୢୡ ͳ
‫כ‬
‫ݑ‬ୢୡ ‫୍ܭ‬ǡ୙ୢୡ
‫୔ܭ‬ǡ୙ୢୡ ൅ ‫ܥݏ‬ୢୡ
‫ݏ‬ ͳ ൅ ‫୍ܶݏ‬ୢୡ
Meas.
݁ ି௦்ి
filtering
Figure 5-6: DC voltage control loop (via DC side)

Analogous to the controller parameter design of the current controllers the non-
compensable delays and filter time constants are combined to one first-order
element with the corresponding time constant Td,Udc, which is defined in (5.28).
Td,Udc = 2Td,Idc + Tc + TLPF,dc ≤ 7Ts + 3TLPF,dc (5.28)
Hence, the IT1-system given in (5.29) characterises the dynamic behaviour of the
DC voltage plant.
KS 1
GP,Udc ሺsሻ = = (5.29)
sTd,Udc ∙ (1 + sTd,Idc ) sCdc ∙ ൫1 + sTd,Idc ൯
In line with the converter energy balancing controllers, the PI controller is tuned
using the symmetrical optimum method with a phase margin of φPM = 60°. The
resulting parameters are presented in (5.30) and (5.31).
Td,Udc Cdc KP,Udc Cdc
KP,Udc = = (5.30) KI,Udc = = 2 2 (5.31)
aKS Td,Idc aTd,Udc aTd,Udc a Td,Udc
The DC dynamic response of the DC voltage control can be summarised by first-

order approximation.
1 1
GC,Udc (s) = -1 ≈ (5.32)
1 + GO,Udc (s) 1 + aTd,Udc s
Active and Reactive Power Control
Since the AC current controller is implemented in a dq reference frame rotating

with the angular speed of the grid ωg and its d-axis aligned on the grid voltage
vector, the reference current components iac,d* and iac,q can be directly used to
control the active and reactive power separately. The active and reactive power
can be calculated based the instantaneous power theory, as shown in (5.33) and
(5.34) [Teo11, Sha16].
3 3
Pac = ൫uac,d iac,d + uac,q iac,q ൯ ≈ uac,d iac,d (5.33)
2 2
3 3
Qac = ൫uac,q iac,d – uac,d iac,q ൯ ≈ – uac,d iac,q (5.34)
2 2
Consequently, the active and reactive power reference P* and Q* can be accurately
tracked by closed-loop PI controllers. The second-order approximation of the PQ
plant’s transfer function is given in (5.36) with the corresponding time constant
Td,PQ of the non-compensable delays and filters defined in (5.35).
Td,PQ = Tc + TLPF,PQ ≤ Ts + TLPF,PQ (5.35)
KS 3ൗ u
GP,PQ ሺsሻ = = 2 ac,d (5.36)
(1 + sT1 )(1 + sT2 ) ൫1 + s2Td,Iac ൯൫1 + sTd,PQ ൯
Assuming that the filter time constant Td,PQ is larger than the time delay of the
inner AC current control loop (Td,PQ > TIdc ≈ 2Td,Iac ≈ 6Ts + 2TLPF,ac), the control
parameters are derived using the modulus optimum method, as given in (5.37) and
(5.38).
T1 Td,PQ KP 1
KP,PQ = = (5.37) KI,PQ = = (5.38)
2KS T2 6uac,d,nom Td,Iac T1 6uac,d,nom Td,Iac
5.2.3 Grid Forming Control
In case an MMC is used for the evacuation of renewable energy sources from
remote locations which are not directly or only weakly connected to an AC power
grid, e.g. offshore wind power plants, it is required that the corresponding MMC
provides a grid forming functionality. Contrary to the grid following operation,

the control is not tracking, but setting the grid frequency and the voltage
amplitude in this operation mode.
By simplifying the AC network to one effective network capacitance Cac, the
voltage dynamics of the grid can be described by (5.39) and (5.40), with iac and
uac being the current and voltages at the AC-PoC and ig,i being the sum of the
distributed consumers and sources [Qor18].
n
duac,d 1
– ωg uac,q = ൭iac,d – ෍ ig,d,i ൱ (5.39)
dt Cac
i=1
n
duac,q 1
+ ωg uac,d = ൭iac,q – ෍ ig,q,i ൱ (5.40)
dt Cac
i=1
To regulate both positive and negative sequence of the AC grid, the cascaded
voltage control is integrated in the DDSRF AC current control presented in
section 5.1 (AC Current Control). The PLL is substituted by an oscillator with a
fixed angular frequency ω*, to generate the grid frequency [Sch18].
Since the measurement values of the distributed source currents ig,i are typically
not accessible for the control, they cannot be integrated as feed forward, but have
to be regarded as disturbance. The resulting plant model for the GFC can be
characterised by the IT1-system given in (5.42), where Td,GFC summarised the
dynamics of the inner current control loop, the non-compensable delays and filters
(cf. (5.41)).
Td,GFC = 2Td,Idc + Tc + TLPF,dc ≤ 7Ts + 3TLPF,ac (5.41)
KS 1
GP,Udc ሺsሻ = = (5.42)
sTUac ∙ (1 + sTd,GFC ) sCac ∙ ൫1 + sTd,GFC ൯
Analogous to the DC voltage controller, the PI controller is tuned using the

symmetrical optimum method with a phase margin of φPM = 60°. The resulting
parameters are presented in (5.43) and (5.44).
TUac Cac KP,GFC
KP,GFC = = (5.43) KI,GFC = (5.44)
aKS Td,GFC aTd,GFC aTd,GFC
MTDC Fault Separation Strategy 71
6 MTDC Fault Separation Strategy
A key objective of this work is the evaluation and enhancement of the FBC-based
protection strategy. As shown in Figure 6-1, after the fault detection and the
localisation of the faulted line, the key building blocks of the protection strategy
are the fault control, the fault separation and the grid restoration. Based on a
detailed analysis of each phase, a fault control concept, suitable FSU options and
corresponding protection logics as well as methods for the post-fault restoration
of the DC grid must be elaborated. The individual aspects are incorporated into
protection strategies adjusted to the needs of the FSU technologies and the grid
restoration methods.
Fault Propagation
Fault Detection Development
Fault Localisation & Enhancement
Fault Control FBC-based
Open FSU Protection
Grid Restoration Strategy
tf tdet tloc tsep trst
Figure 6-1: Overview of the development and enhancement of the protection strategy
The development of the building blocks of the protection strategy are carried out
in the meshed test network, which also comprises a radial feeder, if not indicated
differently.
6.1 DC Fault Control for Fault-Blocking Converters
Depending if a DC fault is inside or outside of a FBC’s protection zone

(cf. section 3.1), the converter has to
x suppress its fault current contribution to zero, support the fault
separation process and after fault separation restore the remaining part
of the protection zone,
x ride through the fault without protection actions and ensure it’s safe
operation by limiting it’s DC current.
Figure 6-2 illustrates the required response of FBCs to a DC fault inside and
outside of their protection zone. In case of a DC fault in the protection zone PZ2,
C2, which is located within PZ2 takes protective actions, while C1, which is
associated to PZ1, has to ride through the fault until the two protection zones are
separated from each other, e.g. by a DC CB located between PZ1 and PZ2.
C1
No protection action
• FRT operation PZ1
• DC current limitation
Protection action PZ2

C2
• Fault current suppression
• Support fault separation
• Grid restoration
Figure 6-2: Overview about the protection action of FBCs in case of a DC fault
Within this section, the DC current limitation and DC fault control methods are
developed, which enable the FBCs to fulfil their tasks.
6.1.1 DC Current Limitation
To enable a DC-FRT during a fault outside of a converter’s protection zone and

to ensure its safe operation in case of an undetected DC fault, the control needs to
limit the converter’s DC current output. Even though the safe operation of the
converter could be ensured by blocking all the FB-SM, converter blocking is only
regarded as a backup protection option to avoid the interruption of the converter’s
controllability and hence the reactive power support to the AC system.
The proposed control structure (cf. chapter 5) permits a direct limitation of the
DC reference current to Idc,max, as presented in Figure 6-3 and Figure 6-420. In
addition to the current limitation, the control has to ensure that the converter
currents and voltages as well as the stored energy do not exceed their limits during
a DC-FRT. In case the TEB is controlled via the AC side, e.g. if the DC voltage
is controlled via the DC current (cf. Figure 5-6), no additional measures have to
be taken.
However, in case a converter balances its total energy via the DC current control,
e.g. if the active power is controlled via the AC side, the DC current limitation in
combination with the DC voltage breakdown impedes the TEB function. Hence,
a capacitor voltage limiting PI controller, as shown in Figure 6-3, is added to the
generation of id*, adjusting the d component of the AC reference current in case
20
Since the critical design fault case for the DC current limitation is a PPG fault at the DC busbar
transfer function of the DC network (Gdc(s) = 1/sC) is substituted by RFlt in Figure 6-4 and Figure 6-3.
the average capacitor voltage exceeds a predefined upper or lower boundary, e.g.
uത c,op = ሾ0.9 1.1ሿ p.u.
‫ݑ‬ୢୡ
DC Control ܴ୊୪୲
DC current
limitation ‫ݑ‬ୢୡ DC plant
ଶ ‫כ‬
ሺuത c ሻ ‫כ‬
݅ୢୡ ݁ୢୡ ݅ୢୡ ܲୢୡ
TEB DC current ͳ ͳ
controller controller ܴୢୡ ൅ ‫ܮݏ‬ୢୡ ͵‫ܥ‬ௌெ ܰ‫ݏ‬
ܲୟୡ Converter
‫ݑ‬ଶ
Energy Plant
AC Control
Active power ‫ݑ‬ୟୡ AC plant
‫כ‬
controller ݅ୟୡ ݁ୟୡ ݅ୟୡ
AC current ͳ
controller ܴୟୡ ൅ ‫ܮݏ‬ୟୡ
DC voltage
controller ͵
‫ݑ‬
ʹ ୟୡ
ܷୡǡ୫୧୬
λ ‫୍ܭ‬ǡ୉୪୧୫
‫୔ܭ‬ǡ୉୪୧୫ ൅
Ͳ ‫ݏ‬
ܷୡǡ୫ୟ୶
‫ݑ‬ଶ
Figure 6-3: Block diagram of the DC current limitation (TEB via DC current control)
DC Control DC current
limitation ‫ݑ‬ୢୡ DC plant
‫כ‬ ‫כ‬
݅ୢୡ
udc DC voltage ݅ୢୡ DC current
݁ୢୡ ͳ ‫ݑ‬ୢୡ
ܴ୊୪୲
controller controller ܴୢୡ ൅ ‫ܮݏ‬ୢୡ
AC Control ‫ݑ‬ୟୡ AC plant ܲୢୡ

‫כ‬ ݁ୟୡ
‫כ‬ ݅ୟୡ ݅ୟୡ ܲୟୡ
ሺuത ଶc ሻ Active power AC current ͳ ͳ
controller controller ܴୟୡ ൅ ‫ܮݏ‬ୟୡ ͵‫ܥ‬ௌெ ܰ‫ݏ‬
͵ Converter
‫ݑ‬ଶ ‫ݑ‬
ʹ ୟୡ Energy Plant
Figure 6-4: Block diagram of the DC current limitation (TEB via AC current control)
The FRT of an undetected DC fault is presented in Figure 6-5 for a converter in
DC voltage control mode (left) and in active power control mode (right). For the
DC current limitation, the critical design fault is a bolted PNG fault at the DC
busbar while the converter transfers its rated power from the AC to the DC side,
as this fault causes the highest surge current. The current limitation functions are
demonstrated in the meshed test network with converter C1 (DC voltage control
mode) and C2 (active power control mode). The power reference of C2 is set to
PC2* = 1200 MW while both C3 and C4 are set to PC3* = PC3* = -1200 MW, to
generate the critical power flow regarding the current limitation for both FBCs
under test. In both cases the critical design fault occurs at the corresponding DC
terminal and is removed after an exemplary time of Δtflt = 100 ms.
Figure 6-5: DC-FRT with DC current limitation during an undetected PNG busbar fault;
DC terminal voltage, DC terminal current, converter arm currents with arm current
protection limit (dashed red line), average capacitor voltage per arm
The voltage breakdown at tsim = 0 ms instantaneously results in a transient of the
DC and the arm currents. Due to the total DC inductance21, the initial transient
arm current is limited to iarm,max ≈ 2.5 kA and therefore does not exceed the
internal protection limit of Iarm,max = 0.9 ∙ IIGBT,max = 2.7 kA. After this transient,
the control limits the DC current to idc,T = Idc,max = 1.1 p.u. At tsim = 100 ms the
21
The fault current limiting inductance for a pole-to-pole fault is LDC = 2/3 Larm + 2 LDC,T (cf. (2.16)).
fault is cleared and the converters are able to restore the DC grid voltage and the
active power transmission to their pre-fault values. In both cases, all SM voltages
are maintained within a band of uc = [1.5 2.4] kV during the fault operation and
the restoration process. Since the critical design fault demonstrates that the
developed control and the converter layout enable DC-FRTs respecting the
converter’s voltage and current component limits, the internal converter currents
and voltages are not discussed in detail in the following sections. During all
following DC fault handling processes, the internal converter protections (cf.
section 4.2) are active but never trip.
6.1.2 DC Fault Control Methods
Contrary to DC faults outside of a converter’s protection zone, the detection of a

fault within its protection zone immediately trips its DC fault operation. The
required response of the converter depends on the different fault handling and
separation concepts and specific fault scenarios, e.g. the type or the location of
the fault. To minimise the energy input into the faulted protection zone and
generate near-zero voltage and current conditions for the FSUs the DC fault
control needs to enable:
x a rapid limitation of the injected current into the DC network, which
requires a suppression of the converters DC terminal current,
x a fast discharge of the faulted pole, which requires the control of the
DC terminal voltage,
x the suppression of the fault current flowing through the FSU to be
opened, which requires controlling the corresponding line current.
To accommodate all these requirements, a cascaded fault control concept
enabling a high degree of flexibility as well as a rapid transition between different
fault operation modes is elaborated. An overview about the concept, which is
presented in detail in the following sections, is given in Figure 6-6.
Terminal Current Control (TCC)
If a DC fault is detected within the protection zone of the FBC, the converter shall
limit its energy input into the faulted DC network as fast as possible. Within the
proposed control structure this DC terminal current control (TCC) is realised by
setting the DC reference current to idc* = 0 A [Ruf19a, Wen19]. Consequently, the
DC power cannot be used for the energy balancing control during DC fault
operation. Even though a capacitor voltage limitation, as shown in Figure 6-3,
FBC FSU
A
V A
A
u*DC
i*DC,L PI PI PI
iDC,L uDC iDC uDC xflt
Line Terminal Terminal

Current Voltage Current
Control Control Control
Figure 6-6: Illustration of the DC fault control concept

could be applied to maintain the capacitor voltage limits, the AC reference control
is changed to TEB22, since this approach facilitates a more stable capacitor voltage
during the fault operation. The DC current control parameters calculated in (5.17)
and (5.18) do not need to be adjusted, due to the unchanged current control loop.
Terminal Voltage Control (TVC)
Depending on the breaking capabilities and the counter voltage of the FSUs and
the grid restoration strategy the rapid control of the DC terminal pole-to-ground
or pole-to-pole voltage to zero is required. Using the proposed control structure,
this terminal voltage control (TVC) can be realised by changing the DC voltage
reference udc* to the required value, i.e. udc* = 0 V. For a fast response, the DC
voltage is directly controlled via the DC current, while the TEB is realised via the
AC current control. As a short circuit in the DC system changes the transfer
function of the DC voltage control loop, which is defined in Figure 5-6, it has to
be ensured that DC faults do not lead to instabilities. Hence, the requirements on
the stability margins have to be set accordingly. Since the control parameters
derived in section 5.2.2 are designed for a phase margin of φPM,U = 60°, the even
bolted pole-to-pole-ground faults at the DC busbar do not result in an instable
voltage control. Hence, the voltage control parameters are not changed for the
fault handling process.
Line Current Control (LCC)
To improve the application of FSUs with a limited or even no DC current

interruption capability, like vacuum circuit breakers design for breaking AC
22
To facilitate smooth control mode changes, the PI controller of the reference controllers are reset to
the output value of the previously activated reference control.
currents, and to reduce to fault separation time, the DC fault control cascade is
extended by a line current control (LCC), as shown in Figure 6-6 [Ruf18].
Therefore, the current flowing into the line which is to be separated is used as
reference of a PI controller generating the reference voltage forwarded to the DC
voltage controller (cf. Figure 6-6).
The tuning of the LCC is, however, not as straight forward as for the other control
loops, since on the one hand, transmission lines are highly frequency dependent
and on the other hand, the control loop parameters change with the fault location.
For the derivation of the control parameters the faulted line can be represented by
a pi-model with a suitable approximation of the frequency characteristics [Sem85,
Bee16]. Transmission line short-circuits cause voltage and current traveling
waves which reflect between the line terminal and the fault location. Therefore,
every fault location is associated with a specific frequency spectrum with a
dominant natural frequency component23. Thus, the faulted transmission line can
be simplified to a pi-model corresponding to this natural frequency. A simplified
control loop for the LCC with a fault at xflt (cf. Figure 6-6) is given in Figure 6-7.
DC line DC voltage
current control control loop Faulted line
‫כ‬
݅ୢୡ ͳ ‫ݑ‬ୢୡ ͳ ݅ୈେǡ୐
‫כ‬ ‫୍ܭ‬ǡ୐େେ
݅ୈେǡ୐ ൌͲ ‫୔ܭ‬ǡ୐େେ ൅
‫ݏ‬ ͳ ൅ ‫ܶݏ‬୙ୢୡ ܴ୤୪୲ ൅ ‫୐ܴݔ‬ᇱ ൅ ‫ܮݔݏ‬ᇱ୐
Meas.
݁ ି௦்ి
filtering
Figure 6-7: Simplified line current control loop

For the parameter design of the LCC, the open loop plant is represented by a first-
order approximation the time delays, as given in (6.1), and the simplified transfer
function of the line model corresponding to the fault location xflt as given in (6.2).
Td,LCC = TM + TLPF = Ts + TLPF,dc (6.1)

1
xflt R'L (xflt ) + Rflt
GLine (s, xflt )= ǡ (6.2)
xflt L'L (xflt )
1 +s
xflt R'L (xflt ) + Rflt
23
The dominant natural frequency of a transmission line is the lowest order harmonic of its frequency
spectrum [Hez14].
with RL’(xflt) and LL’(xflt) representing the pi-model parameters corresponding to

the dominant natural frequency of the transmission line at the fault location xflt
and Rflt representing the fault resistance. Even though (6.2) indicates that the
optimum control parameters depend on the distance between the converter and
the fault location, a change of the LCC control parameters depending on the fault
location is not regarded as a robust solution. Although methods have been
developed to localise the location of a fault on a transmission line, the
computation time of these localisation methods as well as their limited robustness
do not permit the application of this information within the protection strategy.
Within this thesis a simple but robust parameterisation based on the worst-case
fault location regarding the stability of the control loop (at xflt = 0 km and a fault
resistance of Rflt = 0.1 Ω) is used. Consequently, the plant can be characterised by
the PT2-system shown in (6.3), which is comprising the DC voltage control loop
given in (5.32), the fault resistance and the non-compensable time delay Td,LCC.
GP,LCC ሺs, 0 kmሻ = GC,Udc (s) ∙Gd,LCC (s) ∙GLine (s, 0 km)
1 1 1 (6.3)
= ∙ ∙
1 + aTd,Udc s 1 + Td,LCC s Rflt
The control parameters can be deduced by applying the modulus optimum method
[Baj08]:
aTd,Udc Rflt 1
KP,LCC = (6.4) KI,LCC = (6.5)
2 Td,LCC aTd,Udc
6.1.3 Analysis of the DC Fault Control Methods
The impact of the different DC fault control methods on the system behaviour
during a DC fault is presented in Figure 6-8 for an exemplary low-impedance
PNG fault in the middle of line L14 of the meshed test network. Thereto, the
terminal voltage and current of converter C1 (operating in Udc-control mode) as
well as the line current flowing through the FSU14 are analysed.
In all cases, the voltage breakdown at tsim = 0 ms causes the tripping of the fault
detection after Δtsim = 0.86 ms. Subsequently, C1 is set to TCC with a reference
current Idc,T* = 0 p.u. for all three cases. During case (a), the control mode remains
in TCC for the entire simulation. The FBC is able to suppress the terminal current
within a band of |idc,T| < 0.05 p.u. within a settling time of ΔtTCC,Iset(5%) ≈ 2.2 ms.
Since all converters suppress their DC current, the DC network passively
discharges via the fault location. Consequently, the line voltage passively decays
and settles within |udc,L| < 0.05 p.u. within ΔtTCC,Uset(5%) ≈ 22 ms after fault
detection.
After the IED localises the fault on line L14 at tloc ≈ 2.6 ms the TVC is activated
in case (b) and (c). Contrary to (a), the converter supports the DC network
discharge process by draining energy from the grid. Nevertheless, the TVC can
cause a persistent DC offset in the line current, as shown in Figure 6-8 (b), which
might prevent an FSU with no or very limited DC current interruption capability
from separating the faulted line. Case (c), however, shows that the residual line
current can be suppressed controlling the line current to Idc,Line* = 0 A
subsequently to the grid discharge. Thereby, the line current as well as the
terminal voltage is limited to a band of ± 0.05 p.u. in ΔtLCC,set(5%) ≈ 12.6 ms after
fault detection for this exemplary fault case.
TCC
TVC
LCC
Figure 6-8: Demonstration of the control modes at converter C1 for an exemplary low-
impedance PNG fault in the middle of line L14 of the meshed test network
In addition, the performance of the different control concepts is evaluated based
on a systematic variation of the fault location, type and resistance in the meshed
test network (cf. section 4.1). The impact of the different control modes on the
current flowing through the four FSUs, which shall separate the fault, and the
corresponding terminal pole-to-ground voltages is shown in detail in Appendix
A.6 for all 48 fault cases in the meshed network.
To quantify the performance of the fault control methods, Figure 6-9 displays the
time until the FSU currents and the corresponding terminal voltages settle within
a band of y(t) ≤ [0.10 0.05 0.02] p.u. The comprehensive analysis confirms the
observations of the exemplary fault cases shown in Figure 6-8. Since the TCC
suppresses the DC current injection of the converters into the faulted DC network,
the voltages of the faulted pole discharge via the fault and the voltages of the
healthy pole remain close to their nominal value (cf. PG faults). Thereby, the FSU
currents and terminal voltages decay to a band of |y| < 0.05 p.u. within
ΔtTCC,Uset(5%) ≈ 23 ms and ΔtTCC,Iset(5%) ≈ 36 ms. By actively discharging the grid
using the TVC, the settling time of the voltage can be reduced to
ΔtTCC,Uset(5%) ≈ 21 ms. Nevertheless, the remaining voltage error can cause
persistent FSU currents, which can be in the order of a few hundred amperes.
Case (c) shows that controlling the line current via the LCC, reduces the settling
time of the FSU currents while maintaining the voltage suppression performance.
Figure 6-9: Boxplots of the settling times of the FSU current and the corresponding
terminal voltages for all 48 fault causes in the meshed network under variation of the fault
control mode; whiskers with maximum 1.5 interquartile range (IQR) and outliers
Based on the comprehensive fault analysis, it is confirmed that the subsequent
application of the TVC and the LCC algorithm does improve both the suppression
of the current flowing into the faulted line as well as the terminal voltage.
Accordingly, the combination of both algorithms is henceforth used for

establishing near-zero of current and voltage conditions prior to the tripping of
the FSU.
6.2 Analysis of Fault Separation Units
A key motivation for the application of fault-blocking instead of fault-feeding

converters in MTDC networks is to reduce the requirements on the DC
switchgear, i.e. the FSUs, by creating near-zero voltage and current conditions
prior to the fault separation. Since the interruption of residual currents created by
a controlled discharge of the DC grid represents a new challenge for HVDC
switchgear, it is necessary to define requirements on the FSUs, examine the
available switchgear technologies regarding their applicability and their impact
on the performance of the fault separation process.
6.2.1 Requirements on FSUs
For the deduction of the requirements on FSUs in MTDC systems protected by

FBCs, the generic fault handling process, illustrated in Figure 6-10, is analysed.
Immediately after fault inception, the voltage collapses. Even though the fault
current contribution from the FBC is limited and can be quickly suppressed to
values close to zero, the discharge of the transmission system’s line capacitance
can cause surge currents in the order of a few tens of kiloamperes flowing through
the FSUs. After the initial surge current, the DC terminal voltage and the current
flowing through the FSUs, which shall separate the fault, are controlled to values
close to zero.
Surge current due to
Current network discharge
Limitation iFSU
Residual (DC) current
FSU interruption
FBC
iDC,T t
uDC,T
Interruption at
uDC,T
residual (DC) voltage
iFSU
t
Figure 6-10: Generic fault current interruption process

Despite of the fault control, the FSU might still have to interrupt a residual DC
current, e.g. in case the FSU current asymptotically decays to zero due to a highly
damped fault current loop. After the fault separation under near-zero current and
voltage conditions, the FSU must isolate the faulted line before the DC voltage
within the healthy part of the protection zone can be restored. Consequently, five
main requirements are identified for FSUs applied in the FBC-based protection
system [Ruf19a]:
Residual (DC) Current Interruption Capability: After the suppression of
the current flowing into the faulted line (caused by the natural discharge
of the grid and the FBC fault control), the corresponding FSUs must be
able to interrupt the residual fault currents. If current-zero crossings cannot
be guaranteed by the protection scheme, the FSUs must be able to interrupt
residual DC currents and provide a TIV.
Voltage Withstand Capability: The FSUs must withstand the TRV occurring
after fault separation and absorb the stored residual energy of the circuit.
Current Withstand Capability: The magnitude of the surge current strongly
depends on the type of fault and the network configuration and can be in
the order of a few tens of kiloamperes. Even though the FSUs only have
to interrupt residual currents they must be able to carry these surge currents
caused by the natural discharging process of the line capacitance.
Isolation: After the fault separation, the FSUs must build up an insulation
capability against the full DC voltage.
Speed: To limit the effect of DC contingencies on the surrounding PoC to a
temporary stop P (cf. section 1.2.3 and [CEN18]), the FSUs must facilitate
a fast fault separation. Since the grid restoration cannot commence before
the relevant FSUs have gained their full insulation capability a fast
isolation process is required as well.
In order to fulfil these requirements, the FSU can be separated into two functional
sections: A residual current breaker (RCB) to separate and a fast disconnector
(FD) to isolate the faulted line [Ruf19a]. The switchgear technology options for
the RCB can be classified into two main groups:
1. Low-voltage and low-energy DC CBs – like solid-state, hybrid or
resonant DC CBs – with reduced requirements regarding current
interruption, TIV withstand and energy absorption capability compared
to full-size DC CBs,
2. Conventional AC CBs – like vacuum or SF6-CBs
To ensure a fast isolation of the faulted line after its separation, fast disconnectors
like the UFD, which is driven by electromagnetic actuators, can be applied in the
FSU. Since existing disconnecting switching technologies typically have similar
current interruption capabilities (iint < 1 A), the main impact of the choice of the
technology is the opening speed. This opening speed is not relevant for the fault
separation, but determines the time when the grid restoration can be initiated.
6.2.2 Low-Voltage and -Energy DC Circuit Breakers
Fault control sequence and tripping logic
To apply DC CBs with reduced voltage ratings and energy absorption

requirements compared to full-size DC CBs, it has to be ensured that the current
and voltage conditions are reduced sufficiently before tripping the RCB. For the
interruption of the residual DC currents, the counter voltage of the RCB must be
higher than the electromotive force of the fault current loop (typically
uRCB,SA,r ≥ 1.5 uEMF [CIG17a]). If this voltage condition is fulfilled, the maximum
energy absorption of the RCB is directly linked to the interrupted current (cf.
(2.46)). Therefore, it must be ensured that the current is reduced to a threshold
which corresponds to the energy limit of the SA prior to the residual current
interruption. It is shown in Figure A-3 and Figure 6-9 that both the terminal
voltage and the current flowing through the FSU can be suppressed to such
predefined thresholds by the sequential application of the TVC and LCC
algorithms.
A fault separation sequence respecting the RCB interruption requirements is
shown in Figure 6-11 for converters connected to a multi-terminal busbar (left)
and a radial connection (right). After fault detection every converter suppresses
its DC current to zero (TCC). If a fault is localised on a transmission line directly
connected to a converter, this converter’s control is changed to TVC to limit the
DC pole voltage below the RCB voltage interruption threshold. After the voltage
condition is fulfilled, the FBC switches to LCC to suppress the current flowing
through the FSU below the current interruption threshold. Since the terminal
current is identical to the line current for converters connected to a single line, the
control mode is changed to TCC, which has a higher dynamic performance
compared to the LCC. After a successful fault separation, the control mode of an
FBC connected to a multi-terminal busbar is set to TCC to control the current to
zero until the grid restoration commences. Since an FBC, which has been
connected to a single line prior to fault separation, is connected to an open
terminal after the separation of its transmission line, it cannot control its DC
current anymore. Hence, the control is changed to STATCOM operation (TVC).
To ensure the safe operation of the RCB and the FD the tripping logic shown in
Figure 6-12 is integrated into the protection IEDs. The residual (DC) current
interruption capability of disconnectors is typically very limited – in the order of
a few hundred mA [CIG17a]. In order to ensure a safe operation of the FD, a
current interruption threshold IFD,thres is added to the FSU logic. The FD

interruption threshold is set to IFD,thres = 0.5 A.
Multi-Terminal Connection Radial Connection
DC Fault Detection DC Fault Detection
Fault Control Mode: Fault Control Mode:

Terminal Current Zero Terminal Current Zero
DC Fault DC Fault
Identification Identification

Terminal Voltage Zero Terminal Voltage Zero
false |uDC,pole| ≤ Uthres false |uDC,pole| ≤ Uthres

true true
Line Current Zero Terminal Current Zero
Trip FSU Trip FSU
false FSU open false FSU open

true true
Fault Control Mode: Control Mode:
Terminal Current Zero STATCOM
Figure 6-11: Fault separation logic for a converter connected to a multi-terminal DC bus
(left) and a radial connection (right)
Residual Current Breaker Tripping
true false
|iRCB| < IRCB,thres true
Trip FSU If true for thold Trip RCB
|uT| < 2/3 USA,p
true
Fast Disconnector Tripping

false
true true
|iFD| < IFD,thres If true for thold Trip FD
Figure 6-12: Tripping logic for FSUs based on low-voltage and -energy DC CBs
Fault Separation Process
The fault separation process is presented for an RCB rated for the interruption of
residual fault currents below IRCB,thres = 100 A at a DC voltage of URCB,int = 10 kV.
Figure 6-13 (left) shows the current through the FSUs, which shall separate the
faulted line (4 per simulation case), the corresponding DC terminal voltages and
the corresponding voltage across the RCB for all 48 fault scenarios of the meshed
test network.
TCC TVC LCC TCC
Figure 6-13: Fault separation process for an DC CB-based FSU with IRCB,thres = 100 A and
URCB,int = 10 kV; FSU currents, terminal voltages and TIVs for all fault cases in the meshed
network configuration (left) and at FSU12 for a low-impedance PG fault in the middle of
line L12 (right)
It is shown that the FSU currents and the corresponding terminal voltages are
reduced below the FSU interruption thresholds enabling a fault separation in less
than Δtsep < 40 ms after fault inception. The maximum current, which has to be
carried, but not separated by the FSUs is iFSU,max = 25.75 kA and the maximum
voltage across the RCBs is TIVmax = 15.41 kV.
For a detailed discussion, the voltages and currents corresponding to the FSUs at
T1 in case of a low-impedance PG fault (RF,PG = 0.1 Ω) in the middle of line L12
are highlighted in Figure 6-13 (left) and shown in detail in Figure 6-13 (right) –
please notify that the scaling of the FSU current is adjusted in Figure 6-13 (right)
for a better visibility of the induvial events. The PG fault occurring at tsim = 0 ms
causes a collapse of the DC voltage on the positive pole across the entire DC
network. After the fault’s detection at Δtdet = 1.4 ms, the converter is set to TCC
and controls its DC current to iDC,T* = 0 p.u. As soon as the IED of terminal T1
localises the fault (Δtloc ≈ 3.2 ms) converter C1 starts to control the terminal
voltage of the positive pole to uDC,T,P* = 0 p.u. (TVC). Once the voltage of the
affected pole P is limited below the RCB voltage threshold uDC,T,P ≤ uRCB,thres = 10
kV, the converter switches to LCC and controls the FSU current to IDC,L12* = 0 A.
The opening condition of the FSU is fulfilled at tsim = 13.3 ms and the RCBs of
both poles are tripped. Once the RCBs open, the resulting TIV drives the line
current to zero and the fault is separated. Subsequently, the UFDs are tripped and
isolate the faulted line. Since C1 is connected to more than one line, the control
mode is set to TCC after triggering the FSU.
Sensitivity Analysis of the CB Type and Rating on the Fault Separation Time
For the deduction of suitable RCB ratings and switchgear technologies, the
sensitivity of the fault separation time on the RCB voltage and current ratings is
shown in Figure 6-14. Thereto, the SA protection voltage and hence the counter
voltage is varied between URCB,r = [10, 20, 50, 100] kV and the current
interruption threshold is varied between Ithres = [100, 200, 500, 1000] A. The
RCB opening time is set to ΔtRCB,O = 0.1 ms.
For each combination the worst-case fault separation time and energy absorbed
in the FSU’s SAs are identified based on the simulation of all 48 fault scenarios
in the 4-terminal meshed network in monopole configuration (cf. section 4.1). In
all simulation cases, the fault is correctly detected, located and successfully
isolated. The maximum fault separation time of all simulation cases is
Δtsep,max = 38.5 ms and occurs for the simulation case with minimal RCB ratings,
i.e. Ithres = 100 A and URCB,r = 10 kV. Even though it can be shown that the fault
separation time reduces with increasing RCB ratings, plateaus in Δtsep can be
observed if one of both thresholds is relatively small and the other threshold is
increased. In case the current interruption threshold is set to values of only a few
percent of the nominal DC current, the time it takes to fulfil the current
interruption condition dominates the fault separation time. This effect can be
observed for all cases with Ithres = 100 A, which show similar average and worst-
case fault separation times with a variation of the rated RCB voltage. The same
effect can be observed for the rated RCB voltage of URCB,r = 10 kV under
variation of Ithres.
40
I thres = 100 A
35 I thres = 200 A
Separation Time [ms]
I thres = 500 A
30
I thres = 1000 A
25
20
15
10
5
10 20 50 100
Rated RCB Voltage [kV]
Figure 6-14: Boxplots of the impact of the RCB ratings on the maximum fault separation
time tsep for the 48 fault cases in the meshed network configuration; whiskers with
maximum 1.5 IQR and outliers
As indicated by Figure 6-9 and shown in detail in Figure A-3 both the terminal
voltages as well as the FSU currents decay over time, if the terminal or the line
current are controlled to zero. Hence, the critical case regarding the energy
absorption of the RCB’s SA is a minimal RCB opening time, i.e. ΔtRCB,O = 0.1 ms.
Table 6-1 shows the maximum absorbed SA energy of all fault cases in the
meshed network scenario under variation of the RCB ratings. Since the absorbed
energy is linearly dependent on the inductance of the fault current loop, the
maximum line length lL12 = 350 km and maximum line impedance
Lcabel’(f = 0 Hz) = 3.5 mH/km are inserted into (2.46).
Table 6-1: Maximum absorbed SA energy in [kJ] of all fault cases in the meshed network
scenario under variation of the RCB ratings in comparison to the approximation of (2.46)
100 A 200 A 500 A 1000 A
Sim. Calc. Sim. Calc. Sim. Calc. Sim. Calc.
10 kV 16.1 18.4 28.7 73.5 108.8 459.4 150.5 1838
20 kV 10.9 18.4 20.7 73.5 37.4 459.4 38.1 1838
50 kV 2.8 18.4 19.4 73.5 25.3 459.4 28.7 1838
100 kV 0.4 18.4 0.75 73.5 0.3 459.4 0.4 1838
In all cases, the maximum energy absorbed in the RCB SAs is smaller than the
corresponding calculated estimation based on (2.46). Since the estimation
assumes a constant terminal voltage and FSU current, while in fact both values
decay during the current suppression period, (2.46) can be used to conservatively
approximate the required energy absorption of the RCB for specific voltage and
current interruption thresholds.
As the RCBs are able to interrupt the residual fault current within a few
milliseconds after they are triggered and the maximum absorbed energy is below
the calculated estimation in all fault cases, an additional opening delay of the
RCBs almost linearly increases the fault separation time. Moreover, the maximum
energy absorbed in the SA of the FSUs decreases with an increasing RCB delay
time due to the ongoing reduction of the FSU current and the terminal voltage.
The impact of the breaker opening time on the fault separation time and required
SA energy is presented in Figure 6-15 for an exemplary RCB rating (Ithres = 100 A
and URCB = 10 kV). While the current interruption and voltage rating remain
fixed, the breaker opening time is varied between Δtopen = [0.1, 2, 8, 20] ms,
corresponding to state-of-the-art DC CB concepts.
Figure 6-15: Sensitivity analysis of the CB opening time on the separation time tsep and the
energy absorbed in the RCB-SAs ESA all fault cases in the meshed network configuration;
RCB rating: Ithres = 100 A and URCB = 10 kV; whiskers with maximum 1.5 IQR and
outliers
Discussion
Since the maximum absorbed energy is below the calculated estimation

(cf. (2.46)) corresponding to the RCB rating, it is concluded that the combination
of the proposed control and the interruption conditions are suitable for RCBs
based on DC CBs. It is shown that the application of RCB with peak TIV ratings
in the range of 5…10 % of the nominal DC voltage and energy absorption
requirements in the order of a few tens of kilojoules can enable fault separation
times between 15…30 ms in both test networks. The choice of the specific DC
CB technology and its ratings, however, strongly depends on the requirements on
the speed of the protection system and hence on the fault separation time.
6.2.3 Conventional AC Circuit Breakers
To evaluate the applicability of AC CBs, i.e. vacuum and SF6 type CBs, as FSUs
in MTDC systems protected by FBCs, it is essential to comprehensively analyse
their interruption characteristics and the stresses imposed on the CBs in a wide
range of fault scenarios. Additionally, the impact of the AC CB type on the fault
separation performance is evaluated, possible weaknesses of the application of
AC CBs in the FBC-based protection strategy are identified and an enhancement
of the strategy is proposed to improve its reliability and performance.
Current interruption and withstand capabilities
For a successful interruption of the residual fault current, both AC CB types have
to dielectrically withstand the TRV occurring after current interruption. Since the
DC network discharges over time in case of a DC fault, the maximum TRV occurs
during a fast current interruption. Therefore, the dielectric withstand capability is
evaluated based on a very short opening time of ΔtACCB,O = 5 ms. In addition, the
breaker opening is triggered immediately after the localisation of the faulted line.
In contrast to the fault separation sequence used for the DC CBs, the fault control
mode is directly changed from TCC to LCC once the faulted line is located by the
protection IEDs. Due to its impact on the TRV, current chopping has to be
considered as a worst-case assumption in the analysis of the dielectric withstand
capability of the CBs. Hence, the chopping limits are set to Ichop = 10 A. To assess
the influence of the arc voltage on the TRV, a CB without any arc voltage and
with a maximum arc voltage of Uarc,max = 8 kV24 is considered. This comparably
high arc voltage is intendent to demonstrate the maximum impact of the arc’s
counter voltage on the current interruption process.
The assessment of the TRV is conducted in the meshed network. Since the
different impedance characteristics of OHL and cable systems can have an
influence on the TRV, OHL faults are respected by substituting the cables model
of line L12 with the OHL model.
24
It has to noted that an arc voltage of uarc = 8 kV will only occurring for low currents in very high
pressure CBs [Nak01]. The peak arc voltage of standard SF6-CB is typically in the range of
Uarc,max = 2…3 kV.
Figure 6-16 shows the FSU currents and the corresponding terminal voltages for
the defined fault scenarios in the meshed test network for (a) a AC CB with no
arc voltage and (b) a AC CB with a very high maximum arc voltage of
Uarc,max = 8 kV.
(a) ΔtCB,O = 5 ms & Uarc,max = 0 kV (b) ΔtCB,O = 5 ms & Uarc,max = 8 kV
Figure 6-16: FSU currents and terminal voltages for an AC CB-based FSU with an opening
time of ΔtCB,0 = 5 ms under variation of the maximum arc voltage Uarc,max = [0; 8] kV.
Once the fault currents decay to zero, the AC CBs interrupt these currents and
separate the faulted lines from the remaining network. Due to the current
interruption, the terminal voltages corresponding to the FSUs maintain their pre-
interruption voltage level, while the voltages on the line side drop to zero, which
causes the TRVs across the CB. As the arc voltage accelerates the separation
process in case (b), the terminal voltage after fault separation are higher in (b) as
in (a). For the assessment of the simulated TRV profiles and their comparison
with the standard IEC TRV envelopes, Figure 6-17 shows all TRV profiles
corresponding to Figure 6-16 with their time axis origin set to the corresponding
current interruption time for both AC CB cases as well as the profile
corresponding to the standard TRV test T10 of a class S2 CB with a rated voltage
of Ur = 72.5 kV. In addition, the maximum TRV, RRRV and ROCOC occurring
during the interruption process in all fault cases are given.
(a) ΔtCB,O = 5 ms & Uarc,max = 0 kV (b) ΔtCB,O = 5 ms & Uarc,max = 8 kV
uarc
Max. TRV [kV] 56.50 Max. TRV [kV] 61.65

Max. RRRV [kV/µs] 0.052 Max. RRRV [kV/µs] 0.057
Max. ROCOC [A/µs] 0.101 Max. ROCOC [A/µs] 0.180
Figure 6-17: TRV profiles during current interruption with AC CBs applied as FSUs; all
fault scenarios in the meshed network case with L12 as OHL
As the arc voltage in case (b) helps to reduce the fault separation time, the
maximum TIV, RRRV and ROCOC of case (b) are higher than in case (a). Hence,
the case (b) with extreme assumptions regarding the CB opening time of
ΔtCB,O = 5 ms and a maximum stable arc voltage of Uarc,max = 8 kV defines a
worst-case regarding the stresses imposed on AC CB-based FSUs during the
residual current interruption process. Since the RRRV slopes of the simulated
fault scenarios are more than two orders of magnitude smaller than RRRV values
for HVAC CBs defined by IEC25 [IEC18], it can be concluded that conventional
AC CBs are able to dielectrically withstand the voltage transients occurring
during the residual fault current interruption, if the maximum peak TRV does not
exceed the rated TRV peak of the CB.
The maximum ROCOC occurring during the current interruption process is
ROCOCmax = 0.18 A/µs, which is also more than ten times smaller than typical
critical current slopes of VCBs (dicrit/dt = 150…1000 A/μs [Hel96]). Hence, it can
be concluded that both conventional AC CB types are able to interrupt the residual
fault currents, if the contacts are fully opened and the FSU current has a current-
zero crossing (CZC).
25
E.g. the RRRV defined for T10 switching tests for AC-CBs with a rated voltage of Ur = 72.5 kV is
RRRVIEC,T10(Ur = 72.5 kV) = 8 kV/µs
Fault control sequence and tripping logic
In general, the same fault control and tripping logic as developed for the FSUs
based on low-voltage DC CBs (cf. section 6.2.2) is used in case AC CBs are
applied as FSUs. Since AC CBs can, however, only interrupt a residual fault
current at or near to a CZC, the no current interruption condition is applied.
The maximum TRV decreases with an increasing breaker opening time, due to
the prolonged discharging process of the DC network. Hence, depending on the
voltage rating of the AC CBs applied as FSU, it might be required to discharge to
pole voltages prior to fault separation. To ensure a safe operation of the CB, the
terminal voltage condition is set to the rated AC CB voltage (uthres = Ur,AC CB).
Sensitivity Analysis of the CB Type and Design on the Fault Separation Time
Apart from the information regarding the voltage and current stresses imposed on
the CBs during the current interruption process, Figure 6-18 demonstrates the
effects of the counter voltage provided by the arc voltage on the fault separation.
Even though all FSU currents are suppressed below IFSU < 200 A within 30 ms
after fault inception, the CB of case (a) cannot interrupt the residual DC fault
current. These currents are therefore only interrupted, once they decay below the
chopping limit of the CB. On the contrary, the CBs of case (b) separate all fault
currents within Δtsep < 29 ms, since the counter voltage created by the arc
suppresses the residual (DC) fault current to zero.
To assess the impact of the breaker type and design on the fault separation
performance the fault separation process in the meshed network is analysed for
exemplary VCB and an a high-pressure SF6-CB designs:
x VCB: Ur = 72.5 kV; tVCB,O = 8 ms; Uarc = 0 kV
x SF6-CB: Ur = 420 kV; tSF6,O = 20 ms ; Uarc,max = 8 kV
To reflect the worst-case regarding the current interruption, the current chopping
limit of both CBs is set to Ichop = 0 A.
As VCBs can be built with contact separation times in the range of a few
milliseconds, due to the short gap distance and the relatively light contacts, the
VCBs can separate faulted lines within a few to a few tens of milliseconds. The
simulations also show fault separation times which are higher than 100 ms. As
already shown in Figure 6-18, these cases are caused by residual DC fault
currents, which decay to zero over several tens to hundreds of milliseconds. Since
the FSU currents are relatively small compared to the nominal DC currents, the
errors of the PI controllers of the fault control are relatively small as well.
Therefore, the fault control with its defined stability margins is not able to
suppress the current to a CZC.
(a) VCB (b) SF6-CB
Figure 6-18: Sensitivity analysis of the AC CB parameters on the tsep for the 48 fault cases
in the meshed network configuration
As the terminal voltages corresponding to the residual FSU currents also decay
towards zero, arc voltages in the order of a few kilos can suppress the residual
fault current to zero and thereby facilitate a fast fault separation. However, it must
be noted that an arc voltage of up to 8 kV is a best-case assumption regarding the
counter voltage provided by an AC CB. It is intended to demonstrate the possible
benefits regarding the application of gas compared to vacuum CBs.
Discussion of the applicability of conventional AC CBs as FSUs in FBC-based

protection systems
The simulation results, indicate that conventional AC CBs can in general be

applied as FSUs in FBC-based protection systems. The comparison of the TRV
and the RRRV with the IEC TRV standard test requirements shows that the
dielectric stresses during the residual fault current interruption processes are
relatively small compared to requirements on CBs applied in HVAC transmission
systems.
From a system perspective the breaker types mainly differ regarding two aspects.
Firstly, the small opening times of VCB facilitates a faster fault separation
compared to SF6-CBs, if there is a sufficient number of CZCs. On the other hand,
the application of gas-based CBs can have a beneficial effect on the fault
separation, due to the arc and therefore counter voltages. Nonetheless, it is shown
that arc voltages in the order of several kilovolts, which can only be achieved by
very high-pressure gas-breakers, are required to reduce the maximum fault
separation time to the same order as the low-voltage DC CBs presented in section
6.2.2, because of the residual DC terminal voltage, which can be in the order of a
few kilovolts.
Hence, a critical aspect for the application of both CB types as FSUs in DC
networks, especially in terms of reliability, but also in terms of the performance
of the protection system, is the dependency of a successful fault separation on the
presence of CZCs.
AC current injection
The dependency of a successful fault separation on the DC systems’ damping and

the corresponding CZCs during a specific fault scenario does not meet the
robustness and reliability requirements on HVDC protection systems [CIG18a].
To facilitate the application of commercial AC CBs as FSUs in FBC-based DC
protection systems, CZCs must be guaranteed and not just be a result of the
system’s damping. Since FBCs are able to control the pole voltages with a high
degree of freedom, an injection of a small AC current into the DC system and
especially into the faulted line can increase the reliability and the speed of the
fault separation. The effect of such an AC current injection into the faulted line
on the current interruption is illustrated in Figure 6-19.
Standard fault control Fault control with AC injection
FSU Current
FSU Current
no current interruption current interruption
Time Time
FSU contact separation FSU contact separation
Figure 6-19: AC current injection concept using the FBC controllability

To enable a direct control of DC and sinusoidal values, resonant controllers
designed for the angular frequency of the reference AC current ωL are added to
the control concept described in section 6.1.2 [Pet17, Pet18, Stu18]. In case an
AC current injection into the faulted line is required, the line current reference is
changed from i*DC,L = 0 A to i*DC,L = i*DC,L ∙ sin(ωL t), as illustrated in Figure 6-20.
The reference of the injected AC line current comprises two degrees of freedom:
The amplitude iL and the frequency fL of the injected line current. Even though a
high line current frequency fL is beneficial for the current interruption process due
to the high number of generated CZCs, the frequency should comply to the
resonance characteristics of the short-circuited DC network26. To avoid an

interference of the line current control with the MMC’s inner current controls,
which comprise 50 Hz and 100 Hz components, it is recommended to avoid the
50 Hz harmonics as line current frequency. Even though high frequencies lead to
a large number of zero crossings and thus an accelerated current interruption, the
frequency of the injected AC current should be smaller than the bandwidth of the
underlying terminal voltage controller. Based on (5.32), the line current frequency
should be smaller than fU,dc < 1/(aTUdc) = 162 Hz). Thus, the line current
frequency is exemplarily set to fL = 120 Hz within this work.
The pre-investigations of the FSU currents shown in Figure A-3 and Figure 6-9,
indicate that an oscillating line current with a peak value of ÎDC,L* = 0.1 p.u. can
create CZC in all cases after ΔtTCC,Iset(10%) ≈ 28 ms.
FBC FSU
A
Resonant controller based fault control V A
A
u*DC
i*DC,L sin(ωLt) PIR PIR PIR
iDC,L uDC iDC uDC
Line Terminal Terminal

Current Voltage Current
Control Control Control
Figure 6-20: Illustration of a DC fault current control with AC current injection

To demonstrate the effect of the AC current injection on the fault separation,
Figure 6-21 shows the FSU currents and corresponding terminal voltages for all
fault scenarios in the meshed test network with VCBs (ΔtVCB,O = 8 ms) applied as
FSUs (a) without and (b) with AC current injection. To limit the TIV across the
VCB, the voltage interruption limit is set to Uint = 72.5 kV. In case no AC current
injection is used, the maximum fault separation time is higher than
tsep,max > 100 ms. Even though the line currents are suppressed below
|iDC,L| < 100 A in all cases, the VCBs are not able to interrupt the current until the
currents decay to zero. On the contrary, Figure 6-21 (b) shows that the injection
of small AC currents into the lines which are to be separated, can reduce the fault
separation times to values below Δtint < 29 ms for all fault cases. After the current
26
Since the reference voltage is generated via the cascade of the DC current and voltage controllers,
the output limitations of both controllers prevent the system against instabilities.
interruption, the corresponding UFDs open and separate the faulted line
(Δtsep < 35 ms).
(a) FSU Currents without
(b) FSU Currents with
Figure 6-21: Vacuum circuit breaker: Breaker current (top) and corresponding busbar pole-
to-ground voltages (bottom) for all fault scenarios (in grey); highlighted: PG fault in the
middle of line L24, FSU24 & FSU42 (blue: positive pole, red: negative pole)
Analogous to the cases without AC current injection, the TRV, RRRV and
ROCOC are monitored during the fault current interruption process and are
presented in Table 6-2. The stresses imposed on the CBs during and directly after
current interruption are in the same order of magnitude as for the case without AC
current injection. Since the RRRV and ROCOC are well below the specified
withstand capabilities of commercial AC CBs, the AC current injection can be an
effective strategy to facilitate a fast and reliable fault separation using commercial
AC CBs.
Table 6-2: Impact of the AC current injection on the withstand capabilities VCBs applied
as FSUs.
Without AC current injection With AC current injection
Max. TRV [kV] 56.5 72.3
Max. RRRV [kV/ms] 0.052 0.069
Max. ROCOC [kA/ms] 0.101 0.101
6.3 HVDC Grid Restoration
After the separation of a faulted line, both the DC grid voltage and the power flow
within the affected protection zone must be restored as fast as possible. Since DC
networks in symmetric monopole have an isolated neutral point, while bipolar
systems with DMR are effectively grounded and comprise a return path for
compensating currents, both systems behave differently during grid restoration.
Hence, the recovery process of both configurations is analysed and effective
methods for the DC grid restoration are identified, enhanced and adjusted to the
needs of the protection strategy.
Within this work, the restoration process is coordinated by a central DC grid
controller (cf. section 4.6). As soon as the DC grid controller receives the status
open of all four FSUs, it initiates the restart process of all converters. For the
analysis of the grid voltage restoration an FSU based on a DC CB with a rated
voltage of URCB,r = 10 kV (USA,r = 15 kV) and a current interruption threshold of
Iint = 100 A is used for all cases.
6.3.1 Analysis of the DC voltage restoration
Firstly, the prospective behaviour of the DC grid voltage after an exemplary PG

and an exemplary PNG fault without any counter measures regarding the pole
balancing is analysed within the meshed DC test network, both in monopole and
bipole configuration. The exemplary PG and PNG faults are low-impedance DC
faults (RG = 0.1 Ω) in the middle of line L14 (cf. Figure 4-1).
In all four cases, the fault currents through the FSU14 and FSU41 and the
corresponding terminal voltages are controlled to values close to zero.
Consequently, the FSUs successfully separate the faulted line. After the
separation of L14, the DC voltage restoration process commences. As shown in
Figure 6-22 (PNG fault), DC faults with the involvement of both DC poles result
in a symmetric discharge of the DC network. Hence, the P and the N pole charge
symmetrically during the voltage restoration process and there is no need for
additional measures regarding pole re-balancing. Moreover, Figure 6-22 (Bipole
with DMR – PG Fault) shows that the bipolar scheme with DMR does not
experience overvoltages on the healthy pole during the voltage restoration
process, since the low-impedance DC-side grounding of the mid-point in the
bipolar system decouples both poles. During the DC voltage restoration process,
the DMR carries a compensation current and enables the individual charging of
the affected pole. Consequently, no additional measures have to be taken for the
grid voltage restoration in bipole network configurations.
On the contrary, single PG faults can affect the voltage of the healthy pole in
symmetric monopole networks, due to the high-impedance DC-side grounding of
the system. If no counter measures are taken and the converter maintains it pre-
fault DC voltage during the fault separation process, PG faults in symmetrical
monopole networks can cause an overvoltage on the unaffected pole up to the
protection level of the pole SA [Dan17, Wan19]. By applying the developed fault
control (cf. section 6.1.2), the FBCs can rapidly limit the current injected into the
unaffected pole and hence prevent the DC voltage from rising, as shown in
Figure 6-22 (Symmetric Monopole).The pole voltage imbalance is linked to a
zero-sequence of udc,P - udc,N = Udc/2 in the converter side AC voltage uac,2 and
only decays via the high-impedance zero-sequence grounding of the converter, if
no counter measures are taken. Once the DC voltage restoration commences, the
imbalance between the pole voltages remains and causes an overvoltage on the
healthy pole of udc,N ≈ 1.5 p.u. while the voltage of the previously faulted pole
remains at udc,P ≈ 0.5 p.u. Consequently, the pole voltage imbalance and the
corresponding overvoltage on the unaffected pole must be suppressed by
appropriate counter measures to protect the grid’s components and to resume
normal operation conditions.
Symmetric Monopole Bipole with DMR
PG Fault
PNG Fault
Figure 6-22: Prospective DC grid voltage profiles for an exemplary PG and PNG fault in
MTDC network in symmetric monopole and bipole configuration
To overcome this issue, re-balancing schemes typically used in MTDC systems

based on half-bridge MMCs in symmetric monopole configuration can be applied
to FBC-based HVDC networks [Ruf19b]. Within such networks based on half-
bridge MMCs, PG faults result in a persistent overvoltage on the unaffected pole.
Consequently, pole re-balancing is a necessary step to protect the components
against temporary overvoltages and to restore the system to normal operation.
There are two main counter measures to these overvoltages: dynamic braking
systems (DBS) or AC-side grounding schemes permitting zero-sequence currents
[Wan19]. Such re-balancing schemes can be applied to FBC-based protection
systems to balance the DC poles during the voltage restoration process [Ruf19b].
Moreover, it is possible to utilise the controllability of the FBC and discharging
the healthy pole prior to the voltage restoration [Dan17, Ruf19b].
6.3.2 Dynamic Braking Systems
Figure 6-23 (left) shows the DC grid voltage for the same exemplary fault
scenario: Meshed MTDC network, low-impedance PG fault in the middle of line
L14. After fault inception the converters suppress their DC current and the faulted
line is separated by the FSUs at tsep = 17 ms. Subsequent to the fault separation
and the time required for the commutation between the terminal and the grid IED,
the DC voltage restoration commences. At this point in time, the DC voltage on
the previously faulted positive pole is almost zero, while the voltage on the
healthy negative pole is still uDC,N(17 ms) ≈ – 320 kV.
During the voltage restoration, the MMCs control the pole-to-pole voltage to
uDC,PN = 640 kV, which in combination with the asymmetrical pole voltage
distribution results in an overvoltage on the N pole. As soon as the pole voltage
at a DBS location exceeds uDC,N = 1.1 p.u. the DBS is triggered and remains active
until the pole voltage is limited to uDC,N = 1.05 p.u. Thereby, the DC voltage is
restored to the ± 10 % operation band within ΔtU,rst ≈ 66 ms after fault inception.
In this exemplary case the braking resistors dissipate EDBS,T1 = 9.5 MJ and
EDBS,T2 = 9.3 MJ, which is at least an order of magnitude smaller than the energy
dissipated during an onshore AC-FRT (up to a few 100 MJ) [Wan19]. The
voltages across the affected DBS switches TDBS,n of DBSC1 and DBSC2 are shown
in Figure 6-23 (right). The maximum voltage in this case is uT,DBS = 469 kV. This
voltage, however, strongly depends on the voltage imbalance between the DC
poles prior to restoration and could therefore increase to the pole SA protection
voltage, i.e. USA,DC,p = 1.8 p.u. = 576 kV. Consequently, the insulation level of the
DBS IGBT stacks needs to be dimensioned accordingly. Alternatively, a more
complex DBS design, e.g. based on surge arresters, could be applied [Wan19].
Figure 6-23: DC voltage profiles (left) with zoom (right) using an DBS circuit with lumped
braking resistors for pole re-balancing; Exemplary low-impedance PG fault in meshed
MTDC test network in monopole configuration at the fault location L14 - 50%
During the operation of the fault separation and restoration sequence, the
converters do not exceed any voltage or current limits. The internal converter
behaviour of converter C1 is shown in the Appendix A.7.
6.3.3 AC-Side Grounding and Zero-Sequence Control
To avoid the discharge of the healthy pole during the fault separation process, the
zero-sequence of the converter-side AC current iac,20 is controlled to zero until the
restoration process commences [Wan19]. The schematic of the zero-sequence
suppression and the flow-chart of the protection sequence is given in Figure 6-24.
DC Fault Detection
iac2,dq * Fault Control Mode:

AC Current Control Terminal Current Zero
DC Fault
(cf. Figure 5-2) Identification
eac,dq *
eac,dq0 *
Fault Separation Enable iac,20
Zero-Sequence eac,0 * Sequence suppression
Current Controller
iac2,0 * if FSU open
‫୍ܭ‬ǡ୍୸
‫୔ܭ‬ǡ୍୸ ൅ true
‫ݏ‬ Fault Control Mode: Grid IED
Terminal Current Zero (Restart logic)
0 uac2,0
Enable iac0 Suppresion Restart Signal

Control true
Disable iac,20
Voltage Restoration
suppression
Figure 6-24: Zero-sequence current suppression control (left) and schematic diagram of
the fault handling sequence
Analogous to the DBS case, Figure 6-25 (left) shows the DC grid voltage profile
for the exemplary fault scenario. During the separation process, the zero-sequence
current is suppressed by the control presented in Figure 6-25 (left) and the voltage
of the healthy pole is maintained to its nominal voltage [Wan19]. Once the voltage
restoration commences, the pole-to-pole voltage is controlled to its nominal value
of udc,PN = 640 kV causing a temporary overvoltage on the negative pole. At the
same time the zero-sequence current suppression is deactivated to permit the pole
voltage re-balance via the zero-sequence current. Thereby, the pole voltage
imbalance decays and both pole voltages resume within the ± 10 % tolerance band
in ΔtU,rst ≈ 101 ms after fault inception. The total energy dissipated within the
natural resistor of grounding scheme during the fault handling process is
EZ,C1 = 2.1 MJ and EZ,C2 = 1.8 MJ.
As within the DBS cases, the converters do not exceed any voltage or current
limits. The internal converter behaviour of converter C1 is given in the
Appendix A.7.
Figure 6-25: DC voltage (left) and zero-sequence current (right) profiles using a zig-zag
grounding transformer for pole re-balancing; Exemplary low-impedance PG fault in
meshed MTDC test network in monopole configuration at the fault location L14 – 50%
6.3.4 Converter Controlled Rebalancing
Since the cause of the overvoltage on the healthy pole is the voltage imbalance
prior to the DC voltage restoration, it can be prevented by removing the unbalance
before the restoration process commences. In case of a permanent DC fault, like
an insulation break-down of a HVDC cable, the fault provides a permanent low-
impedance grounding on the affected pole. Hence, by discharging the healthy pole
via the FBCs into the fault location the pole voltage unbalance can be eliminated.
Subsequently, the faulted line can be separated by the corresponding FSUs and a
balanced voltage restoration process commences.
DC-PoC DC Fault Detection
Fault Control Mode:

Terminal Current Zero
DC Fault
SM1 SM1 SM1 Identification
SM2 SM2 SM2
Fault Control Mode: Converter
AC-PoC SMn SMn SMn Terminal Voltage Zero controlled
DC network
discharge
false |uDC,P,N| ≤ Uthres
true
Fault Control Mode: Fault
Line Current Zero separation
SM1 SM1 SM1
SM2 SM2 SM2 false FSU tripping condition
true
SMn SMn SMn
Trip FSU
if FSU open
yes
y
Fault Control Mode: Grid IED
Terminal Current Zero (Restart logic)
Restart Signal
true
Voltage Restoration
Figure 6-26: Schematic diagram of the discharge process of the healthy pole via the
converter and the fault location (left) with the corresponding protection logic (right)
In order to discharge the healthy pole, a controlled unbalance suppression method
can be applied [Ruf19b]. By controlling the DC terminal pole-to-pole voltage
uDC,PN to zero using the TVC method (cf. section 6.1.2), the pole unbalance can
be suppressed without the interruption of the reactive power control of the FBC.
Thereby, the healthy pole is discharged via the FBCs and the low-impedance
grounding of the fault, as shown in Figure 6-26 (left). The corresponding
protection logic for the DC grid discharge is illustrated in Figure 6-26 (right).
Consequently, both poles are already balanced prior to the fault separation and no
further DC voltage balancing actions are required during the DC voltage
restoration process itself.
The characteristic behaviour of the DC terminal voltages and currents during the
converter-controlled grid discharge and the subsequent voltage restoration
process is shown for a PG fault in the middle of line L14 in Figure 6-27 for a low-
and in Figure 6-28 for a high fault impedance. After fault detection, all converters
control their DC terminal current to zero.
Once the fault is localised on L14, the converter C1 and C4 control their DC
current to iDC,T ≈ -1.1 p.u. in order to discharge the healthy pole. As soon as both
pole voltages are discharged below the predefined voltage threshold, i.e. uDC,P,N ≤
0.05 p.u., the converters switch to LCC mode and separate the faulted line.
Despite of the difference in the fault impedance, the protection system requires
Figure 6-27: DC voltage (left) and current (right) profiles during the controlled balancing;
Exemplary low-impedance PG fault in meshed MTDC test network in monopole
configuration at the fault location L14 – 50%
Figure 6-28: DC voltage (left) and current (right) profiles during the controlled balancing;
Exemplary high-impedance PG fault in meshed MTDC test network in monopole
configuration at the fault location L14 – 50%
similar times for fault separation in the exemplary fault cases
(Δtsep(RF,PG = 0.1 Ω) = 44 ms & Δtsep(RF,PG = 20 Ω) = 46 ms). Since the pole
voltage is already balanced, both are restored within the band of ± 10 % in less
than 40 ms after fault separation, resulting in a voltage restoration time of
ΔtU,rst(RF,PG = 0.1 Ω) = 77.8 ms and ΔtU,rst(RF,PG = 20 Ω) = 82.5 ms. As with the
other balancing methods, the converters do not exceed any voltage or current
limits. The internal converter behaviour of converter C1 is given in the
Appendix A.7.
Even though the controlled discharge of the healthy pole is an efficient method to
enable a balanced DC grid restoration, which does not require additional
balancing equipment, it has two major limitations:
x The balancing of the DC pole voltages depends on the presences of a

low-ohmic grounding point in the DC system, i.e. the DC fault. Hence,
it cannot be directly applied for the grid restoration during temporary
faults, like atmospheric fault in OHL based networks segments.
x The speed of the balancing and therefore, the overall fault handling
process depends on the fault resistance. Even though it is shown that
high-impedance cable faults, in the order of Rf = 20 Ω, are sufficient to
discharge both poles prior to the restoration, high-impedance faults
might prolong the discharge and hence the fault separation time.
To overcome these limitations, high-speed pole line earthing switches (PLES)
with making capabilities can be added to the protection scheme as presented in
Figure 6-29. Once a line is identified as faulted, the closing of the corresponding
PLES is initiated. Since high-speed PLES do typically require some tens of
milliseconds to close, the healthy pole is discharged via the converters and the
fault location as long as the fault is present in the system.
3
1 DC Fault Control
1 4
2
2 Close PLES
FBC 3 Open FSU after operation conditions are fulfilled
4 Balanced DC Voltage Restoration
Figure 6-29: Restoration via fast line earthing

The effect of the PLES on the pole voltage balancing is presented in Figure 6-30
based on the same exemplary fault. The closing time of the PLES is set to the
Figure 6-30: DC voltage (left) and current (right) profiles during the converter-controlled
balancing supported by PLES; Exemplary low-impedance PG fault in meshed MTDC test
network in monopole configuration at the fault location L13 – 50%
exemplary values tPLES,C = 20 ms in order to demonstrate the effect of the PLES

on the DC pole voltages. The key difference compared to Figure 6-27 is the drop
in the voltage of the N pole at Δtsim ≈ 23 ms and the corresponding peak in the
terminal current. After the line discharge, the FSU separate the faulted line and
the voltage restoration commences. Compared to the case without PLES, the
restoration time decreases by 19 ms to Δtu,rst = 59 ms.
6.3.5 Comparison of the Voltage Restoration Methods
For the comprehensive evaluation of the re-balancing methods, the KPIs tsep, tU,rst,
tP,rst, ΔE (cf. section 3.2) are calculated per converter based on all fault scenarios
defined in section 4.1 within the meshed network configuration for the different
grounding and restoration schemes:
x Bipole with DMR
x Sym. monopole with DBS
x Sym. monopole with zero-sequence grounding
x Sym. monopole with converter-controlled grid discharge
(no PLES; PLES with tPLES,C = 20 ms; PLES with tPLES,C = 40 ms)
The stresses imposed on the cable system are evaluated and compared with state-
of-the-art test requirements in Appendix A.8.
Figure 6-31: Comprehensive comparison impact of the HVDC grid restoration strategy on
the performance of the protection system fault all 24 faults in the meshed network
Fault Separation
In all cases, a fault can be separated within Δtsep < 55 ms. Since a low-impedance
of the fault current loop facilitates a fast discharge of the faulted pole, the fault
separation time in the bipolar system is smaller than in the monopolar cases.
While the fault separation times are similar in the DBS and AC grounding case,
the time required to discharge the healthy pole causes an increased fault
separation time in case a converter-controlled balancing is applied. However, it is
shown that within the meshed test network, the application of high-speed PLES
does only have a minor impact on the fault separation, since the is already
discharged via the FBC once the high-speed PLES closes, e.g. after
ΔtPLES,C = 20 ms. Therefore, a PLES is only relevant to enable a DC-side
discharge in case of a temporary fault which extinguished before the healthy pole
is discharged and to increase the reliably of restoration method.
Voltage Restoration
To evaluate the voltage restoration two KPIs ΔtU,90 and ΔtU,rst are considered.
Apart from the bipolar system, the fastest voltage restoration is achieved with the
DBS system, because it directly limits the voltage to the set maximum voltage of
1.1 p.u. It is shown that the maximum voltage restoration time in the AC
grounding case is almost twice the worst-case restoration time of the DBS case,
with the chosen transformer and grounding resistor parameters. Moreover, the
simulation results show a wide spread in the restoration time. One reason for this
spread is the fixed AC zero-sequence impedance used for the restoration of
different network configurations after the separation of the various faults. Hence,
the optimisation of the AC grounding system would require the adjustment of the
grounding impedance based on the fault location. Finally, it is shown that the
voltage restoration time in case of the converter-controlled pole re-balancing is in
the same order of magnitude as the restoration time in the DBS case. Even though
the fault separation can require more time, due to the discharge of both poles of
the network, the balanced conditions facilitate a fast restoration within the defined
voltage band. Analogous to the fault separation, it is shown that the application
of a fast PLES system only has a minor influence on the voltage restoration
converter-controlled grid discharge method without PLES.
Power Flow Restoration and Transient Energy Imbalance
The restoration of the active power flow within the ±10 % tolerance band is
achieved within ΔtP,rst < 150 ms in all cases. Due to the 50 % redundancy in case
of PG faults and the relatively fast fault separation and voltage restoration, the
bipole system shows the fastest recovery of the active power flow and the smallest
transient energy imbalance. In line with the fault separation time, the application
of the DBS and the AC grounding schemes results in similar power flow
restoration times, which are for all cases smaller than ΔtP,rst < 130 ms. As the
overvoltage limitation and hence the balancing of the healthy pole in case of a PG
fault requires the same amount of energy and the application of both schemes
results in similar fault separation times, the transient energy imbalance is similar
for both schemes as well (ΔE < 90 MJ). Compared with the DBS and AC
grounding cases, the converter-controlled DC grid discharge shows an increase
in the power restoration time of approximately 20 ms, which is in line with the
higher fault separation times.
It is shown that the DC pole voltage re-balancing has a considerable impact on
the overall performance of the FBC-based protection strategy during single pole-
to-ground faults in monopolar DC networks. If a DBS is included in the HVDC
network to ensure an FRT of the system during faults in the AC transmission
systems, the DBS could be used for re-balancing purposes as well. Alternatively,
pole re-balancing can also be accomplished using AC grounding schemes
providing a zero-sequence current path, such as zig-zag grounding transformers.
An alternative method – a converter-controlled grid discharge – solely relying on
the controllability of the FBC is proposed. Even though the method does not
require addition equipment for the grid restoration, combining the method with
high-speed PLES can enhance the reliably.
The choice of the restoration method for a specific network is expected to be
project specific. For example, in case DBSs have to be installed to enable the FRT
of offshore WPPs connected to shore via the DC network, it might be possible to
use the same DBSs for the DC voltage restoration. If no DBS is foreseen in a
symmetric monopole network, a low-impedance AC grounding schemes as well
as the developed converter-control grid discharge method are can enable a
balanced restoration of the grid voltage after the separation of a PG fault.
Compared to a DBS, which is constructed similar to a converter phase (two
converter arms), AC grounding schemes and especially the controlled discharge
can be economically attractive solutions.
System Impact 109
7 System Impact
While the focus of the previous chapter has been on the DC-side fault separation,
evaluating the applicability of the developed protection strategy requires a
comprehensive analysis of its capability to limit the impact of DC contingencies
on surrounding AC networks. Hence, protection system’s KPIs have to be
analysed for both the radial and the meshed test network in monopole and bipole
circuit configuration under variation of the FSU technology. To demonstrate that
the protection strategy can be applied to larger HVDC networks than the meshed
and radial network, an outlook towards its extensibility is given.
Since DC faults result in a temporary stop in the active power transfer of the
affected converters, requirements for the DC-FRT of islanded generation units,
like WPPs, are defined. Their functionality needs to be demonstrated, e.g. by an
exemplary DC-FRT of a WPP with controls matching the defined requirements.
7.1 Performance Evaluation
As it is shown in section 6.2.2, both DC CBs with voltage ratings in the range of
5…10 % of the nominal DC voltage and fast AC CBs, which do not provide any
counter voltage, can be applied as FSUs in FBC-based protection systems, if the
strategy and the fault control is adjusted to their needs. The performance analysis
is therefore carried out with two exemplary FSU types:
1) DC CB with a rated RCB voltage of URCB = 10 kV (USA,r = 15 kV) and
an energy absorption capability of ESA,r = 12.5 kJ (Iint = 100 A).
To enable a fast fault separation, fulfil the requirements on the surge
current carrying capability and enable a compact design of the FSU, such
RCBs could for example be realised by a solid-state (SS) CB comprising
two antiparallel series connections of three integrated gate-commutated
thyristors (IGCTs) with a rated voltage of UIGCT,r = 6.5 kV [ABB18,
Ruf19a]. This design results in an on-state resistance of approximately
RFSU,on ≈ 1.5 mΩ and therefore a power loss of PFSU ≈ 5.3 kW (under full
load) per FSU [ABB18]. Hence, the losses of this exemplary FSU design
are in the same order of magnitude as the losses of a load commutation
switch of a hybrid CB [Has15].
110 System Impact
2) VCB with a rated voltage of 72.5 kV

For the test case, fast VCBs are used, which can fully separate their
contacts within the range of ΔtCB,O ≈ 8 ms after tripping. Since the arc
voltage of VCBs is relatively small to the residual terminal voltage, the
arc voltage is neglected (uarc = 0 V). To ensure the presence of CZC, an
LCC with AC current injection, as presented in section 6.2.3, is applied.
The performance analysis is carried out for both the meshed and the radial
network in symmetric monopole and bipole configuration. In line with the
analysis of chapter 6, all fault cases described in section 4.1 are taken into
consideration. The pole voltage re-balancing after PG faults in the monopolar
networks is realised via DBSs located at the terminals T1, T2, T5 and T6.
To illustrate the impact of a DC fault in the different test networks, Figure 7-1
shows the voltages at the DC terminals as well as the active and reactive power
at the PoCs for a PG fault in the middle of line L14 (meshed network) and in the
Meshed Network Radial Network

DC Voltage [kV]
AC Power [MW]
Figure 7-1: DC voltage and power profiles for a low-impedance PG fault in the middle of
line L14 and L57 in the meshed and radial network with VCB-based FSU and DBS- based
balancing scheme
System Impact 111
middle of line L57 (radial network). For these exemplary cases, the VCB-based
FSU is used in the protection scheme.
In both networks, the faulted line is separated in less than Δtsep = 35 ms and the
grid voltage is restored in ΔtU,rst = 78 ms. As the converters ride through the fault
without interruption, they uphold their reactive power controllability during the
entire fault handling process (within a band of ΔQ < ± 0.1 p.u.). The active power
can be restored at all AC-PoCs within ΔtP,rst,mesh = 121 ms and ΔtP,rst,radial = 168 ms
resulting in a maximum transient energy imbalance at all AC-PoCs of
ΔEmesh = 63 MJ and ΔEradial = 107 MJ. After the separation the faulted line L14 in
the meshed network, the DC terminal voltages and the power flow resume to the
pre-fault state. On the contrary, due to the loss of the connection between T5 and
T7, the fault in the radial network results in the separation of the converter C5
from the remaining network and thus in a long-term set-point change. After the
separation of the faulted line, C5 resumes to STATCOM mode.
For a broad evaluation of the protection system’s performance, the worst-case
values for the design relevant KPIs for the individual combinations of the FSU
type, the network topology and the circuit configuration are presented in
Figure 7-2. The protection system successfully separates the faulted lines and
restores the grid in all conducted test cases. Since all converters maintain their
controllability, the reactive power provided at the AC-PoC is not affected by DC
contingencies, apart from a dynamic disturbance (cf. Figure 7-1).
Due to the different structure of the networks, it is not possible to directly compare
the KPIs obtained in the radial and the meshed network. Nonetheless, the
protection system is able to separate all faults in the given test networks and
restore the DC voltage within. The comparison between the symmetric monopole
and bipole grid configuration shows, that the effective earthing of the bipolar
system with DMR and its 50 % redundancy during PG faults has a positive effect
on the fault separation and restoration process. In both networks, the worst-case
KPIs are approximately 20…30 % smaller in the bipolar than in the monopolar
cases.
Moreover, it is shown that in the meshed network, the protection system with
VCB and AC current injection achieves shorter fault separation times and hence
shorter DC voltage and active power restoration times than the low-voltage DC
CB-based FSU. On the contrary, in the radial DC network, the DC CB-based FSU
outperforms the VCB. Reason for this is absence of a converter at terminal T8
and hence the absence of a controlled AC current injection. As the converters,
which are not directly connected to the faulted line, only limit their DC current to
zero, the CZC is a result of the natural discharge of the grid into the fault location.
Especially during high-impedance faults, the system’s damping can results in
112 System Impact
relatively long fault separation times. Hence, it is suggested to use FSU with DC
current interruption capability at a remote node, like T7, in the protection zone.
Meshed Network Radial Network
Fault separation time Fault separation time
Fault separation
[ms] time [ms] Fault separation
[ms] time [ms]
250 250
200 200
150 150
Transient energy 100 UDCDC voltage Transient energy
restoration 100 UDCDC voltage
restoration
imbalance [MJ] 50 time [ms] time [ms]imbalance [MJ]
restoration 50 restoration
time [ms] time [m
0 0
Active power Active power

PActive power
AC recovery PAC recovered
restorted to 90 % PActive power
AC recovery PAC recovered
restorted to 90 %
recovery
timetime
[ms][ms] to 90[ms]
% [ms] recovery
timetime
[ms][ms] to 90[ms]
% [ms]
Monopole with VCB Monopole with SSCB Bipole with VCB Bipole with SSCB
Figure 7-2: Worst-case KPI evaluation of DC contingencies in the meshed and radial
network under variation of the circuit configuration (sym. monopole and bipole with
DMR) and exemplary FSU types (low-voltage and energy SSCB and VCB)
Within the sensitivity analysis of the impact of DC contingencies on surrounding
AC systems, it is shown that for HVDC grids with a transmission capacity of a
few gigawatt, a protection system comprising FBCs and FSUs with low or even
no DC current interruption capabilities can separate DC faults in the order of a
few tens of milliseconds after fault inception. Depending on the amount the grid
structure, its circuit configuration and the size of the protection zone, the worst-
case DC grid voltage and active power restoration times are in the order of
Δtrst ≈ 150 ms and the corresponding transient energy imbalance per converter
can be limited to ΔE < 100 kJ/MW. The compliance of the protection strategy to
the definition of a temporary stop in P strongly depends on a transmission
system’s inertia and the ratio of the transient energy imbalance to the total power
of the transmission system.
Comparing the KPIs of this work’s protection strategy with the KPIs of a
protection strategies based on hybrid (or mechanical) DC CBs located at every
line end in the same meshed test network [Bra19, Wan19], indicate that the FBC-
based protection system with a single protection can achieve similar restoration
times in HVDC networks comprising only a few converter stations.
Even though the fault separation in the FBC-based protection system takes longer
than in protection systems based on DC CBs, the absence of current limiting line
inductors enables a fast restoration of the power flow after the fault separation.
Nevertheless, if the power outage times do not comply with the temporary stop
System Impact 113
in P requirements of a given transmission system, the grid needs to be split into

several protection zones.
7.2 Network Extension
To enable the application of the strategy to extensive DC networks, the DC system

can be divided into multiple protection zones, as illustrated in Figure 4-1. To
allow the FRT of unaffected protection zones, grid splitting interfaces (GSI)
implemented at the DC-PoCs must ensure that DC faults do not cause protection
actions of the unaffected protection zones.
Therefore, GSIs, like fast DC CBs in combination with fault current limiting line
inductors or DC-DC converters, have to limit the voltage drop to the affected
protection zone. The requirements on the separation speed of the GSI and the
associated voltage drop in the unaffected protection zones must be coordinated
with the FRT capability of the corresponding converters. A protection strategy
for the GSI is proposed in Figure 7-3.
false
true
DC Fault Detection Open GSI uPZ,1 – uPZ,2 < ΔUPZ Re-close GSI
Wait for fault separation and voltage

restoration in the affected protection zone
Figure 7-3: Schematic representation of the GSI logic

The concept is demonstrated in the extended test network with an exemplary PG
fault at tsim = 0 ms on line L24 at the end connected to T2. The corresponding
simulation results are given in Figure 7-4. The exemplary network is configured
as symmetric monopole with a converter-controlled pole re-balancing without
PLES. The FSUs are based on VCBs with a rated voltage of 72.5 kV (cf. section
7.1). To guarantee the presents of CZCs, the fault control with AC current
injection is applied (cf. section 6.2.3). In addition, a bidirectional hybrid DC CB
with a line inductor of LGSI = 100 mH is implemented at T2 as GSI.
The protection IED associated to the GSI detects the fault Δtdet = 0.3 ms after fault
inception and trips the GSI. Subsequent to the breaker opening time of
ΔtCB,O = 2 ms the DC CB commutates the fault current into the absorption path
and thereby separates both protection zones. Contrary to PZ1, the DC voltage and
power profiles PZ2 only show a dynamic disturbance during the first 15 ms after
fault inception. Since the DC voltage does not drop below the under-voltage
114 System Impact
threshold of the protection IEDs (uthres = 0.75 p.u.), PZ2 rides through the fault
without any protection actions. The fault causes a shift in the mid-point of the DC
voltage in PZ2. The fault separation process in PZ1 is similar to the fault presented
in section 7.1 and is hence not discussed here in detail. After the faulted line L24
of PZ1 is separated from the remaining grid at Δtsep = 35 ms, the restoration
process commences. At tsim = 72 ms the voltage difference between both poles of
PZ1 and PZ2 is within the exemplary reconnection limits of ΔUPZ = 0.1 p.u.,
causing the re-closure of the GSI and the reconnection of both zones.
Protection Zone 1 (Meshed Network) Protection Zone 2 (Radial Network)
DC Voltage [kV]
Separation
of the PZs
Reconnection
of the PZs
AC Power [MW]
Figure 7-4: DC voltage and power profiles for a low-impedance PG fault on L24 - 0 %
extended test network with VCB-based FSU and converter-controlled re-balancing
It is shown, that the fault only has an impact on the power flow at converter C5
in PZ2, which is due to the temporary stop of the power transfer (200 MW) from
PZ1 to PZ2. After the reconnection of both zones, the power at C5 is restored at
tP,rst,C5 ≈ 130 ms.
System Impact 115
7.3 DC-FRT Requirements on Surrounding Networks
A prominent field of application for DC networks is the evacuation of power

generated by islanded generation units, like offshore WPPs [Her16]. Hence, the
protection system shall enable the FRT of generation units solely connected to a
single HVDC converter of a meshed DC network. Within this section, the
DC-FRT operation of such islanded generation units is presented based on a
simulation case in which offshore WPPs are connected to the converters C3 and
C4 of the meshed test network. The general findings, however, can be transferred
to other scenarios of generation units sorely connected to a converter which
temporary stops its active power transfer during fault separation within the DC
network.
In such cases, the (offshore) HVDC converters operate in GFC mode during
normal operation and provide the reference voltage and frequency for the WTGs,
which transfer their generated active power to the AC collector grid. In case of
DC contingencies, the HVDC converters associated to the affected protection
zone change their operation mode to the fault handling control mode introduced
in section 6.1.2. As illustrated in Figure 7-5, the AC reference control mode of
the offshore HVDC converter is changed to TEC (cf. 5.2.2) to maintain the stored
energy within the converter. Since almost no active power is transferred from the
collector grid to the faulted DC network, the energy generated by the WTGs
cannot be evacuated during the fault separation process.
• Limit UAC
• GFC Mode
4 km
Temp. Stop in P G
FSU
FBC Const. P
8 km 3 km
G
Energy Dissipation
6 km
DC Fault Control G
Figure 7-5: DC-FRT of an offshore WPP

To comply with state-of-the-art WTG designs, the energy difference at the
offshore converter terminal ΔE must be within the energy dissipation capabilities
of the WTG choppers. Moreover, two key requirements are identified to enable a
DC-FRT of islanded generation units, like WPPs, solely connected to an HVDC
converter, which temporary stops its active power transfer during DC faults:
116 System Impact
1. The generation units must remain connected to the grid and suppress
their active power transfer during the DC-FRT.
2. The generation units must be able to seamlessly transition to a GFC
mode, which locks the frequency of the generation units to each other
and to the nominal grid frequency and limits the AC voltage, i.e.
Ucoll < 1.2 p.u.
To fulfil these requirements, two adjustments are exemplary done within the
control of the grid-side WTG converter presented in 4.7:
1. An overvoltage limitation to Uac,max = 1.15 p.u. is added to the reference
output voltage edq*,
2. A variable frequency band is added to the PLL, which limits its reference
frequency to 49…51 Hz in case of an AC overvoltage (uac,rms > 1.1 p.u.).
The reference current id* corresponding to the active power transfer is
automatically set to id* = 0 during overvoltages in the collector grid, since the
grid-side converter is operated in q priority mode. As the active power transfer of
the MMC stops during the DC-FRT operation, the AC collector grid voltage rises
and the WTGs provide the maximum reactive power to reduce the AC voltage.
To demonstrate the DC-FRT, Figure 7-6 shows the voltage and current profiles
at T4 and AC-PoC4 as well as the collector grid voltage and current during an
exemplary low-impedance PNG fault in the middle of line L24 of the meshed test
network. To demonstrate the converter control during the FRT operation, the FSU
opening time is set to ΔtFSU,O = 50 ms. The DC fault is detected by the protection
IED of terminal T4 after Δtdet = 0.7 ms, which initiates the fault handling process
of C4. The converter is able to suppress the fault current and limit its internal
capacitor voltages during the fault handling process. Due to the temporary stop in
the active power injection of C4, the AC voltage and frequency start rising. After
an initial transient, the collector grid voltage can be limited to ucoll < 1.25 p.u. and
the frequency maintains around fcoll < 52 Hz. Due to the interrupted power
transfer, the DC voltage of the WTG rises and is limited by the WTG chopper to
udc,WTG ≈ 1.15 p.u. The absorbed energy in the WTG chopper is EWTG ≈ 1.3 MJ
per 8-MW WTG. As the amount of absorbed energy is directly linked to the time
of the temporary stop in active power, the protection system is interoperable with
standard WTG designs, if the active power restoration time at the offshore PoCs
is smaller than the maximum AC-FRT time defined in today’s grid codes, i.e.
ΔtP,rst < 150 ms. After the fault is separated and the grid voltage is recovered, the
HVDC converter resume to GFC control. As the AC grid voltage decay, the WPPs
inject their active power into the collector grid. After an initial dynamic response
of the converter, the offshore system resumes normal operation.
System Impact 117
Figure 7-6: FRT operation of WPP4 connected to the meshed test network for a high-
impedance PNG fault in the middle of line L24
118 System Impact
Conclusion and Further Research Needs 119
8 Conclusion and Further Research Needs
Multi-terminal HVDC networks are envisioned as a technically and economically

promising solution for the large-scale integration of renewable energy sources
into the power generation portfolio. To limit the downtime of HVDC networks
and thereby the impact of DC contingencies on surrounding AC systems, faulted
lines must be separated quickly and reliably from the remaining part of the DC
network.
Several concepts for the fast separation of faults in HVDC networks have been
proposed, most relying on fast DC CBs located at every line end. However, fault
separation concepts based on FBCs, which allow a controlled DC fault handling,
like full-bridge and mixed-cell MMCs, can be a competitive alternative,
depending on the network design. A major advantage of FBC-based protection
systems is that in comparison to strategies based on full-size DC CBs, switchgear
with low DC current breaking and energy absorption requirements can be used
for the fault separation. Since the component costs of full-size DC CBs, as well
as the costs associated with the weight and volume of the DC CBs itself and their
corresponding high-energy air-cored inductors, might be a significant part of the
total installation costs of HVDC stations, FBC-based protection systems with low
footprint FSUs and no need for fault current limiting inductors can be an
economical alternative.
However, to enable the protection of future multi-terminal HVDC networks with
FBC-based protection systems several open challenges still have to be overcome:
x Development of DC fault control, which ensures the fast separation of
faulted lines and enables the application of FSUs with low or even no
DC current interruption capabilities
x Definition of requirements on FSUs and identification of suitable
switchgear technologies and adaptation of the protection strategy to the
needs of the FSUs
x Restoration of the DC grid voltage after fault separation in different
network circuit topologies (symmetric monopole and bipole)
In addition, a suitable framework for the evaluation of the protection strategy,
comprising relevant HVDC network and circuit configurations is required. The
dynamic behaviour of the protection system has to be analysed comprehensively
in a wide set of network configurations.
For this purpose, a stepwise investigation and development approach of the

individual phases of the protection strategy is carried out:
Converter and DC Fault Controls: Especially during DC faults, it is
essential to have a high degree of controllability over the individual
voltages and currents of FBCs. Based on existing MMC control concepts
and parametrisation methods, an MMC control allowing the independent
regulation of the AC, the circulating current and the DC quantities is
elaborated. Depending on the specific requirements on the controls during
the fault separation and grid recovery phases, the FBC-based protection
relies on a stable and dynamic adjustment of its DC terminal current, the
DC terminal voltage and even the current flowing through the FSUs of a
faulted line. To fulfil these requirements, a cascaded DC fault controller is
developed. As the application of FSUs without any or with very limited
DC current interruption capabilities, like conventional AC CBs, requires
externally generated current zero crossings, an AC current injection option
is added to the DC fault control scheme. Moreover, the developed control
allows a secure DC-FRT even in case of an undetected bolted fault.
Fault Separation Units: A key motivation for the application of fault-
blocking instead of fault-feeding converters in HVDC grids is the
reduction of the requirements on HVDC switchgear by creating near-zero
voltage and current conditions prior to the fault separation. Based on the
developed fault control concept, the protection strategy enables the
application of FSUs with comparably low interruption voltages (in the
range of 5…10 % of the rated DC voltage) and low energy absorption
requirements (in the order of a few tens of kilojoules) for the interruption
of the residual fault currents.
Moreover, the conducted EMT simulations indicate that the stresses
imposed on FSUs without or with very limited DC current interruption
capabilities during the interruption of residual fault currents are within the
standardised withstand requirements of conventional AC CBs. However,
it is demonstrated that the success of the fault separation depends on the
presence of current zero crossings. Even though the arc voltage of high-
pressure gas CBs can enhance the fault separation process, their counter
voltage might not be sufficient to ensure a fast fault separation in every
fault case.
To meet the requirements on reliability and robustness of HVDC
protection systems, a fault control concept is elaborated, which injects
small AC currents – the range of a few percent of the nominal DC current
– into the faulted line. This AC current injection does not only improve the
reliability of the fault separation but also decreases the overall fault
separation times.
Grid restoration: The proposed FBC-based protection strategy discharges
the affected protection zone, which can be the entire DC grid in case of
small DC networks, to separate a faulted line. The DC voltage and the
active power flow need to be restored quickly after fault separation. While
the pole voltage in bipole HVDC networks comprising a dedicated
metallic return can be controlled individually due to the balancing current
path of the return conductor, the pole voltages of networks in symmetric
monopole configuration can only be controlled symmetrically. As a
single-pole-to-ground fault causes a rapid discharge of the affected pole,
the pole voltage imbalance after fault separation can cause overvoltages
on the unaffected pole of up to twice it’s nominal voltage.
To enable the application of the FBC-based protection strategy to
monopolar HVDC grids, which is the most frequently used configuration
for MMC-based systems, it is shown that both, DBS and AC zero-
sequence grounding schemes can be applied for the pole voltage re-
balancing. In addition, a restoration method is elaborated, which enables a
balanced grid restoration without the need for additional restoration
equipment by making use of the high degree of controllability of FBCs.
Based on a comprehensive fault analysis, including the evaluation of the
restoration methods’ impact on the DC voltage and active power flow
restoration, it is shown that all three approaches are suitable to enable
balanced pole voltages after the grid restoration.
Hence, in cases in which DBSs are required to provide an AC-FRT
capability of a DC network, e.g. for HVDC systems connecting offshore
WPPs to shore, the DBSs can be used for the pole voltage re-balancing as
well. In case DBSs are not foreseen in the network, a zero-sequence
grounding or especially the application of the developed controlled DC
discharge are technically feasible and economically attractive solutions.
To allow a comprehensive assessment of the protection strategy functional
requirements, including interoperability and extensibility requirements, as well as
quantifiable performance indicators are formulated. It is shown that for HVDC
grids with a transmission capacity of a few gigawatt27 a protection system
comprising FBCs and FSUs with low or even no DC current interruption
capabilities can separate DC faults in a few tens of milliseconds and restore the
27
The investigated meshed test network comprises 4 converters with PMMC = 1.2 GW and has a
transmission capacity of PHVDC,Σ = 2.4 GW. The extended test network comprises 7 converters and is
design to transmit PHVDC,Σ = 3.6 GW e.g. from offshore WPPs to shore.
DC grid voltage and active power in Δtrst ≈ 100…150 ms. Based on the defined
KPIs, the comparison of the DC grid protection based on FBCs and on hybrid
CBs located at every line end shows that the impact of both systems on
surrounding AC networks is in the same order of magnitude. Moreover, first
investigations indicate that the FBC-based protection system can be applied in
extended HVDC grids, if suitable separation interfaces, such as DC/DC
converters or fast DC CBs, are implemented between the individual protection
zones of the DC grid.
To enable the interoperability between HVDC networks protected by FBCs and
islanded generation units, like offshore WPPs, the generation units must comply
with the temporary stop in active power of the FBCs and comprise grid forming
functions during this temporary stop. Based on a simulation model of WPP
comprising WTGs which fulfil the defined requirements, the interoperability
between the developed protection system and islanded generation units is
exemplarily verified.
Based on the comprehensive assessment it is concluded that with the elaborated
enhancements the combination of FBCs and switchgear with low and even no
requirements on DC current interruption capabilities are a technically feasible
option for the protection of DC grids.
Nonetheless, HVDC grid protection based on converters with fault-blocking and
controlling capabilities is still a relatively young field of research. During the
development, analysis and application of the FBC-based protection system,
several needs for future research and developments are identified.
x First investigations indicate the applicability of FBC-based protection
systems in combination with suitable grid separation interface to wider
HVDC grids. To enable the application of the protection system to larger
grid structures, the separation, the FRT and the reconnection of the
protection zone should be analysed in detail. As extensive DC grids will
probably comprise converters and protection equipment of several
manufactures, the FBC-based protection scheme must be interoperable
with different HVDC grid protection approaches.
x The protection of HVDC grids must comply with the stability
requirements of the surrounding AC transmission systems. In addition
to the generic KPI approach of this work, the impact of DC contingencies
on AC transmission systems must be studied by means of comprehensive
grid simulations. Since faults in HVDC systems are typically analysed
with EMT programs and the stability of AC transmission systems is
typically evaluated using phasor-based simulation tools, novel methods
for the assessment of DC contingencies on the overall system stability

have to be developed.
x The focus of this work is on the primary protection strategy. However,
the application of the strategy to real HVDC networks requires a
thorough analysis of the failure modes and the elaboration of a
comprehensive back-up protection.
x It is shown that the performance of the protection system strongly
depends on the fault control of the FBC and the coordination between
the FSUs, the IEDs and the converter controls. In addition to the
simulation-based assessment of this work, the demonstration of the
strategy – at least in laboratory-scale conditions – is required raise its
technology-readiness-level. In addition, this work’s simulation results
indicate that conventional AC CBs can be applied as FSUs in the
protection system. These observations must be confirmed by suitable
tests in high-power laboratories.
124 References
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List of publications
Patents
1. P. Ruffing, M. Heidemann, A. Schnettler, C. Petino, “Method for
Handling a Fault Between an AC System and a DC System in a Medium
Voltage or a High-Voltage Network”, DE 10 2016 119 886 A1, Apr. 19,
2018.
Reviewed Journals & Magazines
2. P. Tünnerhoff, P. Ruffing, A. Schnettler, “Comprehensive Fault Type
Discrimination Concept for Bipolar Full-Bridge-Based MMC HVDC
Systems with Dedicated Metallic Return”, in IEEE Transactions on Power
3. M. Stumpe, P. Ruffing, P. Wagner, A. Schnettler, “Adaptive Single-Pole
Autoreclosing Concept with Advanced DC Fault Current Control for Full-
Bridge MMC VSC Systems” in IEEE Transactions on Power Delivery,
vol. 33, no. 1, 2018.
4. P. Ruffing, C. Brantl, C. Petino, A. Schnettler, „Fault Current Control
Converters”, in IET Journal of Engineering, vol. 2018, no. 15, 2018.
5. P. Ruffing, N. Collath, C. Brantl, A. Schnettler, “DC Fault Control and
High-Speed Switch Design for an HVDC Network Protection based on
Fault Blocking Converters”, in IEEE Transactions of Power Delivery,
vol. 34, no. 1, Feb. 2019.
6. P. Tünnerhoff, P. Ruffing, R. Puffer, “Power Cable Stresses Caused by
Transmission Line Faults in Next Generation VSC-MMC Systems”, in
IET Journal of Engineering, vol. 2019, no. 16, 2019.
7. W. Leterme, I. Jahn, P. Ruffing, K. Sharifabadi, D. Van Hertem,
“Designing for High-Voltage dc Grid Protection: Fault Clearing Strategies
and Protection Algorithms”, in IEEE Power and Energy Magazine,
vol. 17, no. 3, May-Jun. 2019.
8. C. Brantl, P. Ruffing, P. Tünnerhoff, P. Ruffer, “Impact of the HVDC
system configuration on DC line protection”, in CIGRE Science &
Engineering, vol. 15, Oct. 2019.
138 List of publications
International Conferences
9. P. Ruffing, C. Petino, A. Schnettler, “Dynamic internal overcurrent
control for undetected DC faults for modular multilevel converters”, in
proc. 13th IET International Conference on AC DC Power Transmission,
Manchester, UK, Feb. 2017.
10. C. Petino, P. Ruffing, A. Schnettler, “Intersystem fault clearing in hybrid
AC/DC power systems with full bridge modular multilevel converters”, in
proc. 13th IET International Conference on AC DC Power Transmission,
Manchester, UK, Feb. 2017.
11. P. Ruffing, C. Brantl, C. Petino, A. Schnettler, „Fault Current Control
Converters”, in proc. 14th IET International Conference on Developments
in Power System Protection, Belfast, UK, Mar. 2018.
12. P. Ruffing, C. Petino, S. Rüberg, J. A. Campos Garcia, S. Beckler, A.
Arnold, “Resonance Phenomena and DC Fault Handling during
Intersystem Faults in Hybrid AC/DC Transmission Systems with Partial
DC Cabling”, in proc. 20th Power Systems Computation Conference,
Dublin, Ireland, Jun. 2018.
13. P. Ruffing, C. Brantl, M. Stumpe, A. Schnettler, “A Novel DC Fault
Blocking Concept for Full-Bridge Based MMC Systems with
Uninterrupted Reactive Power Supply to the AC Grid”, in proc. CIGRÉ
Session, Paris, France, Aug. 2018.
14. P. Düllmann, P. Ruffing, C. Brantl, C. Klein, R. Puffer, “Interoperability
Among DC Protection Strategies Based on Fault Blocking Converters and
DC Circuit Breakers within a Multi-Terminal HVDC System”, in proc.
15th International Conference on Developments in Power System
Protection, Liverpool, UK, Mar. 2020.
List of abbreviations 139
List of abbreviations
AAC Alternate Arm Converter

AC Alternating Current
CB Circuit Breaker
CC Circulating Current
CZC Current Zero Crossing
DBS Dynamic Braking System
DC Direct Current
DMR Dedicated Metallic Return
EMF Electromotive Force
EMT Electromagnetic Transient
FB Full-Bridge
FBC Fault Blocking Converter
FRT Fault Ride Through
FSU Fault Separation Unit
GSI Grid Separation Interface
HB Half-Bridge
HEB Horizontal Energy Balancing
HSS High-Speed Switch
HVAC High Voltage Alternating Current
HVDC High Voltage Direct Current
IED Intelligent Electronic Device
IGBT Insulated-Gate Bipolar Transistor
IGCT Integrated Gate-Commutated Thyristors
IQR Interquartile Range
LCC Line Current Control
MMC Modular Multilevel Converter
MTDC Multi-Terminal Direct Current
OHL Overhead Line
PG Pole-to-Ground
140 List of abbreviations
PLES Pole Line Earthing Switch

PPG Pole-to-Pole-to-Ground
PV Photovoltaic
RCB Residual Current Breaker
RES Renewable Energy Source
ROCOC Rate of Change of Current
ROCOV Rate of Change of Voltage
RRRV Rate of Rise of Recovery Voltage
SA Surge Arrester
SF6 Sulfur hexafluoride
SM Submodule
STATCOM Static Synchronous Compensator
TCC Terminal Current Control
TEB Total Energy Balancing
TIV Transient Interruption Voltage
TRV Transient Recovery Voltage
TSO Transmission Grid Operators
TVC Terminal Voltage Control
UFD Ultra-Fast Disconnector
VCB Vacuum Circuit Breaker
VEB Vertical Energy Balancing
VSC Voltage Source Converter
WPP Wind Power Plant
WTG Wind Turbine Generator
XLPE Cross-Linked Polyethylene
Appendix 141
Appendix
A.1 Surge Arrester Characteristic
The voltage current characteristic curve of the surge arresters applied in the
simulation model is presented in Figure A-1 [Ste03].
1200
Protection Level Ures
Line to ground peak voltage (kV)
1000
800
600
Rated Voltage Ur
400
200
0
1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3 1E+4 1E+5
Current (A)
Figure A-1: Surge arrester voltage current characteristic
A.2 AC Grid Models
The AC transmission grids are modelled as three-phase Thevenin voltage sources

with concentrated source impedances, which are parameterised based on the
short-circuit power of typically transmission networks, as given in Table A-1.
Table A-1: AC transmission grid parameters
Parameter Value Parameter Value
Short circuit power S''Strong 45 GVA X/R ratio 10
(weak and strong grid) S''Weak 3.8 GVA Voltage factor [IEC16] cn 1.1
Nominal voltage uac,n
400 kV Z+/Z0 ratio 4/3
(RMSLL)
Nominal frequency fn 50 Hz
142 Appendix
A.3 WTG Model Parameters
The parameters of the WTG mode are given in Table A-2.

Table A-2: WTG model parameters
Parameter Rating
Number of WTG per WPP nWT 50
Nominal power Snom 8 MVA
Nominal AC grid voltage (LL-RMS) Ugrid,nom 690 V
Nominal grid frequency fgrid,nom 50 Hz
Nominal DC voltage UDC,nom 1.45 kV
Nominal generator voltage (LL-RMS) Ugen,nom 690 V
Nominal generator frequency fgen,nom 1.9 kV
Wind Speed vwind 11 m/s
Converter reactance (grid side) LVSC,grid 10 µH
Converter reactance (generator side) LVSC,gen 25 µH
Turbine Radius Rturb 100 m
A.4 PLL Implementation
The angular frequency of the AC required for the current vector control is detected
by a Phase Locked Loop (PLL). For angular frequency detection only the positive
sequence is relevant. Therefore, the AC voltage is transformed into the Decoupled
Double Synchronous Reference Frame (DDSRF) and the positive sequence is
used for the PLL, which ensures, that also during asymmetric AC voltages the
angular frequency is detected correctly [Teo11]. The PLL system is shown in
Figure A-2 and applied parameters are given in Table A-3.
Per unitisation ߱ ௥௘௙

ା
‫ݑ‬஺஼ ‫ݑ‬ௗ௤
DDSRF-dq- ‫ݑ‬ௗା ‫୍ܭ‬ǡ୔୐୐ ȟ߱ ߱
෥ ͳ ߠ ߱‫ݐ‬
Transformation ‫୔ܭ‬ǡ୔୐୐ ൅ Mod(2π)
‫ݏ‬ ‫ݏ‬
‫ݑ‬ଶ
Figure A-2: Schematic representation of the PLL algorithm [Teo11]

Appendix 143
A.5 MMC Control Parameters (all in per unit values)
The control parameters of the MMCs are calculated according to chapter 5 using
the MMC model parameters given in Table 4-1. All parameters are presented in
per unit (based on the MMC and grid parameters given in Table 4-1 and
Table 4-2).
Table A-3: MMC Control Parameters in per unit values
Parameter Values
AC Current KP,Iac = 1.41 KI,Iac = 4.92
CC Current KP,Icc = 0.14 KI,Icc = 0.28 KR,Icc,h = h ∙ 1.84
DC Current KP,Idc = 0.22 KI,Idc =0.44
Horizontal Balancing KP,EΣ = 1.61 KI,EΣ = 55.49
Vertical Balancing KP,EΔ = 0.80 KI,EΔ = 0
Total Energy Balancing (DC) KP,Edc =7.16 KI,Edc = 494.4
Total Energy Balancing (AC) KP,Eac = 7.16 KI,Eac = 494.4
DC Voltage KP,Udc = 5.54 KI,Udc = 1529
Line Current KP,LLC = 0.59 KI,,LLC = 162.6 KR,LLC = 2ωKP,LLC
Active/Reactive Power KP,PQ = 0.07 KI,PQ = 139.6
Grid Forming KP,Uac = 0.82 KI,Uac = 107.6
AC filter (second-order) fAC = 2 kHz ξAC =1/ξ2
CC filter (second-order) fCC = 2 kHz ξCC =1/ξ2
DC filter (second-order) fDC = 2 kHz ξDC =1/ξ2
Phase Locked Loop KP,PLL = 222 KI,PLL = 111

144
A.6
(a) Terminal Current Control (b) Terminal Voltage Control (c) Line Current Control Fault Control Method
Figure A-3: FSU current and the corresponding terminal voltages for all 48 fault cases (12 locations, fault types: PG &
PNG, fault impedance: Rflt,low = 0.1 Ω & Rflt,high = 20 Ω) in the meshed network under variation of the fault control mode
FSU Currents and Terminal Voltage Under Variation of the
Appendix
Appendix 145
A.7 Converter Behaviour During DC Voltage Restoration
Figure A-4: Converter voltage and current profiles using an DBS circuit with lumped
braking resistors for pole re-balancing; Exemplary low-impedance PG fault in meshed
MTDC test network in monopole configuration at the fault location L14 - 50%
146 Appendix
Figure A-5: Converter voltage and current profiles using a zig-zag grounding transformer
for pole re-balancing; Exemplary low-impedance PG fault in meshed MTDC test network
in monopole configuration at the fault location L14 - 50%
Appendix 147
Figure A-6: Converter voltage and current profiles using converter-controlled DC

discharge for pole re-balancing; Exemplary low-impedance PG fault in meshed MTDC
test network in monopole configuration at the fault location L14 - 50%
148 Appendix
A.8 Impact on HVDC cable system
During the fault separation process the FBCs actively reduce the grid DC voltage
to zero and even reverse the voltage polarities of the poles to control the fault
current to zero and discharge the DC network. Consequently, the dielectric
stresses imposed on XLPE cables depend on the fault current suppression control
and in case of a network in symmetric monopole configuration on the pole voltage
re-balancing method.
The voltage stresses imposed on XLPE HVDC cables are usually separated into
voltages with the same polarity and with opposite polarity [CIG12, IEC17]. The
maxima of these voltages at all DC busbars in all fault scenarios in the meshed
and the radial network are summarised in Table A-4. With the investigated re-
balancing methods and the specific design, the maximum voltage with the same
polarity occurs in the monopole grid configuration with AC grounding, due to the
asymmetric pole voltages prior to the voltage restoration process. The maximum
voltage with opposite polarity occurs in the bipolar system due to direct earthing
of the DC system. Nevertheless, the difference between the restoration methods
in regard to the voltage peaks with opposite polarity is neglectable. Even though
the peak voltages do not exceed the voltage levels of state-of-the-art switching
impulse tests for XLPE cables (Umax = 2.1. p.u. and Umin = -1.2 p.u.
[CIG12, IEC17]), the voltage waveforms deviate from the standard test profiles.
Table A-4: Maximum voltage stress on the DC cables in the FBC-based protection strategy
with the re-balancing options for all fault scenarios (absolute values)
Monopole
Bipole
DBS AC GND DC Dis.
PG PPG PG PPG PG PPG PG PPG
umax – same polarity [kV] 472 375 500 376 377 375 377 378
umax – opp. polarity [kV] 233 201 233 210 238 209 241 212
Figure A-7 shows the voltage waveforms of the positive pole for all fault
scenarios at all four DC busbars compared to the standard SI profile (reversed
polarity). For this comparison, the point in time at which the voltage travelling
wave reaches the corresponding busbar is set to tsim = 0 ms. As already shown in
Table A-4, the maximum amplitudes are smaller than the SI test peak voltage.
During the tail of the switching impulse, however, the voltage curves exceed the
envelope due to the system’s damping during the current suppression phase.
Whether these waveforms are more critical for the XLPE insulation of DC cables
than the standard SI tests has to be evaluated by experimental results and the
experience of cable manufactures.
Appendix 149
Monopole Monopole Monopole Bipole

with DBS with AC Gnd. DC Dis.
Figure A-7: Comparison between the voltage profile of the positive pole at all DC busbars
for all fault scenarios (grey) and the standard switching impulse test voltage with reversed
polarity for 320 kV XLPE cables (black) [IEC17]

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HVDC Grid Protection Based on

Fault Blocking Converters

Von der Fakultät für Elektrotechnik und Informationstechnik

Philipp Frederic Ruffing, M.Sc.

Berichter: Univ.-Prof. Dr.-Ing. Armin Schnettler

Tag der mündlichen Prüfung: 23. Juli 2020

Philipp Frederic Ruffing

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Satz: nach Druckvorlage des Autors

D 82 (Diss. RWTH Aachen University, 2020)

Aachen, July 2020

Multi-terminal HVDC systems are envisioned as a technically and economically

2 Physical and Technological Considerations ........................................ 19

3 Requirements and Evaluation Criteria................................................ 37

4 HVDC Network and Component Modelling ....................................... 45

5 Converter Controls ................................................................................ 59

6 MTDC Fault Separation Strategy ........................................................ 71

6.2 Analysis of Fault Separation Units.................................................. 81

7 System Impact ...................................................................................... 109

8 Conclusion and Further Research Needs .......................................... 119

1.1 Motivation of the topic

Regardless of the technological, operational and economic drivers for MTDC

[Her16, Tan07]. If this concept is applied to a DC grid and the separation of a

Figure 1-1: Selective separation of a faulted line in a MTDC network

1.2 State of knowledge

To evaluate the requirements on MTDC protection systems it is essential to have

1.2.1 HVDC Network and Circuit Topologies

considered in the design and the evaluation of HVDC protection strategies

Bipole with Dedicated Metallic Return

Fault Separation Units

Figure 1-2: DC network (left) and circuit topologies (right)

1.2.2 DC Fault Handling with VSCs

In the beginning of VSC-based HVDC transmission the prevailing topologies

SM1 SM1 SM1 LDC,T

Larm Larm Larm Full-Bridge SM

Fault-Feeding Converters (FFC)

All presently installed MMC-HVDC systems are based on half-bridge (HB)

An alternative to fault-feeding converters (e.g. HB-MMC) is the usage of

Figure 1-4: DC fault control scheme [Ruf19a]

1.2.3 Multi-Terminal HVDC Network Protection Philosophies

of a DC grid towards a country or synchronous zone exceeds the network’s

Protection Zone: DC Line Protection Zone: DC Grid

fast protection & protection separation

uDC voltage on healthy lines uDC voltage on healthy lines

voltage on faulted line voltage on faulted line

1.2.4 Fault Handling in HVDC Networks with Fault-Blocking Converters

Table 1-1: Classification of the impacts of DC contingences on the DC networks AC-PoCs

A generic fault clearing process for FBC-based HVDC protection systems is

tf tdet tloc tsep trst

Fault Detection and Discrimination

Fault Current Reduction

Fault Separation Units

Another unresolved issue is the identification and analysis of appropriate FSUs

or simplified switching devices5 [Cha16, Pet16, Dan18]. Moreover, the

Figure 1-7: Pole-voltages in case of pole-to-ground and a pole-to-pole-to ground fault in a

Impact on surrounding AC grids

1.3 Objectives and Investigative Approach

x MTDC fault control – A fault control concept is required, which is

different grounding and circuit configurations (i.e. symmetric monopole or bipole

Technological considerations Evaluation criteria

Elaboration of a converter control system

Development and enhancement of the protection strategy’s building blocks