Doncker学生博士论文 Exploiting the Full Potential of Silicon Carbide Devices via Optimized Highly Integrated Power Modules

Alexander Stippich
Exploiting the Full Potential of

Silicon Carbide Devices via Optimized
Highly Integrated Power Modules
Aachener Beiträge des ISEA Band 155

Exploiting the Full Potential of Silicon
Carbide Devices via Optimized Highly
Integrated Power Modules
Von der Fakultät für Elektrotechnik und Informationstechnik

der Rheinisch-Westfälischen Technischen Hochschule Aachen
zur Erlangung des akademischen Grades eines Doktors der
Ingenieurwissenschaften genehmigte Dissertation
vorgelegt von
Alexander Stippich, M. Sc.
aus Langenfeld (Rhld.)
Berichter:
Univ.-Prof. Dr. ir. Dr. h. c. Rik W. De Doncker
Distinguished Professor Alan Mantooth, Ph.D.
Tag der mündlichen Prüfung: 27. Januar 2021
Diese Dissertation ist auf den Internetseiten

der Universitätsbibliothek online verfügbar.
AACHENER BEITRÄGE DES ISEA
Vol. 155
Editor:
Univ.-Prof. Dr. ir. Dr. h. c. Rik W. De Doncker
Director of the Institute for Power Electronics and Electrical Drives (ISEA)
RWTH Aachen University
Copyright Alexander Stippich and ISEA 2021

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system,
or transmitted in any form or by any means, electronic, mechanical, photocopying, recording,
or otherwise, without prior permission of the publisher.
ISSN 1437-675X
Institute for Power Electronics and Electrical Drives (ISEA)

RWTH Aachen University
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Tel: +49 (0)241 80-96920
Fax: +49 (0)241 80-92203
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Vorwort
Die vorliegende Dissertation entstand während meiner Tätigkeit als Wissenschaftlicher

Mitarbeiter am Institut für Stromrichtertechnik und Elektrische Antriebe (ISEA) der
Rheinisch-Westfälischen Technischen Hochschule (RWTH) Aachen. Im Folgenden möchte
ich mich bei den Personen bedanken, die mich bei der Erstellung der Arbeit unterstützt
haben.
Ich möchte mich herzlich bei meinem Doktorvater Prof. Rik W. De Doncker bedanken, der
mir die Möglichkeit zur Promotion gegeben hat und mich dabei fortlaufend unterstützt
hat. Prof. Alan Mantooth danke ich herzlich für die Übernahme des Korreferats. Ich
möchte an dieser Stelle auch allen Kollegiaten des DFG-geförderten Graduiertenkollegs
mobilEM für die interessante und erfolgreiche Zusammenarbeit danken.
Des Weiteren möchte ich mich sehr herzlich bei allen Mitarbeitern des ISEAs und ins-
besondere bei der LEA-Gruppe für die zahlreichen fachlichen Gespräche sowie diverse
gemeinsame soziale Aktivitäten bedanken. Durch das großartige Gemeinschaftsgefühl am
ISEA wird das Arbeiten wirklich zur Freude und macht die Dissertation in dieser Form
erst möglich. Dabei möchte ich mich ganz besonders bei meinen ehemaligen Bürokollegen
aus dem R223, Silvano Taraborrelli, Jochen Henn und Rafael Goldbeck für das immer
lustige Büroklima und abwechslungsreiche Rennen bedanken. Ebenso großer Dank geht
an die Bürokollegen aus dem B12, Alexander Sewergin, Hendrik Wienhausen und David
Bündgen, mit denen das Arbeiten immer Spaß gemacht hat.
Zahlreiche Studenten haben mich bei der Erstellung der Arbeit unterstützt und damit zum
Erfolg der Dissertation beigetragen. Ein besonderer Dank geht dabei an Maximilian Bat-
tefeld, Lukas Fräger, Abinash Pradhan, Georg Götz, Daniel Philipps und Tobias Kamp.
Für das Korrekturlesen der Arbeit möchte ich mich bei Hendrik Wienhausen, Christoph
van der Broeck, Markus Neubert, Severin Klever und David Bündgen bedanken.
Abschließend möchte ich mich ganz herzlich bei meiner gesamten Familie bedanken, die
mich während der gesamten Zeit immer unterstützt haben. Von ganzen Herzen danke ich
meiner Frau Hannah, die mir immer und bei Allem zur Seite stand und steht, und die
notwendige Geduld mit mir beim Schreiben der Dissertation aufgebracht hat.
Aachen, April 2021 Alexander Stippich

iv
Abstract
This work investigates the design optimization of tailor-made power modules for power
electronic applications and topologies yielding a maximum device utilization of modern
wide bandgap devices. The superior electrical characteristics of silicon carbide (SiC) de-
vices enable converter operation with higher current densities, faster switching transients
and increased switching frequencies. Dc-dc converters designed for high power densities
strongly benefit from SiC devices as the power density increases with increased switching
frequency due to smaller passive devices. However, the fast switching of the SiC power
device amplifies the effect of power module parasitics on the electrical switching behavior.
Parasitic inductances and capacitances of the module and the device can lead to over-
voltages, voltage ringing and displacement currents. This limits the safe operating area
of the devices. Optimizing for best electrical properties usually opposes good thermal
characteristics and, thus, limits the current capabilities of power modules and converters.
While recent work has investigated many packaging concepts that yield either best elec-
trical or thermal properties, a combination of both properties that yields an optimized
overall performance of a power electronic system has not been addressed yet. However,
it is inevitable to optimally combine electrical and thermal properties to utilize the full
benefits of wide bandgap devices in power converters. Hence, this work demonstrates
how design concepts and methods that address combined electrothermal behavior can re-
alize power modules with higher integration and device-utilization potential than existing
technologies.
Due to higher current densities and consequently smaller devices, efficient cooling of SiC
devices is challenging. Micro-channels provide a low-volume but effective cooling solution
that is able to dissipate highest heat flux densities and can be integrated into the base-
plate. However, due to the integration of the cooling structure and removal of materials,
the thermal capacity of such a cooling structure is low. As a result, the semiconductors
suffer from many thermal cycles with large amplitudes. These thermal cycles cause stress
within the materials and their interfaces leading to fatigue. Hence, the lifetime of the
power modules is reduced. Thermal buffers provide a solution to mitigate this disadvan-
tage by inserting additional thermal capacity into the design of power modules. They
dampen thermal cycles and, consequently, enhance the lifetime of power modules. Based
on simulations over realistic mission profiles, small thermal buffers achieve an increased
lifetime of power modules by a factor of four or more compared to modules without ther-
mal buffers. It is a simple yet powerful solution for enhancing lifetime and a cost-effective
alternative to increasing semiconductor die area.
v
The electrical performance of SiC devices is largely limited by the parasitic inductances
and capacitances within the module. A low-inductive power module is designed that is
optimized for the target application and topology of a synchronous boost converter oper-
ated at a very high switching frequency. Due to the high switching frequency, the entire
dc-link capacitance required for the converter operation can be integrated into the power
module that minimizes the parasitic inductance of the commutation loop. The module
layout is based on a planar layout and conventional manufacturing techniques and does
not require complex, three-dimensional packaging techniques. The power module achieves
fast switching transients of more than 100 V/ns in practice. The switching transients are
dominated by the parasitic capacitances of the SiC devices themselves because influences
and effects of the parasitic elements of the packaging are successfully minimized. Conse-
quently, the semiconductor devices are leveraged to their fullest potential.
For the demonstration of the advantages of the presented approach on a system level, the
optimized power module is combined with passive components, sensors and control cir-
cuitry to build a synchronous boost converter. Despite its hard-switching operation mode,
it achieves a high switching frequency and efficiency. The converter reaches a power den-
sity of 75 kW/l. The excellent power density and efficiency are achieved by the highly
integrated power module, which uniquely combines multiple key features to fully exploit
the potentials of SiC devices. The stellar thermal performance enables extremely high
switching frequencies above 300 kHz that allows the integration the entire dc-link capaci-
tance into the module. This enables a low-inductive power module design with excellent
electrical characteristics and switching SiC devices at full speed that minimizes losses and
allows raising the current density further. The resulting power converter highlights the
potential of electrically and thermally optimized, application-specific power modules that
integrates the SiC devices with gate-drivers, cooling structures and capacitors. For the
development of electric vehicles and more electric aircrafts, such modules present a unique
opportunity to develop fast switching dc-dc converters with highest power densities.
vi
Contents
1 Introduction 1
2 State of the Art and Literature Review 7

2.1 Literature Review of Packaging Technologies . . . . . . . . . . . . . . . . . 9
2.1.1 Conventional Packaging Techniques . . . . . . . . . . . . . . . . . . 9
2.1.2 Advanced Packaging Techniques . . . . . . . . . . . . . . . . . . . . 11
2.2 Literature Review of Fluid Cooling Structures . . . . . . . . . . . . . . . . 12
3 Micro-Channel Cooling Structures for SiC MOSFETs 15

3.1 Simulation of Micro-Channel Structure . . . . . . . . . . . . . . . . . . . . 16
3.1.1 Investigation of Different Materials . . . . . . . . . . . . . . . . . . 21
3.1.2 Geometry Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Experimental Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.1 Detailed Simulation of the Prototype . . . . . . . . . . . . . . . . . 26
3.2.2 Thermal Impedance Measurements . . . . . . . . . . . . . . . . . . 30
3.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4 Thermal Buffers for Enhanced Lifetime 37

4.1 Thermal Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2 Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.1 Thermal Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.2 Mission Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2.3 Loss and Lifetime Estimation . . . . . . . . . . . . . . . . . . . . . 46
4.3 Lifetime Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.3.1 Lublin cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.3.2 WLTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5 Application-Specific Power Module 57

5.1 Design of Power Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.1.1 Analysis of Parasitic Elements . . . . . . . . . . . . . . . . . . . . . 61
5.2 Double-Pulse Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.2.1 Power Module for Double-Pulse Tests . . . . . . . . . . . . . . . . . 68
5.2.2 Rogowski Coil Current Measurement and Post-Processing Procedure 73
5.2.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
vii
Contents
6 Highly-Integrated DC-DC-Converter 103

6.1 Component Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.1 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.2 Control Circuits and Sensors . . . . . . . . . . . . . . . . . . . . . . 106
6.1.3 Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . 107
6.2 Converter Prototypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.2.1 Device Loss Estimation . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.2.2 EMI Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.2.3 Efficiency Measurements . . . . . . . . . . . . . . . . . . . . . . . . 113
6.2.4 Comparison of Converter Prototype . . . . . . . . . . . . . . . . . . 115
6.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7 Conclusions and Outlook 119

7.1 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
7.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
A Appendix 125
A.1 Cooling of SiC MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
A.1.1 Material Parameters for Simulation . . . . . . . . . . . . . . . . . . 125
A.1.2 Thermal Impedance Measurements . . . . . . . . . . . . . . . . . . 125
A.1.3 Additional Measurements of Milled Micro-Channel Structure . . . . 127
A.1.4 Etched Micro-Channel Cooling Structure . . . . . . . . . . . . . . . 128
A.1.5 3D-printed Cooling Structure as Baseplate Replacement . . . . . . 130
A.2 Thermal and Lifetime simulation . . . . . . . . . . . . . . . . . . . . . . . 133
A.2.1 Additional Data of WLTC for Integrated Power Module . . . . . . 133
A.2.2 Lublin Cycle Results with Integrated Power Module with SiC Buffers135
A.2.3 Lublin Cycle Results with Conventional Power Module . . . . . . . 138
A.3 Double-Pulse Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 143
A.3.1 Decomposition of Shunt . . . . . . . . . . . . . . . . . . . . . . . . 143
A.3.2 S-Parameter Measurement of Shunt . . . . . . . . . . . . . . . . . . 143
A.3.3 Shunt Measurements With Compensated Delay . . . . . . . . . . . 144
A.4 Power module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
A.4.1 Additional Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 148
A.4.2 Additional Measurement Results . . . . . . . . . . . . . . . . . . . 148
A.4.3 Simulating Double-Pulse Test with SPICE . . . . . . . . . . . . . . 154
A.5 Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
B Acronyms 159
C Symbols 161
List of Figures 165
List of Tables 173
Bibliography 175
viii
1 Introduction
The indispensable reduction of green-house gases to reduce global warming is a key driving
factor for the transformation of the energy supply towards renewable energies [120]. For
this transformation, power electronics play an important role as it is of the heart of
any modern electrical power conversion system. Efficient power electronics are a key-
enabling technology for almost all future stationary and non-stationary applications. For
example, photovoltaic system [15], wind turbines [13], future dc grids [30], [154], [155] and
appliances [157] are not possible without power electronic converters. For the mobility
sector, power electronics convert the stored energy into motion, regardless of the vehicles
being powered by batteries, catenary systems or hydrogen fuel cells.
The health threatening air pollution in urban areas [184] is an additional motivation for
the reduction of mobility services based on fossil fuels. More electric aircraft are being
developed to cut emissions in air traffic [60]. Electric vehicles are gaining traction to
reduce emission from road-bound mobility [164]. Moreover, electric vehicles offer the
possibility to reduce air pollution especially in urban area as they reduce local emissions
[7]. To make the development of electric vehicles economically feasible and sustainable,
it is necessary to increase efficiency and reduce cost, size and weight of power electronic
components and systems.
A conventional drive-train architecture of electric vehicles exhibits a single high-voltage

battery with a nominal voltage rating of approximately 400 V [132] that is directly con-
nected to the drive inverter and have the same voltage level [94], [142]. With the require-
ment of ultra-fast charging of batteries, drive-trains with even higher dc-link voltages
up to 800 V are developed [165] as this allows reducing the charging time of the battery
systens within the same current rating [76] and enables charging powers of 240 kW [25]
or more [165]. For future electric drive-train architectures, additional high-power dc-dc
converters are proposed to overcome the limitation of a single, combined and high dc-link
voltage [58], [94], [139], [159]. With decoupled voltage levels of the battery, the drive in-
verter and the charging infrastructure, several benefits can be achieved on a system level.
A lower battery voltage is a desirable design option to improve the battery lifetime [131].
Modular battery packs allow to combine high-power and high-energy battery technologies
in multiple units as hybrid battery systems, which promises cost and weight reduction
and efficiency improvements [9], [133], [198]. With decoupled voltage levels, the inverter
and electrical machine can be operated more efficiently at an adjustable dc-link voltage
with the aid of dc-to-dc converters [58], [94], [139]. Switching losses of the inverter can
be reduced with an adjusted dc-link voltage as function of speed of the machine [127].
1
1 Introduction
Hence, the ongoing trend towards the electrification of the mobility sector and the next-
generation drive-train architectures demand highly compact power electronic converters
[159], [186]. For all mobile applications, high power densities and efficiency of the con-
verters are key properties [121]. The size and weight have a significant influence on the
efficiency of the mobile system. The required high power densities are achievable with
modern wide-bandgap (WBG) semiconductors such as gallium nitride (GaN) or silicon
carbide (SiC) devices. While the potentials of WBG devices are known for decades [10],
[182], commercial availability has only emerged in the recent years. WBG devices exhibit
superior material properties that enable devices with faster switching transients at higher
voltages compared to silicon (Si) devices [80], [81].
As a result of the fast switching transients, the devices are able to operate at much higher
switching frequencies compared to Si-based devices, leading to an increased power density
because of the reduced size of passive components in power electronic converters [89]. The
potential of these new devices is limited by parasitic effects of power electronic packages.
Stray inductances prohibit fast switching transients due to voltage overshoots, ringing and
increased switching losses [24]. Commercially available SiC power modules exhibit high
stray inductances of more than 30 nH [109], [193]. Hence, new packaging and integration
methods are required for fast switching transient to overcome limits imposed by current
packaging technologies [36].
Due to ultra-fast switching transients, new packaging and integration methods are re-
quired as parasitic effects of commercially-available packages limit the switching speed
[36]. Consequently, optimized power module are investigated that achieve stray induc-
tances below 5 nH [32], [33]. Packaging techniques with three dimensional (3D) structures
are examined to achieve best switching capabilities [99], [194], [204]. Novel thermal cool-
ing concepts are also investigated [74], [110], [119], [148]. However, the publications focus
on either thermal or electrical design aspects and present thermal resistance measure-
ments or only double-pulse measurements. Power electronic converters that exploit the
full potentials are only rarely presented. When converters are constructed with novel
low-inductive power modules, they do not utilize the full potential of the new devices and
only provide small gains in power density as the switching frequency is set low [33]. In
contrast, this thesis aims to optimally combine electrical and thermal design aspects of
a highly-integrated power electronic module to enable dc-dc converters with very high
power density.
2
Research Objectives
The objective of this thesis is to free fast SiC devices from the operational limitations that
are imposed by the package design. Many novel packaging concepts rely on advanced man-
ufacturing techniques and 3D structures that excel in specific areas. Compared to this, the
objective of this thesis is to adapt existing technologies and to optimally design a package
from an application perspective. The existing concepts are evaluated, adapted and tuned
towards the application with an emphasis on a simple and feasible implementation. In
order to utilize the full electrical potentials of SiC devices, the parasitic properties of
packages must be minimized and the high heat flux densities of must be handled. Hence,
a package design is required that is able to exploit the full thermal and electrical po-
tentials of SiC devices at the same time to achieve the highest performance in a power
electronic converter. Switching transients must be chosen to be as fast as possible for
lowest switching losses even at elevated switching frequencies.
The potentials and implications of an application-specific power module with fully ex-
ploitable SiC devices shall be investigated on a system level for a power electronic con-
verter. The power electronic module and converter shall be designed to push the operating
boundaries and utilize the benefits of a high switching frequency such as a reduced size
of passive components. Consequently, the power density of power electronic converters
shall be pushed to higher levels to enable new applications with extreme requirements
on size and weight. The implications on the efficiency and electromagnetic interference
(EMI) of such a SiC converter designed for highest power densities shall be determined
and potentials for future developments identified.
Statement of Novelty
In this thesis, a highly-integrated power module is developed that allows pushing the
switching frequency of power electronic converters to the limit. The size of the passive
components is reduced and, therefore, a leap in the power density of the overall converter
is achieved. This is the result and key outcome of several sub-aspects investigated in this
thesis, which are optimally combined in the power electronic converter.
Cooling structures based on micro-channels are developed for the cooling of SiC devices.
The structures are designed with coarser dimensions compared to micro-channel cooling
structures found in literature for a robust device with lessened requirements on the clean-
ness of the fluid coolant. They provide a low-volume but effective cooling solution that
is able to cool highest heat flux densities and can be integrated into the baseplate. It is
one key element for high power density converters based on SiC devices due to their high
current densities compared to Si devices. However, due to the integration of the cooling
structure and removal of materials, the thermal capacity of such a cooling structure is
3
1 Introduction
low. As a result, the semiconductors are subjected to many thermal cycles with large
amplitudes. As thermal cycles cause stress within the materials and their interfaces and
lead to fatigue, the lifetime of the power modules is reduced. Thermal buffers provide a
solution to mitigate this disadvantage by inserting additional thermal capacity into the
design of power modules. They reduce thermal cycles and, consequently, enhance the
lifetime of power modules. Based on realistic mission profiles, thermal buffers are system-
atically investigated and demonstrate that even small thermal buffers are able to increase
lifetime of power modules by a factor of four or more. It is a simple yet powerful solution
for enhancing the lifetime and a cost-effective alternative to increasing semiconductor die
area and allows tuning the lifetime for specific applications.
The package developed during this thesis is designed based on a lateral layout and can be
manufactured with conventional techniques such as wire-bonding and die-attach solder-
ing. A low-inductive power module is designed that is optimized for the target application
and topology of a synchronous boost converter at very high switching frequency up to
333 kHz. Due to the high switching frequency, the entire dc-link capacitance can be inte-
grated into the power module. This integration minimizes the parasitic inductance of the
commutation loop and makes it possible achieve very fast switching transients of more
than 100 V/ns in practice. The switching transients are dominated by the parasitic capac-
itances of the SiC devices itself because influences and effects of the parasitic elements of
the packaging are successfully minimized. Consequently, the semiconductor devices are
leveraged to their fullest potential. The application-specific power module design enables
power electronic converters with highest power densities for future mobile applications.
For the transient analysis of the power module, a digital post-processing procedure is
developed for a low-inductive, accurate measurement of the current in highly-integrated
power modules via a Rogowski coil during double-pulse measurements. This digital pro-
cedure allows the usage of a completely passive Rogowski coil for high-bandwidth current
measurements for double-pulse tests. The Rogowski coil is directly connected to an os-
cilloscope and is of extremely low cost. The influence of parasitic properties of the mea-
surement setup and equipment on the results is investigated in detail. The measurements
show that the smallest parasitic elements can significantly influence the results when
investigating WBG devices of which the current and voltage oscillations are appearing
above 10 MHz. It is further revealed that the current measured with standard coaxial
shunts exhibits an inductive coupling to the sensing port that makes them unsuitable for
measurements of fast switching transients of WBG devices.
For the demonstration of the advantages of the presented approach on a system level, the
optimized power module with the integrated cooling structure is combined with passive
components, sensors and control circuitry to build a synchronous boost converter. Despite
its hard-switching operation mode, it achieves a high switching frequency of 333 kHz and
a high efficiency of 98.2 %. The converter reaches a power density of 75 kW/l. The high
power density and efficiency are achieved by the highly integrated power module, which
uniquely combines multiple key features to fully exploit the potentials of SiC devices. The
low thermal resistance of the package allows dissipating high heat flux densities. This
4
enables the operation of the SiC devices at high switching frequencies as the switching
losses can be dissipated. This high switching frequency allows the integration of the entire
dc-link capacitance into the module. This enables a low-inductive power module design
with excellent electrical characteristics and switching SiC devices with fastest switching
transients. This in turn minimizes losses and allows raising the current density and
switching frequency further, creating a self-amplifying effect until the characteristics of
the semiconductor device itself and the passive components of the converter are limiting.
The resulting power converter highlights the system level potential of electrically and
thermally optimized, application-specific power modules. For the development of electric
vehicles and more electric aircraft, such modules present an enabling technology to develop
dc-dc converters with highest power densities.
Outline of this Thesis
This thesis is structured in 6 major chapters, which are briefly summarized.
Chapter 2: State of the Art and Literature Review
A short overview on the state of the art and novel techniques currently investigated in
literature is presented. The overview covers the thermal and electrical design of power
electronic modules.
Chapter 3: Cooling Structures for SiC MOSFETs
Based on the literature review, a micro-channel cooling structure is investigated as a

solution to effectively cool SiC devices and that is integrated into the power module.
Compared to concepts presented in literature, the structures are coarser to lower the
requirements on the cleanness and the particle size in the coolant fluids. Micro-channel
structures directly milled into the baseplate are investigated. Several design aspects are in-
vestigated with computational fluid dynamics (CFD) simulations to achieve a low thermal
resistance that fulfills the cooling requirements for the target application. The simula-
tions are verified based on experimental thermal impedance measurements with a manu-
factured prototype. The results demonstrate that a very high heat flux can be dissipated
from small SiC devices with a small required volume and without requiring double-sided
cooling techniques.
5
1 Introduction
Chapter 4: Thermal Buffers for Enhanced Lifetime
Highly-integrated cooling structures achieve low thermal resistances, but also lower the
thermal capacity that negatively impacts the thermal impedance. Thermal buffers are in-
vestigated that specifically add thermal capacity to the power module without influencing
the thermal resistance. Lifetime simulation with realistic mission profiles of driving cy-
cles are conducted for inverter operation of the semiconductor. The simulation results of
modules with and without thermal buffers are compared. For an integrated micro-channel
cooling structure, thermal buffers are able to increase the lifetime of power modules con-
siderably.
Chapter 5: Application-Specific Power Module
Using conventional manufacturing techniques only, a low-inductive, highly-integrated SiC

power module is developed that is specifically optimized for the presented application. It
integrates the gate-driver, dc-link capacitors and a cooling structure. The parasitic prop-
erties of the modules are statically analyzed first based on simulations and experiments.
For accurate double pulse measurements, an additional power module is manufactured
incorporating a low-inductive Rogowski coil current probe. The effects of the equipment
on the measurement are analyzed and investigated for the presented power module. Ex-
tensive double-pulse measurements are conducted to validate the transient behavior of
the developed prototype. The low-inductive and low-loss characteristics of the electrical
design are demonstrated.
Chapter 6: Highly-Integrated DC-DC-Converter
Based on the previous chapters, the developed power module is used to realize a syn-
chronous boost converter for a specific application. A high-frequency inductor is designed
and manufactured. Peripherals such as a microcontroller (MCU) for the control of the
converter, current and voltage sensors are added to form a complete dc-dc converter sys-
tem. Efficiency and EMI measurements are conducted up to full power of the converter
to demonstrate the capabilities of the power module and the converter design.
Chapter 7: Conclusion and Outlook
The last chapter summarize and concludes the results of the previous chapters. Further-
more, potentials for future developments are presented that are able to improve the power
density of dc-dc converters even further.
6
2 State of the Art and Literature Review
wire bonds
solder die die DBC
interface material baseplate
heatsink
Figure 2.1: Conventional package structure.
Packaging of power semiconductors is a multi-physics design problem. Packaging requires

careful design decisions regarding thermal, electrical and mechanical aspects of the power
module.
A schematic representation of a state-of-the-art package design for insulated-gate bipolar

transistor (IGBT) power modules is shown in Figure 2.1. The power module is based
on a thermally conductive yet electrically insulating substrate, the direct bonded copper
(DBC) ceramic substrate. Copper is bonded to both sides of a sheet of a ceramic by a
high temperature oxidation process. Various ceramic materials can be used, for example
aluminum oxide (Al2 O3 ) or aluminum nitride (AlN). Using an active metal brazed (AMB)
process, similar substrates are also realized based on different ceramics, for example silicon
nitride (Si3 N4 ).
The bottom layer of the DBC is usually soldered onto a baseplate. The layer on the top of
the substrate is structured into an electrical layout. The semiconductor die are soldered
to this side of the DBC. The top-side gate and emitter pads of the IGBT die are bonded
with heavy-wires using an ultrasonic welding process. The bond wires are usually made
of aluminum.
The conventional packaging methods have also been applied to power modules based
on SiC metal-oxide semiconductor field-effect transistors (MOSFETs). A picture of an
opened module is depicted in Figure 2.2, where the SiC MOSFET and Schottky-barrier
diode (SBD) die are soldered to the DBC and connected via heavy-bond wires. The
datasheet of this module lists 30 nH as stray inductance [193]. This does not include
any additional stray inductance of the connection to the dc-link capacitor. Such a high
stray inductance leads to voltage overshoots and voltage ringing with fast switching SiC
devices.
7
Figure 2.2: SiC power module from Wolf-

speed [193]. Figure 2.3: 35 nH power module.
Voltage uDS in V
Voltage uDS in V
800 800
400 400
0 0
0 0.05 0.1 0.15 0.2 0.25 0.3 0 0.05 0.1 0.15 0.2 0.25 0.3
Time in µs Time in µs
(a) Turn-on (b) Turn-off
Figure 2.4: Voltage waveforms during switching with high stray inductance.
For demonstration purposes, a comparable 35 nH half-bridge power module is manufac-

tured with the same 1.2 kV devices [192], which is depicted in Figure 2.3. The stray
inductance is verified with an impedance analyzer. The low-side voltage waveforms uDS
of the half-bridge during turn-on and turn-off at 800 V operating as a synchronous boost
converter are presented in Figure 2.4.
The resulting voltage transients reach 55 V/ns. The voltage overshoot at current of approx-
imately 30 A is 150 V while the SiC MOSFET is rated for a dc current of 98 A. For very
fast voltage and current transients, the stray inductance limits the safe operating area due
to the high over-voltages and causes additional EMI due to voltage ringing. Hence, the
stray inductance of conventional packaging technologies must be adapted and optimized
for SiC devices. At the same time, the thermal performance of modules must not be
neglected.
8
2.1 Literature Review of Packaging Technologies
DC+ bond wire

DC+ diode
AC G
S capacitor
AC DC+ DC- MOSFET
G AC ceramic
DC-
S
G S G S DC- GS GS copper
(a) Layout of (b) Layout of [167] (c) Layout of [32]
[193]
Figure 2.5: Layouts of lateral SiC power modules
Conventional cooling systems use a separate heatsink that is air or water cooled. The
heatsink is thermally attached to the power electronics module via a thermal interface
material (TIM). A typical example for a TIM is thermal grease based on silicone. The
grease fills the voids between the two surfaces of the cooler and the baseplate of the
module. While this gives better results than using no TIM at all, the materials usually
exhibit a very low thermal conductivity [37] and significantly contribute to the overall
thermal resistance [42].
As a consequence of the non-optimal electrical performance outlined in the previous sec-

tion, many different concepts and designs are proposed for low-inductive power modules
in current literature for SiC devices [105], [145]. In the following, a literature review is
presented with a focus on half-bridge power modules with a voltage rating up to 1200 V.
2.1.1 Conventional Packaging Techniques
Conventional power module packaging has been investigated and optimized for SiC devices
in literature. The designs utilize the conventional packaging techniques such as a lateral
layout for the power loop on a DBC with bond wires used as the top-side connection.
In Figure 2.5 a selection of three different layouts for power modules is presented. The
left layout in Figure 2.5a represents the design depicted in Figure 2.2 from [192], which
is commercially available. As the module is a three-phase module, the layout must be
designed in such a way that the plus and minus connections of the individual half-bridges
9
can be easily connected to each other and the dc link connection. The distance between the
positive and negative terminals is quite large, resulting in a high power-loop inductance of
over 30 nH [109]. Additionally, the gate and Kelvin-source contacts are located far away
from the gate and source pads of the die. This results in a large gate loop inductance of
about 15 nH - 30 nH [83]. Both high parasitic inductances limit the maximum possible
switching speeds of the commutation cell.
The layout in Figure 2.5b, presented in [167], eliminates the problem of the large gate-
loop inductance by locating the gate and Kelvin source pads directly beside the die,
resulting in a low gate-loop inductance. The power-loop stray inductance of a single
half-bridge layout remains large with 30 nH, which is caused by the required space for
the diodes, but also because of a modular approach. A low power loop stray inductance
is achieved by connecting multiple of the shown layout in an anti-parallel layout. This
way, the direction of the current in each module is opposed to the direction of the current
of the adjoining modules, resulting in a magnetic flux cancellation that lowers the stray
inductance. However, the plus and minus terminals for the individual power modules are
in alternating order, but still must be connected to the main dc-link capacitance that
adds additional stray inductance.
The layout in Figure 2.5c presented in [32], [33] pursues the goal of the lowest possible
parasitic inductance with conventional packaging. As the stray inductance of a power
module is proportional to the enclosed area of the conductor loop, the enclosed area of
the loop must be reduced. The plus and minus connections of the module are located right
next to each other and the semiconductor die are placed as close as possible to minimize
the enclosed area. With a simulated stray inductance of 2.4 nH for the power-loop and
3 nH for the gate-loop, both parasitic inductances are minimal. Twice the number of
bond wires is used compared to the module in Figure 2.5a to reduce the stray inductance.
The gate loop is kept small by directly locating the gate pads and pins next to the die.
A small capacitor is added onto the DBC to bypass the stray inductance to the external
dc-link capacitor during the switching instant. The layout presented in [54] follows a
similar design but replaces the bond wires with an all-planar connection technique that
further reduces the stray inductance. The module exhibits a calculated stray inductance
of 1.6 nH.
In [183], a full-bridge module is designed for an unidirectional bridgeless-boost topology for

power factor correction. Local bypass capacitors are added to minimize the commutation
loop during switching. The gate drivers, which are also based on SiC to be able to operate
at high temperatures, are integrated into the package to form an intelligent power module
(IPM). The bridgeless-boost converter is able to switch at up to 500 kHz.
As a summary, low-inductive power modules can be achieved with conventional packaging

techniques by minimizing the enclosed area of the power and gate loops. It requires the
placement of the active devices in close proximity to each other, which makes it difficult
to cool these devices when a high power loss is expected.
10
2.1.2 Advanced Packaging Techniques
Various different novel approaches are presented in literature that work towards minimiz-
ing the stray inductances of power modules and to utilize the full potential of SiC devices.
In the following, an overview of some of these approaches is presented.
To remove the conventional bond wires that have a high resistance, a high stray inductance
and a low reliability, flip-chip bonding is investigated for SiC devices in [143], [144]. The
bond wires are substituted by small copper connectors with an array of solder balls that
are bonded onto the die and the substrate. With this approach, a SiC half-bridge module
with stray inductance of under 5 nH is achieved [143].
In [99], [196] power modules with SiC MOSFETs and SBDs soldered between two DBCs
are outlined. With a lateral structure of the power loop, a stray inductance of about
14 nH is achieved [99]. A significantly reduced stray inductance of 2.6 nH is achieved when
designing a 3D power loop [196]. Vertical interconnections between the top and bottom
DBC are utilized that minimizes the enclosed area and, thus, the stray inductances. Local
decoupling capacitors are implemented on a printed circuit board (PCB) to bypass the
stray inductance of the main dc-link capacitor during the switching instant.
3D packaging in [204] is examined with stacked devices and integrated gate drivers to
achieve best switching capabilities. The half-bridge power module with vertically in-
terconnected high-side and low-side SiC MOSFETs based on a flexible thin epoxy-resin
dielectric substrate material is presented. The stray inductance of the bondless module
is simulated 1.5 nH.
In [106], a 3D design is presented that is based on multilayer Si3 N4 ceramic substrate. Vias
through the ceramics are utilized to optimize the electrical multilayer layout to reduce
the parasitic stray inductance. The module is transfer molded and local capacitors and
damping resistors are placed on top of module. With this design, a stray inductance of
1.6 nH is calculated from double-pulse measurements.
[147] presents a concept for a compact and low-inductive half-bridge commutation cell
that integrates the gate drivers and current sensor to an IPM. The design is based on
a copper diamond heat-spreader and a high temperature cofired ceramics (HTCC) logic
board. By using a HTCC substrate on top of the SiC MOSFETs, the power-loop has been
realized without bond wires to reduce the power-loop stray inductance to about 5 nH.
Another 3D package is presented in [35] that uses a spring interconnection for stacked
submodules. Two of such submodules form a half-bridge power module. The module
consists of Si IGBTs and SiC SBD. A low-inductive behavior is achieved by opposed
forward and return currents within the individual submodules, which result in 2 nH of
stray inductance. A material mix of DBC and a low temperature cofired ceramics (LTCC)
interposer is used to manufacture the bondless power module.
11
In recent years, research has also been conducted towards the embedding of semicon-
ductors into high-current PCBs [113], [115]. The advantages of this approach are the
3D structure that leads to low parasitic inductance of about 2.8 nH [114]. However, the
thermal design of such an approach is challenging [111]. This approach is also being
investigated with SiC devices and stray inductance of only 1.7 nH are achieved [107].
A power chip on chip approach is presented in [128], [129]. The active devices are placed
on top of each other and are embedded into a PCBs similar to the previous designs with
embedded die. Due to the placement on top of each other and nearby capacitors, the
power loop is small and the stray inductance is estimated below 2 nH.
Overall, the presented excerpt of the literature indicates that a vast amount of research
is conducted towards bondless power modules, i.e. modules that replace the bond wires
with different bonding techniques. This is in order to reduce the stray inductance [145],
but also to increase the reliability as bond wires are a common source of failure in SiC
power modules [14]. Furthermore, 3D packaging techniques are investigated as a way
to reduce the stray inductance compared to lateral structures. New materials such as
HTCC, LTCC and epoxy-resin substrates are utilized within the power modules or are
used to integrate gate-driver into the power modules.
2.2 Literature Review of Fluid Cooling Structures
Many sophisticated and integrated fluid cooling technologies have been evaluated for
power electronic devices. For example, a large pin-fin fluid cooling structure is utilized
in the Infineon HybridPACK2 [64], [205] with Si IGBTs. The pin-fin structure and the
baseplate are manufactured in one piece, which eliminates the TIM. Although this is
an example for a cooling structure incorporated with the power module, the resulting
structure is still rather large and voluminous, increasing weight and cost.
The Danfoss ShowerPower ® concept [119], [163], [170] can be attached to the baseplate
of conventional modules. It uses a plastic meander structure and parallel cells to ensure
a homogeneous cooling effect on the baseplate of the power electronic module, which also
eliminates the TIM.
An approach for integrated cooling structures is the elimination of the baseplate of power
modules and directly cooling the backside of the DBCs. The coolant is moved as close
as possible to the heat source, i.e., the semiconductor devices. The ceramic layer of the
DBC still provides electrical insulation and water or a mixture of water and glycol can be
used as coolant fluid. In comparison to traditional cooling techniques of semiconductor
power modules, several material layers such as the copper baseplate and the solder layer
are omitted. One concept based on this idea is presented [42] where two DBC are bonded
together using additional and structured copper layers, forming a 3D cooling structure
12
2.2 Literature Review of Fluid Cooling Structures
between the two DBCs. Impingement jet cooling is another approach that has recently
been demonstrated for the application to power electronics for discrete devices [74] and
power modules [73], [110], [148]. Impingement jet cooling uses a single jet or a set of jets
of fluids with a high velocity and directs them onto the surface of the bottom side of the
DBC where the semiconductor is located. It promises local, but very high heat transfer
coefficients with a low pumping power of only up to 100 mW per device. In contrast to
more conventional techniques with baseplates, heat-spreading is not contributing to the
overall heat transfer. Instead, the impingement jet directly removes the heat from its
source and is thus called hot spot removal [73].
Micro-channel cooling structures for heatsinks have been researched since decades [55],
[87] and provide excellent heat transfer coefficients of up to 100 W/cm2 K. Micro-channels
integrated into the DBC or the baseplate for the cooling of power electronics have been re-
searched and various techniques for the integration of micro-channels have been deployed.
The narrow and numerous channels require complex manufacturing processes and increase
costs. Laser-ablated micro-channels, channels fabricated with diamond bladed wafer dic-
ing or micro-milling have already been evaluated in literature [70], [150], [153]. Very
low channel widths in the range of 100 µm and more than one hundred parallel channels
are used for die with an edge length of 1 cm [135], [153], [199]. A large number of nar-
row channels optimizes the surface area between the fluids and the copper walls of the
micro-channels. While rectangular shapes are commonly found due to their easy manu-
facturability, circular shapes are also investigated [34]. The micro-channels are directly
fabricated into the bottom copper layer of DBCs, which provides the least amount of ma-
terials within the cooling path. Even experiments for integrating the micro-channels into
the ceramic layer of the substrates are conducted [203]. The achieved thermal resistances
are in the range of 0.10 K/W for Si devices. In [100], a thermal resistance of as low as
0.35 K/W is achieved with a micro-channel cooling structure utilized for the same SiC
devices that are utilized in this thesis [192]. The exact design of the cooling structure
is not presented. However, the results are obtained for two die in parallel, essentially
doubling the thermal resistance per device. Halving the die-size essentially doubles the
thermal resistance due to the reduced heat-conducting area.
Double-sided cooling techniques have also been presented and are commonly used in
combination with micro-channels [135], [199], [202] or pin fins [99], [196] or other structures
[194]. Double-sided cooling techniques do not only utilize the bottom side of the die for
cooling, but also attach a cooler on the top side of the die. Theoretically, this halves the
thermal resistance of any cooling structure for power electronic devices. In practice, the
top side of semiconductor die is not fully metallized and additionally contains the gate
pad and a passivation area, decreasing the available cooling surface on the top. Thus,
halving the thermal resistance is usually not achieved. The manufacturing of double-sided
cooling structure for power electronic modules is complex and requires flip-chip bonding
capabilities because the bottom and the top side must be soldered or sintered. It is
incompatible with standard wire-bonding techniques.
13
Due to the advancement in additive manufacturing, cooling structures can be fabricated

with the 3D-printing process with different materials, e.g. nickel, stainless steel, and
others. Such structures have been demonstrated in combination with discrete devices and
enable small and efficient cooling structures for high-power density converters [186], [188],
[190]. The cooling structures are attached via an insulating TIM material to the discrete
devices. Such structures have not been applied to power electronic modules based on
DBC substrates that provides insulation yet.
Another concept based on 3D-printed cooling structures are pins that are directly man-
ufactured onto the semiconductor die [26], [27]. Conventional bonding techniques like
bond wires, soldering or sintering are not required. The pins are directly jointed with
the chip metallization during the 3D-printing process that helps to decrease the thermo-
mechanical stress in semiconductor. However, manufacturing of such structures is complex
as the device must not be damaged during the processing. Because the fins are in direct
contact with the semiconductor with no insulation in between, the fluid coolant must be
electrically insulating, for example oil.
Some of the presented integrated cooling concepts with higher heat transfer coefficients
have been presented decades ago. Naturally, these have not been investigated for the
application to SiC devices, but now become essential for SiC devices with high current
densities. Most of the research activities and proposals of cooling structure work to
eliminate the TIM and thus lower the thermal resistance from the junction to the fluid.
14
3 Micro-Channel Cooling Structures for SiC
MOSFETs
The cooling of power electronic devices is a key element for high power density power
electronic systems [88]. Ultimately, the maximum power rating of devices is determined
by the achievable cooling performance defined by the thermal resistance. The thermal
resistance limits the amount of power loss that can be dissipated while keeping the devices
within their safe operating area. Reducing the thermal resistance of power modules allows
to increase the switching frequency as more switching losses can be dissipated or a higher
current density of the devices can be achieved. As a result, a low thermal resistance
maximizes device utilization. However, this should not be achieved by large and expensive
cooling structures that diminishes any benefits of higher power densities via increased
switching frequencies on a system level, but with a proper designed power module.
SiC MOSFETs exhibit an increased current density and a smaller die size compared to
Si IGBTs for the same voltage and current rating. For example, a SiC MOSFET with
a die size of 0.26 cm2 [192] features the same voltage and current rating as a Si IGBT
with a die size of 0.7 cm2 [66]. This equals a factor of almost three. Hence, there is a
disadvantage for the SiC devices as the cooling performance is highly dependent on the
device area [140] because the rated junction temperatures of commercially available SiC
devices are similar to those of Si devices. While SiC devices can potentially operate at
higher junction temperatures than Si devices, reliability issues such as threshold voltage
instabilities limit the maximum junction temperature [82], [102].
Consequently, designing cooling systems is a more challenging task for SiC devices when
aiming for the same thermal resistance as their Si counterparts. New cooling techniques
and structures are required that achieve a higher heat-transfer coefficient compared to
state-of-the-art technologies while keeping the overall size of the power converter systems
constant [140].
Based on the literature review in Section 2.2, a micro-channel cooling structure is inves-
tigated for SiC devices in this chapter. Key criteria are the achievable heat transfer and
the required pumping power. The power density and manufacturability of the structures
are also of great importance. Micro-channel cooling solutions presented in literature re-
quire highly accurate manufacturing as several hundreds of narrow micro-channels are
utilized, which are manufactured via laser-ablation or micro-milling techniques among
others. Compared to these structures, coarser structures are investigated in this chap-
ter with channels that are milled into the baseplate of the power modules as shown by
15
3 Micro-Channel Cooling Structures for SiC MOSFETs
die-attach
layer die micro-channel
DBC
solder
baseplate
Figure 3.1: Micro-channel cooler milled into baseplate.
Figure 3.1. The spacing of the channels is in the range of several hundred microme-
ter. Coarser structures are easier to manufacture and allow rapid-prototyping of highly-
integrated power modules. Furthermore, coarser structures lower the requirements on
the cleanness and the maximum particle size in the fluid, i.e., according to [69], which
is of great importance for cost-sensitive automotive applications. Whether a sufficient
performance can be achievable with a coarser, simpler and cheaper cooling structure has
yet to be demonstrated.
To determine the feasibility of micro-channel structures for SiC devices, a CFD simulation
is carried out. Based on this simulation, material variations and the influence of several
geometry parameters on the steady-state thermal resistance are analyzed. For verification
of the simulation results, a prototype is constructed and analyzed in detail. The transient
response of the presented structures is investigated and its implications on the lifetime
are discussed. The chapter closes with a summary of the thermal aspects for a power
module designed for SiC devices.
3.1 Simulation of Micro-Channel Structure
The cooling performance is investigated for SiC MOSFET bare die manufactured by
Wolfspeed with a dc current rating of 98 A and a voltage rating of 1200 V [192]. The die
are 4.04 mm times 6.44 mm in size, which results in a die area of 26.01 mm2 . The die
thickness is 180 µm. An initial estimation of the power loss of the SiC devices, which are
going to be operated in high-frequency power electronic converters, is used as a starting
point for the design of the cooling structure. With a targeted switching frequency in the
range of 300 kHz and a total switching energy of approximately 1 mJ [36], [192], a single
device exhibits a power loss of 300 W. This calculates to a heat flux density of 1153 W/cm2
with the aforementioned die size. This does not include additional conduction losses.
Because most semiconductor devices are rated for a maximum junction temperature of
150 °C or 175 °C, cooling becomes difficult at these very high heat flux densities, even for
fluid coolant systems with low inlet temperatures of 25 °C or 55 °C.
16
A CFD simulation is built with ANSYS Fluent to examine the feasibility of a milled micro-
channel structure. Several assumptions and simplifications are made for the simulation.
For example, the surface roughness of the structures is not taken into account as well
as the inlet and outlet connections. Furthermore, the simulation does not incorporate
the conductive and convective heat transfer on the top side of the die, e.g. through wire
bonds. Symmetry boundary conditions are utilized to reduce the model size.
The geometry constraints of the simulation are given in Table 3.1. They are chosen such
that manufacturing is easily feasible with conventional milling and soldering processes,
for example the channel width and the number of channels. The thermal properties of the
materials used for the simulations shown in the following sections are given in Table A.1.
Conventional solder with a thermal conductivity of 50.9 W/mK and a thickness of 50 µm

is chosen to simulate the die-attach material. The ceramic of the DBC is a standard
Al2 O3 ceramic with a thermal conductivity of 24 W/mK and a thickness of 380 µm for the
ceramic and 300 µm for the copper. The baseplate consists of copper and is attached to
the DBC via a solder layer. The cooling structure consists of nine channels with a width
of 500 µm each. The width of the copper fins is the remaining copper width when the
channels are milled into the structure, which is 625 µm in this case. The height of the
channel can be chosen independently of their width and is chosen to 500 µm. In fact, the
effective channel height is larger due to the height of the solder layer that bonds the DBC
and the baseplate. Its thickness is set to 50 µm. A copper border of 2 mm is added to
both sides of the channel structure to ensure a large soldering surface for attaching the
baseplate to the DBC. To achieve a high power density on a system level, a minimum
volume of the cooling structure must be ensured. For this reason, the outer dimensions
are fixed to a length of 15 mm and a width of 13.5 mm. This corresponds to around 5 mm
Table 3.1: Geometry parameters for simulation

parameter value
DBC length 15 mm
DBC width 13.5 mm
DBC ceramic thickness 380 µm
DBC copper thickness 300 µm
channel copper border 2 mm
top side copper
2 mm
excess length
baseplate thickness 3 mm
channel width 500 µm
fin width 625 µm
solder thickness 50 µm
17
Temperature
in °C
250
225
200
175
150
125
100
75
50
25
Figure 3.2: Temperature rendering of the cooling structure.
overhang of the cooling structure to each side of the semiconductor die. The 5 mm are
chosen as a trade-off between a sufficient heat-spreading and being able to effectively cool
multiple SiC devices in close proximity to each other with the cooling structure.
The power loss of the device is 300 W modeled as a loss density within the volume of the
die. The simulated coolant fluid is a mixture of 60 % water and 40 % glycol. The inlet
temperature is 25 °C and the volume flow is 0.2 l/min. The resulting pressure drop of the
cooling structure is 28 mbar. The required pumping power Ppump is 4.7 mW according
to:
Ppump = Q · ∆p (3.1)
Q is the volumetric flow rate through the cooling structure and ∆p is the pressure drop
across the cooling structure.
The simulation assumes a laminar fluid flow. The dimensionless Reynolds number deter-
mines whether the fluid flow is of laminar or turbulent nature. The Reynolds number Re
is given as
18
v · Dh ρ · v · Dh
Re = = (3.2)
ν µf
µf
with ν =
ρ
for a fluid flow in a circular tube. v is the mean velocity of the fluid. Dh is the inner,
hydraulic diameter of the tube. ν is the kinematic viscosity, µf is the dynamic viscosity
and ρ is the density of the fluid.
In [87], the fluid flow analysis of micro-channel heat sinks is outlined. The critical Reynolds
number Recrit at which the flow starts to become turbulent is:
v · Dh
≤ 2300 = Recrit (3.3)
ν
Since the micro-channel structure is not of round shape and can be of different width and
height, an equivalent hydraulic diameter Dh is calculated in [87]:
2·W
Dh = W
(3.4)
N + Γ · (N − 1) + H
W is the width of the whole micro-channel structure, e.g. the inlet to the structure. N is
the number of channels within the structure. Γ is the ratio of the fin width to the channel
width and H is the height of the channels.
The simulated mean velocity of the fluid in the channel is v = 1.33 m/s. The hydraulic
diameter Dh , which is calculated according to Equation (3.4), is 537.3 µm. The Reynolds
number calculates to Re = 371.6, which is far below the critical Reynolds number from
Equation (3.3).
A volume rendering of the temperature distribution of the simulation is given in Figure 3.2.
Figure 3.3 shows a contour plot of the cross section of the cooling structure. The simulated
average junction temperature ϑj is 267.7 °C. This corresponds to a thermal resistance Rth
of 0.81 K/W according to:
ϑj − ϑref
Rth = (3.5)
Ploss
ϑj is the average junction temperature of the semiconductor die and ϑref the reference
19
Temperature
in °C
250
225
200
175
150
125
100
75
50
25
Figure 3.3: Cross-sectional contour plot of temperature.
temperature, i.e., the inlet temperature of the fluid. Ploss is the power loss in the die
that is dissipated via the cooling structure. The baseplate has an average temperature of
103.9 °C. On the top side of the DBC, only minimal heat-spreading occurs. The copper
on the top side of the DBC exhibits a large temperature difference of 80 °C. The heat
conduction is primarily occurring directly beneath the semiconductor die towards the
micro-channel structure.
Compared to values presented in literature, the simulated thermal resistance of 0.81 K/W
is rather high. For example, a thermal resistance of less than 0.1 K/W has been achieved
with Si IGBTs and diodes used in a micro-channel setup [153]. However, an AMB Si3 N4
substrate with higher thermal conductivity and fine-grained micro-channels with a width
of 100 µm have been used. In addition, SiC devices feature a smaller die size compared
to Si IGBTs, which in turn increases the thermal resistance. Although the die size of the
IGBT is not explicitly mentioned in [153], it can be derived from the values given for the
thermal resistivity and thermal resistance, resulting in a die area Adie of approximately
200 mm2 , which is a factor of approximately eight larger. The cooling performance of
the presented solution becomes evident when taking the heat-transfer coefficient h into
account. The surface-related heat-transfer coefficient h, referred to the semiconductor die
area Adie and a temperature difference (ϑj - ϑref ), is calculated as:
Ploss
h= (3.6)
Adie · (ϑj − ϑref )
The heat-transfer coefficient h of the simulated setup is 4.74 W/cm2 K. The thermal resis-
20
tivity, which is the inverse of the heat transfer coefficient, is 0.21 K/cm2 W. This is 23 %
higher than the results presented in literature in the range of 0.17 K cm2/W [70], [153]. The
target power loss of 300 W cannot be dissipated without exceeding the maximum junc-
tion temperature of 175 °C of the SiC device by 92.7 °C. Although the performance of
the micro-channel structure is comparable to values in literature, the thermal resistance
is higher due to the small die area SiC devices.
3.1.1 Investigation of Different Materials
To decrease the thermal resistance of the overall cooling system, materials with a higher
thermal conductivity must be utilized for the small SiC devices. The investigated materi-
als include an AlN ceramic and silver-sintering for die-attach instead of an Al2 O3 ceramic
and conventional die-attach soldering. The standard thickness of the AlN ceramics is
630 µm. Furthermore, an Si3 N4 AMB substrate is examined that has a lower thermal
conductivity than AlN, but is available with a smaller thickness due to its superior me-
chanical properties [29]. Similar to the Al2 O3 DBCs, a thickness of 380 µm is available
for the Si3 N4 AMB. Because silver-sintering layers can be manufactured thinner in com-
parison to solder layers [91], the die-attach layer thickness is only 25 µm. The simulation
results for the different material combinations are shown in Table 3.2.
For a power loss of 300 W, all simulated materials still exceed the rated junction temper-
ature of 175 °C [192] at a volume flow of 0.2 l/min. In case of AlN ceramics, the junction
temperature can be reduced by up to 63 °C, which makes them the most promising choice
for SiC MOSFETs. It becomes evident that AlN ceramics or materials with a compara-
ble thermal conductivity are required for SiC devices with very high heat flux densities.
Available power modules with SiC MOSFETs also utilize AlN substrates [193]. Although
the ceramic layer of AlN substrates usually has a higher thickness compared to Al2 O3
DBCs, the manifold increased thermal conductivity of 170 W/mK yields a considerably
Table 3.2: Simulation results for different material combinations
junction temperature thermal resistance

material combination
in °C in K/W
Al2 O3 & soldering 267.7 0.81
AlN & soldering 204.9 0.60
Si3 N4 & soldering 212.7 0.62
Al2 O3 & sintering 256.7 0.77
AlN & sintering 194.2 0.56
Si3 N4 & sintering 201.8 0.59
21
Junction temperature in °C
Length y direction in mm
3
copper of DBC 197
2.5
196
2
die
y 195
1.5
194
x excess length 1
1 1.5 2 2.5 3
Length x direction in mm
(a) DBC structure top view (b) Simulation results of the parameter sweep
Figure 3.4: View of the geometry parameters changed during the parameter sweep and
the simulation results.
lower temperature. The simulation with Si3 N4 AMB results in an about 7 °C higher junc-
tion temperature compared to the AlN DBC . The lower thermal conductivity of 90 W K/m
versus 170 W K/m is almost mitigated by the reduced thickness.
Using sintered silver as a die-attach material instead of solder further decreases the junc-
tion temperature by about 11 °C. Sintered silver has a high thermal conductivity of more
than 250 W/mK compared to solder with approximately 50 W/mK. Furthermore, the
reduced thickness of the sintered layer decreases the thermal resistance. However, the
influence of the die-attach material on the junction temperature and the thermal resis-
tance is lower as the thin die-attach layer does not significantly contribute to the overall
thermal resistance compared to the ceramics.
3.1.2 Geometry Analysis
In addition to the different materials, several geometry parameters are investigated re-
garding the cooling performance. The analysis is based on the same parameters as before
including an AlN ceramic and silver-sintering as a die-attach material for best thermal
performance. The ANSYS Workbench design-of-experiments is used to create a set of
simulated geometry variations and interpolates values between several simulated design
points.
The effects of the excess length and width of the copper surrounding the MOSFET on the
top side, as shown in Figure 3.4a, are investigated. The simulation results in Figure 3.4b
indicate that there is only a negligible impact on the junction temperature. Due to the
high thermal conductivity of the AlN ceramic, the heat spreading on the top side of the
22
die copper
thickness
solder
baseplate thickness thickness
Figure 3.5: Investigated parameters.
DBC is limited. The heat is conducted straight to the micro-channel structure on the
bottom side of the DBC. A junction temperature difference of only 3 °C is observed when
the copper excess length is increased from 1 mm to 3 mm.
The influence on the thermal resistance of several other parameters is investigated. Fig-
ure 3.5 shows the according parameters, such as the thickness of the copper of the DBC.
Different copper thicknesses for DBCs are available from manufacturers [28], [29]. The
available thicknesses of the bonded copper, which are assumed to be the same on both
sides of the DBC, are simulated and the results are shown in Table 3.3. Similar to the
excess width and length of the copper, the copper thickness has a limited influence on
the junction temperature. Increasing the thickness from 200 µm to 400 µm decreases the
junction temperature by 4 °C.
The thickness of the solder layer between the baseplate and the DBC is investigated as
depicted in Figure 3.5. Simulations are carried out for a solder layer thickness between
50 µm and 250 µm. The simulation results are shown in Figure 3.6a. The solder layer
thickness has a more significant influence on the cooling performance. The observed
variation of the junction temperature is about 15 °C. On the one hand, increasing the
thickness of the solder layer with its lower thermal conductivity increases the overall
thermal resistance. On the other hand, it also has an influence on the effective height of
the channel and, thus, affects the fluid flow in the channels. Figure 3.6a also shows the
simulated pressure drop of the structure for different thicknesses of the solder layer. The
pressure drop decreases with an increased layer thickness assuming a constant volume
Table 3.3: Simulation results for different DBC copper thicknesses
copper thickness junction temperature thermal resistance

µm in °C in K/W
200 197.1 0.57
250 195.5 0.57
300 194.4 0.56
400 193.2 0.56
23
210 30 200
Pressure drop in mbar
205
25 198
200
20 196
195
190 15 194
50 100 150 200 250 1 2 3 4 5
Thickness of baseplate solder in µm Thickness of baseplate in mm
(a) Solder layer thickness (b) baseplate thickness
Figure 3.6: Results of parameter sweep.
die
channel
height channel
number of
width channels
Figure 3.7: Investigated channel parameters.
flow. Reducing the pressure drop at a constant volume flow also reduces the required
pumping power, in this case by about 40 %.
The thickness of the baseplate depicted in Figure 3.5 has a small influence on the cooling
performance. It slightly contributes to the heat spreading within the baseplate and, thus,
increases the heat exchange of the micro-channel structure to the coolant. The relationship
between the simulated junction temperature and the baseplate thickness in Figure 3.6b
shows an exponential decline. With a baseplate thickness of more than 3 mm, its influence
decreases considerably. The maximum junction temperature reduction is 5 °C.
Finally, the geometry of the channel is investigated based on the channel width and the
channel height as depicted in Figure 3.7. The investigated parameter ranges are chosen
with regard to the boundaries imposed by the manufacturing process. For the milling
process, the minimum channel width is determined by the size of the milling head. The
width of the channels is between 400 µm and 800 µm as standard milling heads are available
in this range. A minimum copper width of the fins is necessary for mechanical stability.
At 800 µm channel width, the width of the copper fin is 287.5 µm. A variation between
400 µm and 800 µm is investigated for the channel height. The results of the simulation
are given in Figure 3.8.
24
Junction temperature in °C Pumping power in W

800 220 800 0.02
Channel height in µm
Channel height in µm
750 750
700 700
210 0.015
650 650
600 600
550 200 550 0.01
500 500
450 450 0.005
190
400 400
400 450 500 550 600 650 700 750 800 400 450 500 550 600 650 700 750 800
Channel width in µm Channel width in µm
(a) Junction temperature (b) Pumping power
Figure 3.8: Channel width and height simulation results.
There is a significant influence on the junction temperature when decreasing the channel
width from 800 µm to 400 µm. It changes from more than 220 °C to less than 190 °C. The
lower temperature requires a pumping power that is about ten times higher. Ultimately, a
compromise must be found between the required pumping power and thermal resistance.
Changing the channel width has a greater influence on the cooling performance than the
channel height. The junction temperature is lower for the minimum channel width than
for the minimum channel height, which are both 400 µm. The solder layer between the
baseplate and the DBC also influences the effective channel height.
Another important aspect of the micro-channel cooling structure is the number of chan-
nels. An increased number of channels is desirable as this maximizes the surface area to
the fluid. The number of channels is limited by conventional milling processes and by the
minimum width of the channels and the copper fins that must be sustained. Simulation
results for 10, 11 and 12 channels are given in Table 3.4. The results are given for the
same volume flow and the same pressure drop as the structure with 9 channels with a
junction temperature 194.4 °C and a thermal resistance of 0.56 K/W.
Table 3.4: Simulation with different number of channels
number of channels 10 11 12
junction temperature in °C 190.2 190.1 183.9
constant volume flow
thermal resistance in K/W 0.55 0.55 0.53
junction temperature in °C 185.1 180.9 171.8
constant pressure drop
thermal resistance in K/W 0.53 0.52 0.49
25
The results show a decrease of the thermal resistance from 0.56 K/W with 9 channels to
about 0.53 K/W with 12 channels at the same constant volume flow, which is a reduction
of 6 %. It is further reduced to 0.49 K/W or by 13 % with the pressure drop kept at the
same level, e.g. the total volume flow is scaled proportional to the number of channels.
3.2 Experimental Verification
In the previous sections, it has been shown that using a AlN ceramic with silver-sintered
SiC MOSFETs yields the lowest thermal resistance. Furthermore, the influence of several
geometry parameters on the thermal resistance has been examined with CFD simula-
tions.
To validate the simulation results, a prototype is manufactured that consists of a single

SiC MOSFET that is silver-sintered to an AlN DBC. Nine channels have been chosen such
that the remaining copper fins are at least 500 µm wide for mechanical stability and simple
manufacturing. The channel width of the milled micro-channels and the effective channel
height has been selected as 600 µm to ensure a low thermal resistance while reducing the
susceptibility to particles in the cooling liquid and the required pumping power.
Dedicated areas for the source contact, the gate and Kelvin-source contact are added as
shown by Figure 3.9a. The thickness of the baseplate is 3 mm according to the simulation
results. The MOSFET die are nickel-plated to allow soldering at the top side of the die.
The top-side connections are established using copper bonds. The inlet and outlet of
the cooling structure are drilled into the back side of the baseplate. For better corrosion
resistance, the copper surfaces that are in contact with the fluid coolant should be nickel-
plated. This is not carried out for the prototype as it is does not require long-term
stability.
The etched DBC with the silver-sintered SiC die is depicted in Figure 3.9a. The milled
baseplate is depicted in Figure 3.9b and the manufactured prototype is shown in Fig-
ure 3.9c.
3.2.1 Detailed Simulation of the Prototype
With regard to the simulation results presented in the last section, the thermal parameters
shown in Table 3.5 can be extracted for the prototype.
To provide an in-depth understanding of the thermal behavior of the prototype, the per-
formance at higher volume flows as well as the transient thermal impedance is simulated
in the following. The thermal resistance is investigated at five exemplary volume flows in
26
(a) DBC with MOSFET (b) Milled baseplate (c) Assembled prototype
Figure 3.9: Milled prototype.
the range from 0.23 l/min to 0.84 l/min. The simulation results of the investigated volume
flows and the resulting thermal resistance are given in Table 3.6. The increase of the
volume flow to 0.84 l/min is able to reduce the thermal resistance down to 0.41 K/W, which
is a reduction of 26 %. The required pumping power at this operating point is increased
by a factor of more than 20. The junction temperature is 149.3 °C for this simulation and
below the rated junction temperature of 175 °C.
Figure 3.10 shows a contour plot of the cross section located at the center of the micro-
channel structure perpendicular to the fluid flow direction at two different simulated
volume flows. The heat-spreading on top of the DBC is limited as outlined before. There
is a steep temperature gradient near the semiconductor die. The temperature of baseplate
is quite homogeneous because of the high thermal conductivity of the copper and the
Table 3.5: Simulation results for the prototype.
parameter measured value

pressure drop 0.019 bar
volume flow 0.2 l/min
steady-state
198.9 °C
temperature
pumping power 0.003 W
thermal
0.58 K/W
resistance
heat-transfer
6.63 W/cm2 K
coefficient
27
Temperature Temperature
in °C in °C
175 175
150 150
125 125
100 100
75 75
50 50
25 25
(a) 0.52 l/min (b) 0.84 l/min
Figure 3.10: Contour plot on cross section with different volume flow.
resulting heat-spreading. The average baseplate temperature is 90.0 °C at a volume flow

of 0.52 l/min and 79.2 °C at 0.84 l/min. Due to the small surface area of the micro-channels,
the heat-exchange between the baseplate and the fluid is limited and benefits from an
increased fluid velocity.
The theoretical minimal thermal resistance from the semiconductor die through the DBC
is computed as 0.22 K/W for an assumed ideal heat-exchanger attached on the bottom
side of the AlN DBC. This value can be subtracted from the total thermal resistance
of 0.41 K/W at 0.84 l/min to obtain a simplified, remaining thermal resistance of the sole
micro-channel structure. Consequently, the remaining thermal resistance of 0.19 K/W is
related to the microchannel cooling structure. Hence, the thermal resistance of the whole
cooling structure is approximately divided into two equal parts: The thermal resistance of
Table 3.6: Simulation results of milled cooling structure.
parameter measured values

volume flow 0.23 l/min 0.4 l/min 0.52 l/min 0.67 l/min 0.84 l/min
pressure drop 0.023 bar 0.048 bar 0.068 bar 0.095 bar 0.129 bar
steady-state
191.7 °C 168.7 °C 160.6 °C 154.1 °C 149.3 °C
temperature
pumping power 0.004 W 0.02 W 0.03 W 0.06 W 0.09 W
thermal
0.56 K/W 0.48 K/W 0.45 K/W 0.43 K/W 0.41 K/W
resistance
heat-transfer
6.92 W/cm2 K 8.02 W/cm2 K 8.51 W/cm2 K 8.93 W/cm2 K 9.28 W/cm2 K
coefficient
28
100
Thermal impedance in K/W

200
0.23 l/min
0.52 l/min
150 0.84 l/min
10-1
100
10-2
50 0.23 l/min
0.52 l/min
0.84 l/min
0 10-3
0 1 2 3 4 5 10-3 10-2 10-1 100
Time in s Time in s
(a) transient response (b) impedance
Figure 3.11: Transient simulation.
the DBC and the thermal resistance from the micro-channels to the fluid. This highlights
future optimization potential for the cooling structure to lower the thermal resistance. By
utilizing more sophisticated cooling structures with better heat transfer coefficients, such
as more complex, 3D-printed structures with a high surface roughness, a lower overall
thermal resistance can be achieved for small SiC devices.
Steady-state simulation have been carried out for the cooling structure as the thermal
resistance determines the maximum power loss that can be dissipated. However, the
transient performance is also an important criterion of a cooling structure as it determines
the thermal cycles under transient load conditions. To investigate the transient behavior, a
power loss change from 300 W to 0 W at three different volume flows of 0.23 l/min, 0.52 l/min
and 0.84 l/min is simulated using ANSYS Fluent. The simulated temperatures and the
calculated thermal impedances are given in Figure 3.11. A very fast transient response is
observable. Especially at the highest volume flow of 0.84 l/min, the junction temperature
depicted in Figure 3.11a drops fast to the fluid inlet temperature within 2 s.
Figure 3.11b verifies that the steady-state temperature is reached after approximately
2 s and shows that the cooling structure only has a low thermal capacity. Aiming at a
low thermal resistance of the power module, many material layers are removed and the
coolant is moved as close as possible to the heat source. As a result, many materials are
eliminated that contribute to the overall thermal capacity of the cooling structure. The
removal of the large and thick baseplate of power modules that is attached to an external
heatsink decreases the thermal capacity considerably compared to conventional setups.
Although the small copper baseplate with the integrated micro-channels remains in the
presented design, its dimensions are small and, hence, also its thermal capacity. The
remaining structure consists of thin layers, less material and a coolant, which is located
as close as possible to the heat source. On the one hand, the low thermal capacity can
be used to implement a highly dynamic and optimal temperature control based on the
29
1450 1450
1400 1400
Voltage in mV
Voltage in mV
1350 1350
1300 1300
1250 1250
1200 1200
1150 1150
1100 1100
1050 1050
20 40 60 80 100 120 140 0 1 2 3 4 5
Temperature in °C Time in s
(a) calibration of forward voltage (b) impedance measurement
Figure 3.12: Exemplary calibration and impedance measurement.
load profile [75]. On the other hand, modules with a low thermal capacity are susceptible
to increased thermal cycling. The low thermal capacity does not dampen thermal cycles
when the load current and, thus, the losses vary during operation of the power module.
This makes it a critical issue from a lifetime and application perspective. The power
module degrades faster due to the high number of thermal cycles it experiences due to
the absence of thermal capacity.
3.2.2 Thermal Impedance Measurements
For the experimental verification of the thermal impedance, measurements are conducted
on a thermal impedance test bench as described in Appendix A.1.2. The forward voltage
drop Uf of the body diode of the MOSFET is utilized as a temperature sensitive electrical
parameter (TSEP) that can be used as a temperature sensor for the virtual junction tem-
perature (VJT) [6]. Uf exhibits a monotonously falling slope over temperature. The gate
contact of the MOSFET is short-circuited to the source contact for the measurement to
turn-off the channel of MOSFET, which can also conduct the current in reverse direction.
The measured calibration curve of Uf over temperature with a constant sensing current
of 100 mA is shown in Figure 3.12a. The Uf curve is not completely linear in contrast to
previous measurements on Si IGBTs and diodes with a pn-junction. This is likely due to
the MOSFET channel not being entirely closed at a gate-source voltage of 0 V. Since the
curve still has a monotonously falling slope, it can be used for the measurements without
any restrictions.
The forward voltage drop Uf of the body diode and a dc load current generate the power
loss in the device for the thermal impedance test. For a dc load current of 70 A yielding
a total loss of 291.2 W, the measured voltage curve of the impedance measurement is
30
Figure 3.13: Setup of the thermal impedance measurements.
100
160
140
120
100 10-1
80
60 10-2
40
20
0 10-3
0 1 2 3 4 5 10-3 10-2 10-1 100 101
Time in s Time in s
(a) transient response (b) calculated thermal impedance
Figure 3.14: Calculated temperature and thermal impedance.
shown Figure 3.14. The fluid inlet temperature is 20.2 °C. The fluid is a mixture of 60 %
water and 40 % glycol according to the simulations. The pressure drop across the whole
structure from the outer T-connectors as depicted in Figure 3.13 is 1.08 bar with a volume
flow of 0.84 l/min. The pumping power is 1.5 W.
The junction temperature is calculated from the voltage curve in Figure 3.12b via the
previously recorded calibration curve shown in Figure 3.12a. The junction temperature
and thermal impedance are shown in Figure 3.14. The temperature at the time instant
0 s equals the steady-state temperature for the power loss and can be used to calculate
the static thermal resistance of 0.41 K/W according to Equation (3.5).
31
100

180
0.23 l/min
160
0.52 l/min
140 0.84 l/min
120 10-1
100
80
60 10-2
0.23 l/min
40 0.52 l/min
20 0.84 l/min
0 10-3
0 2 4 6 8 10 10-3 10-2 10-1 100 101
Time in s Time in s
(a) transient response (b) calculated thermal impedance
Figure 3.15: Measurements at different volume flows.
Measurements at different volume flows of 0.23 l/min, 0.52 l/min and 0.84 l/min are given in
Figure 3.15. The dc load current is 60 A for this case resulting in a power loss of approxi-
mately 240 W. The inlet temperature is measured to approximately to 20.3 °C. Due to the
different volume flows, different steady-state temperatures of 115 °C, 123.6 °C and 145.2 °C
are obtained. The thermal resistance is 0.39 K/W, 0.43 K/W and 0.52 K/W. Additionally, a
different transient behavior is visible in Figure 3.15a. Whereas the measurement with high
volume flow reaches the steady state after 2 s to 3 s, the measurement at a low volume
flow does not reach the fluid inlet temperature of 20.7 °C after 10 s.
The dominant effects of the micro-channel cooler can be split into two thermal resistance
and capacity pairs as a first approximation. The steep decrease of the temperature in the
time span from 0 s to 1 s can be attributed to the die and the copper on the top of the
DBC. The AlN ceramic layer with a comparably low thermal conductivity connects the
top side to the bottom side of the cooling structure and basically separates the two parts.
The slower decrease after 1 s is caused by the components on the bottom side of DBC,
e.g. the baseplate-integrated cooling structure. With a lower volume flow, a lower heat
transfer coefficient between the baseplate and the fluid is observed.
Further results of the thermal impedance measurements at the different volume flows
are summarized in Table 3.7. The structure has also been measured with pure water
as coolant. The results are given in Table A.2 showing a lower thermal resistance of
about 15 %. The given values are valid for the cooling structure of a single MOSFET
die only. Since the micro-channel structure is required for each individual semiconductor
within the package, the pumping power scales approximately linearly with the number of
semiconductor die.
32
For a volume flow of 0.23 l/min and a corresponding pressure drop of 0.11 bar, the heat-
transfer coefficient calculated according to Equation (3.6) is 7.80 W/cm2 K. The heat-
transfer coefficient at a volume flow of 0.52 l/min and a pressure drop of 0.52 bar increases
to 8.96 W/cm2 K while the pumping power is calculated to 0.45 W, which is ten times the
pumping power compared to the measurement point at 0.23 l/min. The thermal resistance
drops to 0.43 K/W or by 17 %. Increasing the volume flow to 0.84 l/min and, thereby, dou-
bling the pressure drop to more than 1 bar increases the heat-transfer coefficient by 10 %
and reaches 9.83 W/cm2 K. The pumping power increases by a factor of three with 1.46 W.
Calculating the junction temperature with an inlet temperature of 25 °C and a power

loss of 300 W, the result is 160 °C with the thermal resistance of 0.45 K/W at a volume
flow of 0.40 l/min. This is below the maximum rated operating junction temperature of
175 °C. Hence, the goal of cooling 300 W of power loss from the small SiC MOSFET is
achieved at this measurement point. At the maximum measured volume flow of 0.84 l/min,
the calculated junction temperature is 142 °C. Consequently, even a higher power loss can
be dissipated or a higher fluid inlet temperature, i.e., 55 °C can be used.
As a compromise between the pumping power and a good heat-transfer coefficient, a

volume flow in the range of 0.40 l/min to 0.50 l/min with corresponding pressure drops of
0.3 bar to 0.5 bar is favorable. At this point, the thermal resistance is low enough to
dissipate successfully the target power loss of 300 W from the semiconductor. Ultimately,
a trade-off regarding volume and cost has to be found between the required pumping
power and the semiconductor die area that is required to dissipate the power loss.
Table 3.7: Measurement results of milled cooling structure.

volume flow 0.23 l/min 0.40 l/min 0.52 l/min 0.67 l/min 0.84 l/min
inlet temperature 20.6 °C 20.4 °C 20.3 °C 20.2 °C 20.3 °C
dc current 60 A 60 A 60 A 60 A 60 A
power loss 239.0 W 241.8 W 240.8 W 245.5 W 242.1 W
steady-state
145.2 °C 129.5 °C 123.6 °C 119.2 °C 115 °C
temperature
pumping power 0.044 W 0.21 W 0.45 W 0.84 W 1.46 W
thermal
0.52 K/W 0.45 K/W 0.43 K/W 0.40 K/W 0.39 K/W
resistance
heat-transfer
coefficient
33
The measurement results from Table 3.7 are in good agreement with the simulation results
in Table 3.6. The simulated thermal resistance at the same volume flow, for example at
0.4 l/min, is about 0.03 K/W or 6.6 % higher than the measured thermal resistance. This
can be explained by the aforementioned simplifications of the simulations. For example,
the top-side connection of the MOSFET is neglected in the simulation. Additionally, the
inlet and outlet of the cooling structure are not modeled in the simulation, which increase
the heat transfer of the experimental structure due to the larger surface area to the fluid
coolant.
The measured pressure drop is considerably higher than the simulated one at the same
volume flow, for example 0.31 bar versus 0.048 bar at 0.4 l/min. The pressure drop of the
cooling structure is not directly measured, but includes the inlet and outlet as depicted in
Figure 3.13 including tubes and connectors. Especially the connectors, which are screwed
into the inlet and outlet of the baseplate significantly contributes to the pressure drop due
to their angular shape. Hence, the measured pressure drop is higher than the simulated
one by a factor of approximately four at the lowest volume flow and a factor of ten at the
highest volume flow.
The transient behavior of the simulation in Figure 3.11 and the measurement in Fig-
ure 3.15 are also similar. The thermal time constants are within 1 s to 3 s depending on
the volume flow. However, the thermal impedance at high frequencies, i.e., between 10−4 s
and 10−3 s, differs between the simulation and the measurement by a factor of approxi-
mately two. This can be caused by the top-side connection of the soldered copper bonds
on top of the semiconductor die, which are not modeled in the simulation. The copper
and solder add thermal capacity directly to the die that lowers the thermal impedance at
high frequencies.
As an alternative to the milled micro-channels, micro-channels that are directly etched into
the DBC and a 3D-printed cooling structure have been investigated in Appendix A.1.4
and Appendix A.1.5. However, they result in a higher thermal resistance at the same
pumping power compared to the milled micro-channel structure.
Overall, the presented cooling structure enables a power loss dissipation of 300 W from a
die size of only 26 mm2 while featuring a low volume and weight. Therefore, it is perfectly
suited to effectively cool small SiC MOSFET and to build power electronic converters
with outstanding power densities.
34
3.3 Summary
3.3 Summary
In this chapter, an integrated cooling solution for small SiC MOSFETs based on micro-
channels has been investigated. The integrated cooling solution is directly milled into the
baseplate of the module reducing the overall volume of the setup. The influence of the
most significant design parameters has been analyzed based on CFD simulations. It has
been shown that AlN or comparable ceramics are the best choice for SiC modules be-
cause the high heat flux densities cannot be dissipated with conventional Al2 O3 ceramics.
Thermal resistances from die to fluid as low as 0.39 K/W have been demonstrated based on
a manufactured prototype using a water glycol mixture. The measurements are in good
agreement with the simulations and show a deviation below 10 % for the thermal resis-
tance. With pure water as coolant, a thermal resistance of 0.33 K/W has been achieved.
Compared to very fine micro-channels presented in literature, coarser structures with a
lower number of milled micro-channels have been investigated to reduce the requirements
of the maximum particle size in the fluid. The conducted simulations and measurements
demonstrate that they can still be used to effectively cool SiC MOSFET. The cooling
structure is able to dissipate a power loss of 300 W from SiC MOSFET with a die area
of 26 mm2 , which corresponds to heat flux densities greater than 1000 W/cm2 . A further
decrease of the thermal resistance in the range of a few percent is expected by further
optimizing the micro-channel geometry within the manufacturing constraints, for exam-
ple increasing the channel count that lowers the thermal resistance by 6 % without an
increase in required pumping power.
The outstanding thermal performance of the proposed cooling system comes with a re-
duced material usage. Consequently, the cooling structures exhibit an extremely fast
transient response, which is often neglected in recent literature. The structures reach
steady state after only 2 s. These fast response times provide opportunities for active
coolant flow control that enables a constant temperature control [75].
35
36
4 Thermal Buffers for Enhanced Lifetime
The lifetime of power electronic modules is crucial for the development of safe, reliable
and low-cost power electronic systems. The degradation of power electronic modules is
caused by thermomechanical stress induced by thermal cycles during operation [56]. It
causes degradation of bond wires or die-attach solder [122] that will ultimately result in
a failure of the power module and, thus, the power electronics system. In the previous
chapter, a highly-integrated and effective cooling solution for SiC MOSFETs has been
presented. However, due to the low amount of materials that adds thermal capacity to
the heat dissipation path, it exhibits a very fast transient thermal response as shown in
3.2.2. This amplifies degradation in power modules as varying power losses caused by the
mission profile are not damped by thermal capacity.
Typically, the lifetime of power electronic modules can be extended by oversizing the
power module and increasing the semiconductor die area to distribute the heat flux.
Thereby, thermal cycles and the thermomechanical strain for each individual device and
the package are reduced. However, oversizing is associated with higher cost and contra-
dicts a high power density. Another approach are thermal control algorithms that actively
control the device temperature to reduce thermal cycles [3], [124], [177]. However, most
active thermal control techniques work with additional losses in the device [176] or require
additional circuitry [79], [116], [173] sensors [78], [84], [191] and real-time computation
ability [174], [175] to extract and process temperature information from the power module
and, therefore, increase cost considerably.
To overcome these limitations, passive thermal buffers located within the package are
investigated as a method to extend the lifetime of power electronic modules. Reducing
the thermal impedance of power modules by novel packing technologies is certainly not a
new idea to increase the lifetime of power modules. However, using the space available on
the top surface of power device has not been systematically addressed in state-of-the-art
research and the influence of the thermal capacity over realistic mission profiles has not
been investigated. An example of a similar approach has been presented in [195], which
introduces a phase-changing material as a thermal buffer to enhance the thermal overload
capability of a power converter. It has also been investigated as a solution for maintaining
a safe junction temperature during error conditions [179]. Another example is presented
in [22] with a trenched copper plate on top of the chip of the power module in combination
with double-sided cooling. In the following, low-cost thermal buffers are investigated that
transiently store energy to mitigate the amplitude of thermal cycles that occur during
normal operation of an inverter in an electric vehicle.
37
thermal buffer
solder chip
DCB
heatsink heat flux
Figure 4.1: Structure of a module with a thermal buffer.
thermal buffer
solder chip
DCB
cooling
heat flux structure
Figure 4.2: Structure of integrated module with a thermal buffer.
This chapter starts with an introduction of the concept of thermal buffers. They are
investigated analytically and experimentally regarding their thermal impedance. Simpli-
fied thermal models of the cooling structures are created and used in a transient ther-
mal simulation over realistic mission profiles to determine the junction temperature. A
rainflow-counting algorithm is used to extract thermal cycles. The lifetime of modules
with and without thermal buffers are compared based on the extracted cycles and an
empirical aging model to show the effectiveness of the thermal buffers. The chapter closes
with a summary. Aspects of this work have already been published in [158].
4.1 Thermal Buffers
A thermal buffer is an element that increases the thermal capacity of a power device
without influencing the thermal resistance of the module. It can be realized with a small
block with a high thermal capacity that is directly placed on top of the semiconductor. For
passive buffers, metals with a solderable surface are a possible choice for the integration
in a power module. A cuboid made of copper is an obvious choice due to its high specific
thermal capacity and solderability. Aluminum with its higher specific thermal capacity
achieves a higher capacity per mass, but a lower capacity per volume due to the lower
density. Furthermore, it requires a surface treatment such that it is solderable.
The addition of extra thermal capacity by soldering a metal buffer on top of the die has
the potential to dampen thermal cycles and, thus, to lower degradation during operation.
However, soldering a large volume of metal on top of die with a large coefficient of thermal
expansion (CTE) mismatch causes a lot of stress in the soldering layer and the die. To
counteract the thermomechanically induced strain, the thermal buffer can be manufac-
38
4.1 Thermal Buffers
tured with micro-fins facing the semiconductor as investigated in [26], [113]. Only those
fins are soldered onto the chip, relieving the stress caused by the heated copper block.
When thermal buffers are directly placed on top of the die, it may even be of advantage to
use the materials of the die itself and, thus, achieving perfect CTE matching. Reducing
the oversizing of power modules, e.g. reducing the amount of active semiconductor die in
the package, by using additional semiconductor material for thermal buffers is counter-
intuitive at first. However, the thermal buffers are of passive electrical nature and must
not be processed to realize complex, active electronic devices. Consequently, cheap ma-
terials with low purities can be used for the realization of thermal buffers. However, they
usually require a surface treatment to become solderable or to be used with other bond-
ing techniques. Values for common materials are given in Table 4.1 obtained from [103].
Copper has the highest capacity per volume, but not per mass. The semiconductor ma-
terials offer lower thermal capacities per volume, but are still suitable as they are within
the same range of thermal capacity of metals. For example, silicon exhibits half of the
thermal capacity per volume as copper.
Since no additional material is added within the cooling path of the power module, the
thermal resistance of the power module is maintained. The structure of a conventional
module attached to an external heatsink with such thermal buffers is shown in Figure 4.1.
Figure 4.2 depicts the structure for a module with an integrated cooling structure as
presented in the previous chapter. The thermal buffer transiently absorbs parts of the
heat when the semiconductor is generating losses. Hence, it slows down the heating-up
and temporarily buffers thermal energy. It releases the heat through the device when the
device temperature decays resulting in a slower cool-down of the junction temperature.
Due to the placement of the thermal buffers in close proximity to the semiconductors,
the thermal buffers have a low thermal resistance to the die. Thus, they provide a lower
impedance path for the heat flow than the baseplate of conventional power modules,
where the heat flow must pass through the ceramic of the DBC. The amount of added
thermal capacity is limited as the space on top restricted, which is especially the case for
small SiC devices. As a result, thermal buffers are anticipated to be able to dampen fast
temperature swings, but cannot influence long thermal cycles.
Table 4.1: Material parameters for thermal buffers

material specific thermal volumetric heat CTE
capacity cp in J/kg K capacity in J/mm3 K in 10−6 1/K
aluminum (Al) 897 2.43 × 10−3 23.1
copper (Cu) 385 3.45 × 10−3 17
Si 710 1.65 × 10−3 2.6
SiC 670 2.33 × 10−3 4.3
39
100

150
with buffer
without buffer
100 10-1
50 10-2
with buffer
without buffer
0 10-3
0 1 2 3 4 5 10-3 10-2 10-1 100
Time in s Time in s
(a) Simulated junction temperature (b) Simulated temperature difference
Figure 4.3: Simulated transient junction temperature.
Conventional packaging technologies rely on aluminum bond wires that are bonded onto
the top-side of the die with an aluminum metallization. The aluminum metallization does
not allow the soldering of thermal buffers to the chip. However, molded modules with
soldered lead-frames on both sides of the chips, for example [67], exhibit a similar structure
as depicted in Figure 4.1. The thin copper layer applied with the Danfoss Bond Buffer
technology [134] also provides a possibility for the integration into power modules. Hence,
by modifying the packaging technology, thermal buffers can be effectively integrated into
module designs. The utilized manufacturing technology presented in Chapter 5 with a
nickel-plated die surface and copper bonds also allows the integration of thermal buffers
into the package design.
To determine the influence of the thermal buffer on the transient thermal response, a ther-
mal buffer is added to the transient CFD simulation with ANSYS Fluent of the previous
chapter. A comparison of the transient junction temperatures between the package with
and without buffer is depicted in Figure 4.3 for a power step from 300 W to 0 W. The
simulated junction temperatures of the models in Figure 4.3a show that the thermal buffer
dampens the temperature gradient of the device after a power step. The temperature fall
is slower during the cool down, e.g. the device with thermal buffers requires longer to
reach the steady-state temperature. The temperature difference between the modules is
maximal 26 °C. The thermal buffer is able to influence the junction temperature during a
time period of about 2 s after the power step. Figure 4.3b depicts the calculated thermal
impedances of the modules that shows the influence during short time periods up to 2 s.
For experimental verification, a thermal buffer implemented as a copper cuboid with an

edge length of 5 mm is added to the prototype with milled cooling channels as depicted
in Figure 4.4. The thermal buffer is soldered on top of the existing copper bond for
the source connection. The transient thermal response of the junction temperature and
the thermal impedance are measured and compared to the one without thermal buffer.
40
4.1 Thermal Buffers
Figure 4.4: Prototype with thermal buffer on top of die.
100
160
with buffer
140 without buffer
120
100 10-1
80
60 10-2
40
with buffer
20 without buffer
0 10-3
0 1 2 3 4 5 10-3 10-2 10-1 100 101
Time in s Time in s
(a) Junction temperature (b) Thermal impedance
Figure 4.5: Measurement of prototype with and without thermal buffer.
The result is shown Figure 4.5. There is a significant influence on the transient junction
temperature with a difference of up to 20 °C between the two prototypes while the steady-
state temperature remains unchanged. The transient thermal response is altered with the
thermal buffer for a time period of up to 2 s after a power step. Furthermore, the thermal
impedance of the two prototypes show that there is no influence at all on the junction
temperature for about 10 ms. This is different compared to the simulation and can be
explained by the fact that the copper bond of the top-side connection of the prototype
acts as a small thermal buffer. This also means that larger thermal buffers are unable to
help during short-circuit conditions because SiC devices are damaged within microseconds
during overload [23].
The simulation and measurement demonstrate that thermal buffers have the potential to
dampen thermal cycles. Due to the small amount of added thermal capacity, the time
period during which the thermal buffers can dampen the junction temperature is limited
to about 2 s. The potential of the added thermal capacity regarding the degradation and
lifetime of the module is therefore examined in the next section to determine its impact
during realistic mission profiles.
41
4.2 Simulation Setup
The previously presented accurate but slow CFD models of the cooling structure are not
feasible for mission profile simulations due to the required computation power. Hence,
faster models are created based on the finite volume method utilizing a previously de-
veloped framework [16], [49], [125], [172]. The model is transformed to a reduced order
state-space model to support fast simulations. A loss and degradation model are added
to the thermal models in a MATLAB ® /Simulink environment to conduct fast lifetime
estimations over mission profiles.
4.2.1 Thermal Models
The integrated cooling structure presented in the previous chapter is modeled with the
finite volume method. To build a half-bridge module that can be used in inverter oper-
ation, a second SiC MOSFET is added to the model. The model setup is based on the
geometry of the module and material parameters such as thermal conductivity and heat
capacity. The fluid cooling structure of the module is modeled analytically with a con-
stant heat transfer coefficient. This heat transfer coefficient is derived from the previous
simulations and measurements.
A visualization of the model for the integrated cooling structure and the temperature
increase with a simulated input loss of 300 W is shown in Figure 4.6. A total number of
six different models are created using the simulation framework. The original structure
without a thermal buffer and with buffers with a height of 0.5 mm, 1 mm, 2 mm, 3 mm,
4 mm and 5 mm are modeled. This corresponds to an added thermal capacity of 44.9 mJ/K,
(a) Temperature without buffer (b) Temperature with buffer
Figure 4.6: Visualization of the model and its temperature increase.
42
100
10-1
without
0.5 mm
10-2 1 mm
2 mm
3 mm
4 mm
5 mm
10-3 -4
10 10-3 10-2 10-1 100 101
Time in s
Figure 4.7: Thermal impedance of MOSFET1 for different buffer heights and without
buffer.
89.8 mJ/K, 179.6 mJ/K, 269.4 mJ/K, 359.2 mJ/K and 449 mJ/K, respectively. The thermal buffers
are designed such that they cover the entire die area. The two MOSFETs of the half-
bridge are denoted as MOSFET1 for the upper and MOSFET2 for the lower switch in
Figure 4.6.
In Figure 4.7, the thermal impedance of the models with thermal buffers of different
heights of 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm and 5 mm and without a thermal buffer
is depicted for a simulated power loss step of 300 W. The maximum achieved thermal
impedance reduction for the integrated module is 0.15 K/W or 45 %. The static thermal
resistance of the model is 0.40 K/W.
A bode plot of the frequency response function (FRF) of MOSFET1 for all variants is
shown in Figure 4.8. As can be observed from the bode plot, there is a significant influence
on the FRF in the range of 1 Hz to 10 kHz for the examined sizes of thermal buffers. While
the smallest buffer with only 1 mm copper on top exhibits a lower magnitude at around
1 Hz, a buffer with a height of 5 mm already shows a lower magnitude above 0.1 Hz. It
can be observed that the buffer increases the phase at a bandwidth from 10 Hz to 100 Hz
depending on the buffer size. Only a small amount of thermal capacity already has a
significant influence on the FRF. The copper thickness of the smallest buffer is in the
range of the copper found within molded modules with a copper lead-frame on top. The
results motivate to further investigate the potentials of extra thermal buffers in power
modules.
43
100
without
0.5 mm
10-1 1 mm
2 mm
10-2 3 mm
4 mm
5 mm
10-3
0
Phase in °
-20
-40
-60
-80
10-2 10-1 100 101 102 103 104
Frequency in Hz
Figure 4.8: FRF of MOSFET1 for different buffer heights and without buffer.
0.9
0.8
0.7
0.5 mm
0.6 1 mm
2 mm
0.5 3 mm
4 mm
5 mm
0.4
10-2 10-1 100 101 102 103 104
Frequency in Hz
Figure 4.9: Relative magnitude for different buffer heights referenced to model without
buffer.
A relative comparison of the magnitudes of the thermal impedance over frequency for
modules with thermal buffers to the module without buffer is presented in Figure 4.9.
The magnitudes of the thermal impedance of models with thermal buffers are referenced
44
Current in A
80 100
50
60
Speed in km/h
Current amplitude
0
0 500 1000
40
Frequency in Hz
Voltage in V
400 150
20 100
200 Voltage amplitude 50
Excitation frequency
0 0 0
0 500 1000 0 500 1000
Time in s Time in s
(a) Speed profile (b) Calculated amplitudes
Figure 4.10: Lublin driving cycle data
to the model without a thermal buffer, i.e. |Zth (jω)|/|Zth,ref (jω)|. A maximum reduction of
55 % can be obtained by implementing the buffers on top of the SiC MOSFETs with the
integrated cooling structure. The relative presentations reveal that the thermal buffers
significantly influence the FRF up to frequencies in the range of 1000 Hz. At this point,
the internal thermal capacity of the die become dominant. A saturation effect is visible
when increasing the thermal buffer above 3 mm. The minimum magnitude is not achieved
with the largest thermal buffer. Instead, the thermal buffers can be utilized to tune the
transient thermal response of the power module for certain frequencies. Consequently,
the power module can be designed for specific applications that exhibit these frequencies
during their mission-profiles for maximizing the lifetime at minimum cost.
4.2.2 Mission Profiles
For dc-dc converters, thermal cycles occur due to transient power demands. This results in
varying currents and, thus, varying losses and changing junction temperatures. For drive
inverters, the current waveform is sinusoidal and depends on the rotating speed of the
machine causing thermal cycles even during constant power operation. A low fundamental
frequency of the sinusoidal waveforms is a common source for causing degradation in
power modules [122]. Hence, emphasis is put on inverter operation of the power module
to evaluate the degradation and lifetime instead of operation in a dc-dc converter.
For the lifetime simulations, the Lublin heavy-duty driving cycle [47] is utilized with
a duration 1400 s. The power is chosen such that the voltage and current stay within
reasonable range of the utilized power modules and devices [192], [193]. The speed profile
of the Lublin driving cycle as well as the calculated amplitudes of the phase current and
the line-to-neutral voltage waveforms are shown in Figure 4.10. The Lublin cycle is a low-
45
Current in A
100
50
Speed in km/h
100 Current amplitude

0
0 500 1000 1500
Frequency in Hz
Voltage in V
50 400 300
200
200 Voltage amplitude 100
Excitation frequency
0 0 0
0 500 1000 1500 0 500 1000 1500
Time in s Time in s
(a) Speed profile (b) Calculated amplitudes
Figure 4.11: WLTC driving cycle data
speed driving cycle with maximum velocities just above 60 km/h as shown in Figure 4.10a.
Due to the strong acceleration, large current pulses are found within the driving cycle as
depicted in Figure 4.10b.
Another cycle utilized for the evaluation of thermal buffers is the Worldwide harmonized
Light duty driving Test Cycle (WLTC) class 3 driving cycle with a duration of 1800 s
[171]. The speed profile of the WLTC cycle as well as the calculated amplitudes of phase
current and line-to-neutral voltage waveforms are shown in Figure 4.11. The WLTC cycle
consists of different parts denoted as low, medium, high and extra high. Especially in the
high and extra high parts, starting after 1200 s, a higher speed with a maximum of about
130 km/h is demanded as shown in Figure 4.11a compared to the Lublin cycle.
The voltage and current waveforms of both cycles are calculated based on a model of an
induction machine that is operated with a field-oriented control. The waveforms are used
to calculate the losses in the power module during the simulation.
4.2.3 Loss and Lifetime Estimation
The power loss model of the MOSFET inverter is divided into the conduction losses and
switching losses. The duty cycle for each device in the half-bridge is calculated from the
line-to-neutral voltage for each simulation step. The conduction losses PCond are modeled
with the ohmic equation with a temperature-dependent Rds,on for a temperature difference
∆ϑ and the phase current iph according to:
PCond = Rds,on (1 + α0 · ∆ϑ) · iph 2 (4.1)
46
The temperature coefficient α0 is derived from the datasheet. The switching energies are
interpolated from the datasheet values to the voltage and phase current and multiplied
with the switching frequency of the inverter. It is assumed that synchronous rectification
of the MOSFET inverter is applied.
The mission profile simulation is carried out in a MATLAB ® /Simulink environment.

The calculated current and voltage waveforms of the driving cycle are fed into the loss
models. The calculated transient losses are passed to the thermal models that output
the switching-period averaged junction temperature of the devices. After the transient
simulation in MATLAB ® /Simulink , the rainflow-counting algorithm of MATLAB ® is
used to extract and classify the thermal cycles following [5]. The thermal cycles are
fed into an enhanced LESIT lifetime model [8]. The number of cycles to failure Nf is
calculated with:
β2
Nf = K · ∆ϑj β1 · e ϑj +273 · tcycle β3 · Iwire β4 · Ub β5 · Dwire β6 (4.2)
where ϑj is either the maximal, minimal or average junction temperature of the thermal
cycle and tcycle is the power-on-time of the device during the cycle. Ub is the blocking
voltage of the device, Dwire the diameter of the bond wire and Iwire the current per bond
wire. K and βi are parameters which are determined empirically.
The original LESIT model [56] and its derivatives [8] are empirical models and their
parameters are determined and fitted on the basis of experiments. The parameters are
also heavily dependent on the used devices and manufacturing technologies. For example,
the die size, bond wire thickness and materials, die-attach material such as solder or silver-
sintering significantly influence the degradation mechanisms and require the models to be
re-evaluated based on a statistically representative quantity. The parameters are usually
not publicly available for the packages available on the market. The parameters are simply
unknown when designing custom power electronic packages unless time-consuming cycling
tests are conducted.
To show the influence of thermal buffers more independently of the technology, this work
investigates the relative increment of lifetime that results from a change of the thermal
loading. For that purpose, the number of cycles to failure for a single detected cycle can
be normalized to a reference cycle that is specified by the data of the device with the
highest degradation:
β1 β3
β2 β2

Nf ∆ϑj ϑj +273
− ϑ +273 tcycle
= ·e ref
· (4.3)
Nf,ref ∆ϑref tcycle,ref
Referencing the degradation to a base cycle reduces the number of required technology
parameters to β1 , β2 and β3 . While these technology parameters still have an influence
47
on the calculated degradation, relative tendencies between power modules with and with-
out thermal buffers due to the different thermal behavior can be derived. This allows
the evaluation of a power module design that includes thermal buffers relatively to a
power module design without thermal buffers. However, this procedure does not allow to
compare the absolute lifetime of the packages or to compare the results to other power
electronics module, which may even utilize completely different technologies.
The degradation caused by each individual thermal cycles are linearly accumulated [16] to
calculate the state-of-degradation (SOD) or total degradation and is calculated according
to:
n
X 1
SOD = (4.4)
i=1
Nf i
where Nf i is the number of cycles to failure calculated for each individual thermal cycle
according to Equation (4.2) and n equals the quantity of all determined thermal cycles.
The number of cycles to failure for the complete driving cycle Nf,cycle is the inverse of the
total degradation.
1
Nf,cycle = (4.5)
SOD
4.3 Lifetime Simulation Results
The lifetime simulation results of the power modules with and without thermal buffers
are presented and compared for the Lublin cycle and the WLTC.
4.3.1 Lublin cycle
Figure 4.12 shows the results from the rainflow-counting algorithm [5] for MOSFET1 of
the module. The maximum amplitude of the observed cycles does not exceed 60 °C due
to the low thermal resistance of the module. When adding a thermal buffer and further
increasing the thermal capacity, the amplitudes of the cycles are lowered as can be ob-
served with the shift of cycles to the left in the histograms. Especially, there is a reduction
of temperature cycles with large cycle amplitudes greater than 40 °C. Figure 4.12 also
shows very similar distribution of the modules with thermal buffers greater than 3 mm
indicating that the effectiveness of the thermal buffer saturates.
48
without 0.5 mm 1 mm 2 mm 3 mm 4 mm 5 mm
104
Number of cycles
2
10
100
0 30 60 0 30 60 0 30 60 0 30 60 0 30 60 0 30 60 0 30 60
Cycle amplitude in °C
Figure 4.12: Histogram of calculated temperature cycles for MOSFET1.
Compared to the results for a commercially-available SiC power module the number of
detected cycles is lower. The data of the commercially-available SiC power module is
given in Appendix A.2.3. The thermal resistance of the integrated cooling structure is
0.4 K/W. The thermal resistance of the commercial power module is 0.56 K/W, which is an
increase of 40 % to the integrated cooling structure. The lower thermal resistance already
minimizes the thermal cycles of the module as long as the average load is kept at the
same level, i.e. the current rating is not increased because of the lower thermal resistance.
Besides the thermal cycles, a comparison of the calculated degradation of the module is
not possible due to the different packaging technologies.
Figure 4.13 displays the calculated cycles to failure per unit and the total degradation
referenced to the reference values for MOSFET1. The MOSFET1 exhibits a slightly
higher amount of degradation compared to MOSFET2 and is the lifetime-limiting device
of the module within the Lublin driving cycle. Even a small thermal buffer with a height
of only 0.5 mm has a significant influence on the lifetime performance by doubling the
cycles to failure or reducing the total degradation by a factor of two. With thermal
buffers greater than 2 mm, it is possible to triple the lifetime of the module. Increasing
the thermal buffer from 2 mm to 5 mm calculates to a lifetime enhanced by a factor of
four for MOSFET1. The Lublin driving cycle has several short time periods during which
a large current is required as Figure 4.10 shows. This results in short pulses of power loss
and temperature rise, which are effectively damped by the thermal buffers. Hence, even
small buffers are able to to enhance the lifetime significantly for this driving cycle. While
increasing the thermal capacity of the thermal buffer still increase the calculated lifetime,
the incremental benefit is diminishing.
49
6 1
Total degradation in p.u.

without
Cycles to failure in p.u.
0.8 0.5 mm
1 mm
4 without 2 mm
0.6
0.5 mm 3 mm
1 mm 4 mm
0.4
2 2 mm 5 mm
3 mm
4 mm 0.2
5 mm
0 0
MOSFET1 MOSFET2 MOSFET1 MOSFET2
Devices Devices
(a) Calculated cycles to failure (b) Calculated degradation
Figure 4.13: Calculated cycles to failure and degradation for Lublin cycle.
In Figure 4.14, the 20 individual, most significant thermal cycles regarding their degrada-
tion are shown in descending order for MOSFET1. All values are given per unit referenced
to the total degradation during the Lublin driving cycle for the model without thermal
buffers. Only a few cycles are responsible for most of the estimated degradation while
the other several thousand cycles only contribute little. In fact, the 20 most significant
cycles account for over 95 % as revealed by the accumulated degradation. This signifi-
cant contribution to the degradation is lowered by the thermal buffers in line with the
total degradation in Figure 4.13. With a thermal buffer of 5 mm height, the accumulated
degradation of these 20 cycles decreases to 24 % of the total degradation during the Lublin
cycle for a module without thermal buffer.
When only a few cycles during a full driving cycle contribute the most to the degradation,
it is beneficial to optimize especially for these specific thermal cycles of the mission profile.
Consequently, taking the application into account, analyzing driving cycles and identifying
the dominant cycles is of major importance. Design elements including but not limited to
thermal buffers can be developed for mitigating these dominant cycles and enhance the
lifetime of the modules considerably. If the number of semiconductors and die sizes are
reduced due to these optimizations while achieving the same performance, cost of power
electronic modules can be lowered. Hence, another possibility is to downgrade the cooling
structure when thermal buffers are in use and save volume, size and cost in return.
Figure 4.15 shows the same 20 individual cycles as Figure 4.14, but presents their tem-
perature amplitude instead. The effect of the thermal buffers is observable again because
the amplitudes are lowered on average by 10 °C with the largest thermal buffer. Even if
the amplitudes are only lowered by a few degrees for each individual cycle, the positive
influence on lifetime is significant as demonstrated before. However, the degree of this
effect is largely dependent on the technology parameter β1 in Equation (4.3) and, hence,
must be evaluated for each manufacturing technology individually.
50
0.25 1
Accumulated degradation in p.u.

0.2 0.8
Degradation in p.u.
0.15 0.6
0.1 0.4
0.05 0.2
0 0
0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20
Individual cycle
Figure 4.14: Degradation of most significant thermal cycles for Lublin cycle.
60
Temperature amplitude in °C
50
40
30
20
10
0
0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20
Individual cycle
Figure 4.15: Temperature amplitude of most significant thermal cycles for MOSFET1
for Lublin cycle.
Figure 4.16 shows the same 20 individual cycles with their cycle time depicted. The
thermal buffers only have limited influence regarding the cycle time tcycle , which Equa-
tion (4.2) and Equation (4.3) show that it also has an influence on the degradation. With
51
700
600
500
Cycle time in s
400
300
200
100
0
0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20
Individual cycle
Figure 4.16: Cycle time of most significant thermal cycles for MOSFET1 for Lublin
cycle.
the addition of thermal buffers, the cycle time of the thermal cycles is nearly the same.
The prominently visible cycle times of for example 700 s or 350 s are not changed at all
with the addition of the thermal buffers. One cycle with a cycle time of about 200 s is
reduced with thermal buffers with a height greater than 2 mm. Otherwise, only the order
in which they contribute to the overall degradation changes. Hence, the thermal buffers
mostly lower the degradation by the reduction of the temperature amplitude of the cycles
as outlined in Figure 4.15.
A potential for future investigations can be deduced when looking at the cycle times of the
mission profile. The cycle time of the cycles causing the most degradation is usually several
seconds up to a few hundred seconds long. In combination with the fast transient response
of integrated cooling structures with time constants below 2 s that can be improved via
the introduced thermal buffers, there is a realistic opportunity to influence the junction
temperature by adjusting the cooling circuit during the long thermal cycles. For example,
the thermal performance can be influenced by adjusting the volume flow with increasing
or decreasing the pumping power. As a consequence, the junction temperature variation
during the mission profile can be flattened. The amplitude of the long thermal cycles
can be reduced when the pumping power is adjusted based on the mission profile. Only
the slow cycles must be mitigated to achieve considerably better lifetime as shown by the
20 cycles that cause the most degradation. If the cooling circuit is integrated into the
control strategy as presented in [197], the degradation of these cycles can potentially be
mitigated.
52
2 1

0.8
1.5
without without
0.6
0.5 mm 0.5 mm
1
1 mm 1 mm
0.4
2 mm 2 mm
0.5 3 mm 3 mm
4 mm 0.2 4 mm
5 mm 5 mm
0 0
Devices Devices
(a) Calculated cycles to failure (b) Calculated degradation
Figure 4.17: Calculated cycles to failure and degradation for WLTC.
In Appendix A.2.2 the results for the Lublin cycle are presented with thermal buffers made
of SiC. Due to the lower thermal capacity, the results show a lower lifetime improvement
by 25 % compared to copper. However, this still corresponds to an improved lifetime by a
factor of three compared to a module without any thermal buffer because of the lowered
thermal loading.
4.3.2 WLTC
The results for the calculated degradation for the WLTC are depicted in Figure 4.17. The
obtained lifetime improvement with thermal buffers is limited with this cycle. A decrease
of the number of cycles to failure of 30 % is achieved with the thermal buffers regardless
of the height and added thermal capacity.
The reason for the limited influence during the WLTC is seen in Figure 4.18 which depicts
the 20 cycles causing the most degradation. The degradation is dominated by only three
cycles that account for 86 % of the total calculated degradation. This is reduced to about
72 % when thermal buffers are added. The thermal buffers with their limited thermal
capacity, which adjusts the thermal characteristics in the 1 s range, cannot significantly
change the amplitudes of these three cycles. The rest of the thermal cycles are more
significantly damped with the thermal buffers, but only have a minimal influence on the
overall calculated degradation. Whereas the Lublin cycle exhibits very short periods with
a high power requirement that causes short thermal cycles, the WLTC does not have
such short periods with high power losses. However, such long thermal cycles will not
be damped by power modules with larger baseplates either. The thermal capacity of the
baseplate is still too limited for cycle periods as long as e.g. almost 1600 s which is the
longest detected cycle as depicted in Figure A.11. This is another argument for the control
53
0.35 1

0.3
0.8
Degradation in p.u.
0.25
0.2 0.6
0.15 0.4
0.1
0.2
0.05
0 0
0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20
Individual cycle
Figure 4.18: Degradation of most significant thermal cycles for WLTC.
of the pumping power based on the mission profile to dampen long thermal cycles, which
complements the thermal buffers. Thermal buffers are an effective tool to reduce thermal
cycles in many applications that exhibit short-term thermal cycles in the range of up to
a few seconds. For long-term thermal cycles, complementing solutions are necessary to
further reduce the degradation of power modules. Consequently, it is necessary to know
the mission profile and the target application that allows identifying the most harmful
thermal cycles and accordingly taking specific measures to maximize the reliability.
54
4.4 Summary
4.4 Summary
In this chapter, the concept of thermal buffers has been investigated as a way to increase
the lifetime of power modules. Thermal buffers only increase the thermal capacity of
power modules and do not influence the static thermal resistance. Consequently, they
lower the thermal impedance and dampen thermal cycles during operation. With the
example of a highly-integrated cooling solution in a power module with a fast transient
response, the influence on the thermal impedance has been demonstrated by simulations
and experimental prototypes. Using fast thermal, loss and empirical lifetime models,
the lifetime of the power module has been investigated over realistic mission profiles of
motor driving cycles. The lifetime simulations shows that thermal buffers considerably
enhance the lifetime of power modules due to the changed thermal loading of the devices
and the package. The 20 most dominant cycles cause more than 90 % of the calculated
total degradation. Consequently, a large decrease of the degradation is achieved when the
thermal buffers are able to dampen these dominant cycles. The thermal buffers are able
to dampen short-term thermal cycles significantly due to their influence on the transient
thermal response for up to a few seconds. For long-term thermal cycles, the thermal
buffers are ideally complemented with additional measures, for example adjusting the
pumping power based on the power demand in the driving cycle. The simulated decrease
of the degradation during the WLTC is 30 %. During the Lublin driving cycle, the lifetime
increases by a factor of more than four.
Thermal buffers provide an additional design parameter to enhance the lifetime of power
modules during realistic mission profiles. The investigated thermal buffers only require
tiny amounts of materials. They are a cheap alternative to additional, costly semicon-
ductor die area or other lifetime enhancing techniques. They can be used to tailor power
modules to the specific lifetime requirements of the target application.
55
56
5 Application-Specific Power Module
In Chapter 3, a high-performance cooling structure has been developed for SiC devices.
The cooling structure pushes the thermal operating boundaries of small SiC devices due
to the ability to dissipate high heat flux densities due to the integrated and optimized
design for the selected devices. Thermal buffers have been investigated that are able to
mitigate the arising problems regarding lifetime due to low thermal capacity of this power
module concept in Chapter 4.
Besides an optimal thermal design, an optimized electrical design of the power module is
necessary in order to utilize the full potential of SiC devices from an electrical point of
view. On the one hand, voltage overshoots and ringing must be mitigated or kept at a
reasonable level in order to maintain safe operation. On the other hand, switching must
be as fast as possible for high-frequency operation to limit power loss.
The fundamental advantages of dc-dc converters on the basis of WBG devices stem from
increased switching frequencies [89]. Dc-dc converters are required in mobile applications,
for example in the drive-train [149], [188], vehicle chargers [141] or in future more electric
aircrafts with +/-270 V systems [17], [130]. In dc-dc converters, the size of the passive
components — capacitors and inductors — decreases with increasing switching frequen-
cies and improve the power density of dc-dc converters [149], [159]. Hence, setting the
switching frequency as high as possible is key when aiming for highest power density.
Moreover, the higher cost of SiC devices can at least be mitigated on a system level
by lower cost of the passive components due to their smaller size and lower amount of
required materials [21]. But increasing the switching frequency causes higher switching
losses in the semiconductors as well as the passive components. Hence, steepest switching
transients must be achieved for low switching losses when designing converter with highest
power densities.
The advantage of inverters on the basis of WBG devices are higher efficiency characteris-
tics [19]. However, increasing the switching frequency of machine inverters has a limited
effect regarding the power density [11]. The size of the machine is ultimately dependent
on its rotating speed for a given power. An increase of the converter switching frequencies
yields no major advantages beyond a certain level besides e.g. opportunities for improved
control. Furthermore, fast switching transients may cause damage to the windings of
machines [52], [53].
57
Increasing the switching frequency only provides modest advantages for inverters, but
promises large gains for dc-dc converters regarding their power density. Hence, an application-
specific power electronic module is developed based on SiC MOSFETs for the application
in a dc-dc converter to evaluate the potentials of an application-specific SiC power mod-
ule. Under the premise of maintaining a lateral layout for easy manufacturing, a power
module design is presented with loop inductances below 5 nH. Simulations and mea-
surements verify the design. The electrical switching characteristics of the module are
evaluated using double-pulse measurements. The measurements show that the presented
module is able to fully exploit the capabilities of modern SiC MOSFETs without requir-
ing 3D-packaging technologies. It provides a high-density package for very high-frequency
operation and is specifically designed for the application in a synchronous boost converter
with bidirectional power flow. Aspects of this work have already been published in [156],
[161].
5.1 Design of Power Module
An overview of different packaging concepts investigated in literature has been given in

Section 2.1. Many of the presented concepts require advanced manufacturing techniques
such as PCB-embedded die or multilayer ceramic substrates to achieve modules with
low parasitic inductances. However, it has also been demonstrated that low-parasitic
half-bridge modules can be manufactured with state-of-the-art techniques. In contrast
to most of the low-inductive designs presented in literature, the developed power module
is designed under the premise of being manufacturable with state-of-the-art techniques,
e.g. a lateral layout, wire bonds and die-attach soldering. The low-parasitic electrical
characteristics of the presented module are achieved with an optimized geometry and an
application-tailored, integrated design only.
For a lateral design, the options for a half-bridge module layout that minimizes the stray
inductances are limited. The layout presented in [32], [33] is such a low-inductive commu-
tation cell. A similar concept is introduced in [54]. As the enclosed area of the commuta-
tion loop must be kept as small as possible to achieve a low stray inductance, the dc-link
plus and minus connections must be directly placed next to each other. However, in the
designs presented in literature the low stray inductance is only simulated up to the small
capacitor directly soldered onto DBC, which is able to store a low amount of energy. A
design with a local capacitor near semiconductors and a larger external dc-link capacitors
is susceptible to over-voltages and oscillations between the capacitors [54], [86] due to the
stray inductance between the two capacitances. Damping resistors are necessary to limit
these oscillations to reasonable levels.
To overcome the disadvantages of local and external dc-link capacitors, the total dc-
link capacitance of the converter is entirely integrated onto the DBC. As the switching
frequency of the converter is targeted to be 300 kHz or higher, the integration is feasible as
58
DC+ C
DC capacitor
CDC
DC- MOSFET
50 mm
ceramic
AC
copper
SG SG
32.5 mm
Figure 5.1: Layout of the commutation cell.
the required capacitance is lowered compared to converters with low switching frequencies.
This eliminates the need for damping resistor and lowers the component count and power
density increases. The capacitors are also cooled via the DBC. The required capacitors
must provide a sufficiently large capacitance and low size while having low-loss high-
frequency characteristics combined with a high resonant frequency. The power module
integrates four CeraLink™ FA3 900 V capacitors [39] for a total capacitance of 3 µF. As
the integrated cooling structure causes almost no heat-spreading on the top side of the
substrate, the placement of the capacitors close to the semiconductors is not critical. The
calculation of the capacitance values for the converter is given in Section 6.1.3. With the
integration of the capacitors, the design of the module is an application-specific design
that is optimized for the application in a synchronous boost converter as described in
Chapter 6.
The design of the power module is depicted in Figure 5.1. Two SiC MOSFETs with
a nominal resistance of 25 mΩ and a voltage rating of 1.2 kV are utilized with a die
size of 6.44 mm x 4.04 mm [192] for the design of the half-bridge module. In favor of a
small occupied area and, thus, high power density, no SiC SBDs are used although they
might have beneficial properties for the switching energy at high currents [92]. However,
the added capacitance of the SiC SBDs also increases the switching energy for hard-
switched devices. The stray inductance of the module is minimized by means of an
optimal placement of the bare die close to each other on a lateral layout. This minimizes
the enclosed area of the power loop and the commutation path to the dc-link capacitors.
The area of the ac switching node must be kept as small as possible to minimize the
parasitic capacitance to the heatsink. As it is charged and discharged during turn-on and
turn-off of the devices, it also adds to the switching energy.
A low gate-loop stray inductance is also essential for fast switching devices [117]. The gate
drivers use Kelvin-source contacts and are directly attached to the DBC for a minimized
gate-loop inductance. The design and layout of the gate driver are kept symmetrical
between low and high-side. The gate driver circuit for the low and high-side MOSFETs
consists of 1EDI60N12AF isolated gate driver integrated circuit (IC) from Infineon [65]
and MGJ2D122005SC isolated gate drive supply from Murata Power Solutions [112].
59
gate drivers
AC
SiC
MOSFETs
DC- dc-link
capacitors
DC+
Figure 5.2: Manufactured prototype of integrated power module.
The gate driver has a low coupling capacitance over the isolation barrier to ensure low
common-mode currents caused by fast switching of the high-side gate driver. A turn-on
resistor is provided in the design of the gate driver while a turn-off resistor is omitted. It
has been previously demonstrated that the same SiC devices are safely turned off with only
the internal gate resistance with a power module exhibiting a higher gate-loop inductance
[149].
The prototypes are manufactured in-house. As available semiconductor die have an alu-
minum surface on the top side that is not solderable, the die have been nickel-plated to
create a solderable surface. The top side of the SiC MOSFETs is treated with an interme-
diate zincate solution and sodium hydroxide. This removes the Al2 O3 layer and forms a
thin layer of zinc on the surface, preventing any oxidation of the aluminum. Afterwards,
the die are treated with an electroless nickel-plating process. This removes the zinc layer
again and deposits a thin layer of a nickel-phosphorus alloy that can be soldered.
In a first step for the manufacturing of the module, the layout of the DBCs is manufactured
with a spray etching process. The SiC MOSFETs are then silver-sintered onto the AlN
DBC substrate with Argomax ® sinter-preforms [104] and a pressure of approximately
10 MPa. Together with the cooling structure on the bottom side of the DBC and the
capacitors, the top side of the SiC MOSFETs are soldered to copper bonds with a thickness
of 300 µm in a combined soldering process step with lead-free solder. The gate drivers
are separately soldered onto the module afterwards. Finally, the module is encapsulated
with a dielectric silicone gel as insulation. A picture of a manufactured prototype of the
design is shown in Figure 5.2. The thermal buffers that have been examined in Chapter 4
can easily be integrated on top of the copper bonds on each die when required.
60
cooling
structure
(a) Micro-channel cooling (b) Attached micro-channel cooling

structure. structure.
Figure 5.3: Cooling structure of the power module.
Copper bonds for the top side connections and die-attach silver-sintering deviate from the
state-of-the-art manufacturing of power modules, although they are increasingly utilized.
The techniques are used to manufacture the power module as they are available in-house.
However, standard manufacturing techniques such as die-attach soldering or aluminum
bond-wires can also be used as the module is based on a conventional lateral layout. From
an electrical point-of-view, only minimal disadvantages such as a slightly higher wire bond
resistance and slightly less thermally conductive die-attach material are to be expected.
The presented design requires a sufficiently effective cooling structure to be able to cool
both devices. The solution presented in Chapter 3 is such a structure as it is able to cool
hundreds of watts from a small area. The attachment of the cooling structure, which is
paralleled for two devices, is shown in Figure 5.3.
5.1.1 Analysis of Parasitic Elements
Various parasitic elements are of interest in the package as shown in the equivalent circuit
diagram in Figure 5.4, which is based on [38] and adapted to the module layout. The
semiconductor devices SL and SH have several internal elements such as the internal gate
resistance RG,int , the gate-source capacitance CGS the Miller-capacitance CGD and the
drain-source capacitance CDS . The output capacitance Coss is the sum of CGD and CDS .
The parasitic elements caused by the module layout are the stray inductance of the power
loop Lσ , which is arbitrarily divided into two equal parts Lσ/2 in the figure, and the
gate-loop stray inductance LG . The parasitic capacitances of the module layout are the
61
Lσ/2
SH DC+
CGD
LG RG,int CDS LDC
CGS CDC+
AC CDC
SL CSW
CGD CDC−
LG RG,int CDS
CGS
DC-
Lσ/2
Figure 5.4: Parasitic elements in the power module.
parasitic capacitance of the ac switching node CSW and the parasitic capacitances of the
dc-positive and dc-negative plane, CDC+ and CDC− . Furthermore, the integrated main dc-
link capacitance CDC has an internal stray inductance LDC . A common-source inductance
of the gate and the power loop is neglected because the Kelvin-source contact of the gate
loop is directly connected on top of the devices via separate copper bonds that is not
shared with the load current of the device.
The parasitic elements that are caused by the module layout of the proposed design are
evaluated based on a parameter extraction using ANSYS Q3D Extractor and impedance
measurements. ANSYS Q3D Extractor allows the extraction of parasitic circuit elements
such as inductance, capacitance and resistance of geometries. ANSYS Q3D Extractor
assumes a quasi-static field [90] and that the wavelength λ is much greater than the
length l of the considered conductor, i.e. λ l. Displacement currents are neglected for
inductances and resistances calculations. The inductive voltage drops from time-varying
magnetic fields are neglected for capacitance and conductance calculations. Consequently,
coupling effects like wave propagation, electromagnetic radiation, phase delays etc. are
neglected.
5.1.1.1 Power Loop
Figure 5.5 shows the simulation model of the module in ANSYS Q3D Extractor . The
simulated stray inductance Lσ from the terminals of the first capacitor is given in Fig-
ure 5.6. A stray inductance of 4.95 nH is achieved at 100 kHz. The targeted switching
frequency is in the range of 300 kHz to 400 kHz. At 333 kHz, the inductance drops to
4.55 nH. Higher harmonics of the switching frequency must also be considered because
the switching waveforms are more of trapezoidal shape than the sinusoidal waveforms as
62
Power loop inductance in nH

5.5
y
5.25
switching frequency
5
z resonant frequency
4.75
4.5
power loop
4.25
4
10-1 100 101 102
x Frequency in MHz
Figure 5.5: ANSYS Q3D Extractor Figure 5.6: Simulated stray inductance of
model of the power loop. the power loop.
simulated by ANSYS Q3D Extractor . The resonant frequency of the module is expected
to be in a frequency range of 50 MHz or higher. The resonant circuit created by the output
capacitance Coss of 220 pF [192] and the stray inductance simulated to be in the range of
4 nH to 5 nH calculates to a resonant frequency of about 150 MHz. However, the stray
inductance of the dc-link capacitor has also be considered and the total stray inductance
of the module will be higher, which will lower the resonant frequency of the module. At
100 MHz the stray inductance is 4.03 nH.
The lower stray inductance at high frequencies is the result of the proximity effect [147].
The current flow narrows to the innermost copper traces of the module at high frequencies.
As a result, this reduces the enclosed area of the conductor loop and, hence, the stray
inductance of the module.
For an experimental evaluation, a dummy prototype is constructed on a DBC, which is

depicted in Figure 5.7. Copper traces representing the topside copper bonds in the power
module are soldered onto the DBC similar to the final module, but no active devices are
included. The dummy prototype neglects the additional stray inductance caused by the
height of the die and the extra solder layer, which is negligible due to their comparably
small dimension. Connectors at the location of the terminals of the first capacitor are
added to connect the prototype to an Agilent 4294A Precision Impedance Analyzer .
The result of the impedance measurement is given in Figure 5.8. Compared to the sim-
ulation results, the slope of stray inductance over frequency is very similar. However,
approximately 0.25 nH of additional stray inductance is measured over the whole fre-
quency range. This can be attributed to the connectors to the impedance analyzer that
add additional stray inductance on their own.
63
Power loop inductance in nH

5.5
gate loop
5.25
connector
5
power loop
4.75
connector
4.5
4.25
4
10-1 100 101 102
Frequency in MHz
Figure 5.7: Dummy prototype. Figure 5.8: Measured stray inductance of

the power loop.
y
gate loop
z
x
Figure 5.9: ANSYS Q3D Extractor model of the gate loop.
5.1.1.2 Gate Loop
The stray inductance of the gate loop LG with Kelvin-source connection is simulated and
measured similar to the power-loop stray inductance. The simulation model for the gate
loop is depicted in Figure 5.9. Due to the symmetrical design, it is sufficient to simulate
only one gate loop of the power module. The results are shown in Figure 5.10. The
gate loop exhibits a stray inductance of 4.35 nH at 333 kHz that decreases to 3.73 nH at
100 MHz. The stray inductance measurement of the gate loop with the same dummy
prototype as depicted in Figure 5.7 is given in Figure 5.11. Compared to the simulation,
the stray inductance is higher again by about 0.25 nH. The measurement shows a slight
decrease of the stray inductance towards higher frequencies, which is not visible in the
simulation.
A low gate-loop stray inductance is essential for fast switching converters. Otherwise,
the RLC circuit consisting of the gate resistor, the parasitic inductance and the gate
64
Gate loop inductance in nH
Gate loop inductance in nH

5.25 5.25
5 5
switching frequency
4.75 4.75
4.5 4.5
4.25 4.25
4 4
3.75 3.75
3.5 3.5
10-1 100 101 102 10-1 100 101 102
Frequency in MHz Frequency in MHz
Figure 5.10: Simulated stray inductance of Figure 5.11: Measured stray inductance of
the gate loop. the gate loop.
capacitance connected in series may start to oscillate [117]. A Kelvin-source connection

is mandatory to reduce the gate-loop stray inductance and to minimize any coupling to
the drain current iD via common-source inductance. In [117] the maximum gate loop
inductance is calculated to 6.7 nH for the same SiC devices. The calculation includes
the internal gate resistance RG,int of 1.1 Ω of the device and 0.4 Ω internal resistance of
a gate driver circuit as the damping resistors in the RLC circuit. Hence, the gate-loop
stray inductance of the proposed design is sufficiently low to achieve a damped system
and safe operation, but the additional inductance of the gate driver PCB must be taken
into account as well.
5.1.1.3 Parasitic Capacitances
Another important characteristic are the parasitic capacitances of the power module.
Due to the high switching frequencies, parasitic capacitances contribute to the switching
energies for hard-switched devices. Furthermore, they cause common-mode currents and,
as a result, contribute to EMI issues because the bottom side of the DBC is usually
connected to ground via the heatsink. The parasitic capacitance of the devices itself
cannot be changed. The capacitances caused by the module layout shown by Figure 5.12
can be optimized and, thus, are investigated in detail.
The copper on both sides of the DBC form a plate capacitor. The resulting capacitance
can be analytically calculated or simulated with ANSYS Q3D Extractor . For this thesis,
ANSYS Q3D Extractor is utilized with a model similar to the ones for the gate and
power-loop inductances. A constant permittivity over frequency is assumed resulting in
constant capacitances.
65
x
y
CSW
CDC−
CDC+
Figure 5.12: Parasitic capacitances in the power module.
The capacitance of the ac switching node CSW is simulated to 36.3 pF, which includes the
area occupied by the high-side gate driver. The value seems rather low, but considering
voltage transients across the capacitor of e.g. dudtC = 100 V/ns, the resulting common-
mode current reaches iC = 3.63 A flowing through the grounded heatsink according to
equation:
duC
iC = CSW · (5.1)
dt
Additionally, the capacitance causes a higher switching energy as it is charged and dis-
charged during switching and must be minimized for this reason, too. The area of the ac
switching node can be reduced in size if smaller connectors replace the screw terminals
as depicted in Figure 5.2.
The copper traces of the dc-positive and dc-negative plane also exhibit parasitic capac-
itances to the grounded bottom side of the DBC. These capacitances CDC+ and CDC−
basically form integrated Y-capacitors as they are directly connected via the copper of
the bottom of the DBC side to the capacitance CSW of ac switching node. Due to the
module design with the dc-link capacitors integrated on the DBC, they create an ex-
tremely low-impedance Y-capacitor to the dc voltage lanes and the dc-link capacitors.
For the positive voltage copper trace, the simulated capacitance CDC+ is 75.6 pF. For the
negative voltage copper trace, the simulated capacitance CDC− is 63.4 pF. The values are
higher than the parasitic capacitances of the ac switching node. The capacitances provide
a low-impedance return path back to the dc-link for the common-mode currents and may
limit the emitted common-mode currents caused by very steep voltage transients.
66
5.2 Double-Pulse Measurements
iD uDS
SH
iL
Udc CDC iD
SL uDS
uGS
t
toff ton
(a) Schematic of double-pulse measure- (b) Schematic current and voltage
ment. waveforms
Figure 5.13: Principle of double-pulse measurement.
The transient performance of the SiC devices is of utmost importance to verify a safe and
reliable operation with very fast switching transients, especially when the SiC devices shall
be pushed towards the operation limits. Switching energies are also important to estimate
the junction temperature during operation in power electronic converters. The transient
behavior and the switching energies of semiconductors are commonly examined via double-
pulse measurements. Hence, extensive double-pulse measurements are conducted for the
proposed commutation cell design.
The basic circuit of a double-pulse setup is given in Figure 5.13a with all measured vari-
ables for the low-side switch SL . uDS is the drain-source voltage of the SiC MOSFET, iD
the drain current, uGS the gate-source voltage and the load current iL flowing through the
load inductor. The actual test bench available at the institute follows a more sophisticated
topology with auxiliary switches that allows setting voltage and current independently of
the used inductor [50]. As a result, the current and voltage waveform behave as schemat-
ically depicted in Figure 5.13b with toff and ton for the time instant of turning the switch
on and off.
An additional power module is built for the double-pulse test and the differences to the
original module are investigated in detail. Emphasis is placed on the low-inductive cur-
rent measurement with a Rogowski coil that is crucial to obtain a realistic double-pulse
measurement of the proposed power module. The measurement method is compared to
current measurements based on coaxial shunts for verification. Afterwards, the measure-
ment result of the power module are presented and discussed in detail.
67
optical gate
connector
DC+
SH
SiC
AC
MOSFETs CDC
tube for SL
Rogoswki coil
current iD
measurement
DC-
(a) Manufactured prototype (b) Location of current measurement for

double-pulse
Figure 5.14: Power module for double-pulse tests.
5.2.1 Power Module for Double-Pulse Tests
For the purpose of the double-pulse measurements, an additional power module is fabri-
cated based on a PCB, which is shown in Figure 5.14a. The module is manufactured on
a conventional PCB since no cooling is required for double-pulse tests, but simplifies the
handling of the prototype and adaptation to other measurement setups. The geometry
differences to the original design are kept minimal.
Double-pulse measurements of power modules with a very low stray inductance require
a low-inductive current measurement. Otherwise, the additional stray inductance of
the measurement device heavily influences the switching behavior. Especially for low-
inductive, integrated designs such as the proposed one, the current measurement must be
incorporated within the commutation cell design itself. It must be integrated within the
commutation path to the integrated dc-link capacitor CDC as depicted in Figure 5.14b.
Commonly used coaxial shunts exhibit an additional insertion inductance due to their
comparably large geometry [71]. For the given power module, the additional inductance
is measured to approximately 8 nH, which is in line with other values in literature [151],
[185]. Compared to Si IGBT modules with 30 nH or more, this is an additional inductance
of approximately 25 %. For the integrated power module, the inductance is larger than
the overall simulated inductance of the proposed commutation cell and would result in
68
an increase of the stray inductance of 200 %. The impedance of the circuit will be much
larger at higher frequencies and will cause a non-negligible change in switching behavior
and calculated switching energies. The over-voltage and voltage oscillations and the
switching energies will significantly defer from the module operated in the converter. The
effect of the measurement device must be kept minimal to obtain realistic measurements.
Therefore, a shunt measurement cannot be utilized for the proposed commutation cell.
Instead, a Rogowski coil design is utilized that is published in [59], [68]. It requires a
low-inductive Ω-shaped copper tube to be integrated into the power module that adds
several hundred pH to the stray inductance. The Rogowski coil is presented in detail in
Section 5.2.2.
Hence, the commutation cell design must be slightly altered for the double-pulse tests as
the Rogowski coil requires additional space compared to the actual power module design.
The only change in layout is made to account for the Rogowski coil current measurement
and voltage probes. The design is lengthened by 1 mm to account for additional space
that is required by Ω-shaped copper tube of the Rogowski coil. This minimally influences
the stray inductance of the module for double-pulse tests. Furthermore, the ac switching
node area is expanded to connect the voltage probe and the load inductor.
An optical fiber input is used for the gate driver for compatibility with the double-pulse
test bench. During turn-off, only the internal gate resistance of 1.1 Ω and the internal
impedance of the gate driver is used as resistance similar to the original power module.
The value of the external turn-on resistor RG,on is varied during the tests.
5.2.1.1 Influence of Measurement Setup on the Parasitic Elements
The double-pulse power module is fabricated to be similar in structure and design to

the original power module. However, small changes of the stray inductance and parasitic
capacitances are inevitable due to the insertion of the measurement probes and the usage
of a PCB. Thus, several ANSYS Q3D Extractor simulations are carried out for a proper
separation of the influences on the stray inductance.
A model of a DBC-based commutation cell is simulated with the copper tube required for
the Rogowski coil measurement for comparison. The model is shown in Figure 5.15a. The
resulting power-loop stray inductance is 5.62 nH at 333 kHz and 4.53 nH at 100 MHz. At
100 MHz the insertion inductance of the copper tube is 0.5 nH compared to the module
without the copper tube, which is an increase of 12 %. Therefore, the Rogowski coil based
current measurement provides a small increase of the stray inductance and is a viable
solution for a low-inductive current measurement while maintaining a high bandwidth.
The model of the PCB-based module is shown in Figure 5.15b. The parasitic switching-
node capacitances changes to 11 pF due to the FR4 material of the PCB with a lower
permittivity compared to the AlN ceramic and higher distance between the copper planes.
69
y y
z z
x x
(a) DBC-based module (b) PCB-based module
Figure 5.15: ANSYS Q3D Extractor model of power module for double-pulse tests.
This will cause a calculated measurement error of 7.77 µJ at 800 V compared to the original
module as the capacitance is charged and discharged during switching. Compared to
datasheet values, the error on the turn-off switching energies is approximately 2 % at
nominal currents. The power-loop stray inductances Lσ increases to 7.49 nH at 333 kHz,
which is an increase of approximately 1.9 nH or almost 50 %. The stray inductance at
100 MHz is 6.35 nH, an increase of 1.8 nH.
To investigate the source for this increase of the stray inductance, additional ANSYS Q3D
Extractor simulations are conducted. The influence of thickness of the copper traces on
the stray inductance is found to be negligible for this setup. For this, a model of the PCB
module is created but with an assumed copper thickness of 300 µm, which only shows a
reduction of the stray inductance by 0.18 nH. The most significant impact on the stray
inductance is caused by the different distance between the topside and backside copper
layers of the substrates. The distance is 1.55 mm for the PCB and 0.63 mm for the DBC.
Simulating the module with a PCB thickness of 1 mm already results in a total power-loop
stray inductance of 5.44 nH at 100 MHz, which is a reduction of almost 1 nH to 135 % of
stray inductance of the original module. Table 5.1 summarizes the results and shows that
the most significant influence stems from the distance between the topside and backside
copper layers.
Figure 5.16 shows the simulated surface current density on the backside of the module
at 100 MHz with the topside structure superimposed. Eddy currents are induced on the
copper layer on backside of the module. These currents oppose the generated magnetic
field and shield high-frequency magnetic fields. When the distance between the top and
bottom layer of the module decreases, the area of the magnetic field between both layers
decreases. Consequently, less energy is stored in the magnetic field, which reduces the
stray inductance. The influence of this effect is significant when designing power modules
with extremely low stray inductances as for the developed prototype a difference of about
2 nH is simulated, which is a 50 % increase compared to the original power module.
70
surface current x
density in A/m
500
450
400
350
300
250
200
150
100
50 y
z
0
Figure 5.16: ANSYS Q3D Extractor model with visualized eddy-currents on the back-
side.
Compared to commercially-available IGBT and SiC MOSFET modules, for example [193],
an additional stray-inductance of 2 nH due to the measurement is not significant. However,
for the developed, highly-integrated commutation cell with stray inductances lower than
5 nH, this represents a significant difference that will affect switching characteristics. The
relative increase of stray inductance is 45 % for the presented module. Small changes in the
layout of SiC modules lead to significant changes of the switching properties of the module.
Thus, the double-pulse waveforms presented in Section 5.2.3 deviate from the waveforms
of the original power module. The stray inductance of the original power module used in
the converters will be lower causing reduced over-voltages and oscillations.
Such small differences in stray inductance may be neglected for power modules with
higher stray inductance, but significantly influences the overall stray inductance when
designing low-inductive power modules, even with lateral layouts. For 3D-packaged or
PCB-integrated commutation cell designs, the shielding of high-frequency magnetic fields
contributes to sub-1 nH designs [107], [114]. However, parasitic capacitances in such
Table 5.1: Simulated stray inductances of power modules.

module Lσ at 100 MHz % of original module
original module on DBC 4.03 nH 100 %
module on DBC with Ω-tube 4.53 nH 112.4 %
1.55 mm PCB module 6.35 nH 157.6 %
1.55 mm PCB module and 300 µm copper 6.17 nH 153.1 %
1 mm PCB module 5.44 nH 135 %
0.63 mm PCB module 4.66 nH 115.6 %
71
test bench
control
interface
oscilloscope
power test bench

module
module
voltage inductor current

measurement measurement
Figure 5.17: Picture of the double-pulse test setup.
designs must be kept minimal at the same time. Compared to the output capacitances of
the investigated devices of 220 pF, large copper areas create capacitances of similar size
and heavily influence the switching behavior of WBG devices [146], [181].
5.2.1.2 Measurement Setup
The test setup of the power module is shown in Figure 5.17. The module is connected
with the dc voltage and switching node terminals to the test bench on the right. The
voltage measurement for the drain-source and gate-source voltage is located on the left.
The Rogowski coil is inserted into the copper tube and connected to the oscilloscope via a
coaxial cable. The gate voltage supply and the optical fiber cable for the gate driver can
be seen at the top of the power module. A closer view on the power module connected
to the test bench is depicted in Figure 5.18.
The double-pulse test bench uses a LeCroy HDO6104 oscilloscope with a resolution of
12 bit and a bandwidth of 1 GHz with a sample rate of 2.5 GS/s [169]. This corresponds
to one sample point every 400 ps. The gate-source voltage and the drain-source voltage
are measured with PMK BumbleBee ® differential probes with a maximum voltage of +/-
2000 V and a bandwidth of 400 MHz and a differential input capacitance of 2 pF [123]. The
current through the switch is measured with the Rogowski-based current sensor attached
to the oscilloscope via an external 50 Ω termination resistor. The inductor current is
measured using a Keysight N2781B current probe with a maximum current of 150 A and
a bandwidth of 10 MHz [85]. The inductor current is used to match the amplitude of the
Rogowski-coil based current measurement. The current measurement of the Rogowski
coil is only used to measure the current during the switching instants at ton and toff .
72
iD
measurement
uDS uGS
measurement measurement
Figure 5.18: Power module connected in double-pulse test setup.
It is important to deskew the propagation delay between different measurement devices,

especially for the calculation of the power loss [4]. The PMK BumbleBee ® differential
probes have a specified delay of 12 ns. The Rogowski current probe is attached with a
25 cm coaxial cable that has a propagation delay of 1.2 ns, resulting in a difference of
10.8 ns that is accounted for during the evaluation of the test data. A propagation delay
of about 11 ns is also verified experimentally.
5.2.2 Rogowski Coil Current Measurement and Post-Processing

Procedure
Measuring current via a Rogowski air coil is a well known measurement technique [136],
[206]. Due to the its nature of measuring di/dt only, dc currents cannot be measured
and integration of the output signal is required. A high-bandwidth current measurement
based on a Rogowski coil is presented in [59], [68]. The Rogowski coil is placed in a small
Ω-shaped copper tube allowing current measurements with a high bandwidth and a low
insertion stray inductance of only several hundred pH. The Rogowski coil is commercially
available with an integrated analog amplifier and integrator in a shielded housing. The
commercially-available solution has a comparably large footprint on the power module
developed in this thesis. It would require to lengthen the power module by about 2 cm
and would cause an increase of the stray inductance due to the wider geometry. Hence,
an alternative solution is developed that digitally integrates the signal from the Rogowski
coil after the double-pulse measurements and requires no analog circuitry. The required
footprint of this alternative is only the Ω-shaped copper tube and minimizes the increase of
the stray inductance. As any external power supply and additional circuitry are omitted,
73
3D-printed plastic
SMB connector
enameled wire
(a) Rogowski coil receiver (b) Ω-shaped copper tube
Figure 5.19: Manufactured Rogowski coil current probe.
common-mode immunity is also improved as additional components with limited common-

mode rejection ratio are eliminated. The analog signal of the Rogowski coil is directly fed
into the oscilloscope and digitally integrated afterwards in a post-processing procedure.
This requires an oscilloscope with a sufficiently high precision and sample rate.
5.2.2.1 Design of Rogowski coil
The geometric design of the Rogowski coil presented in literature is utilized [59], [68]. The
outer diameter of the Ω-shaped copper tube is 3 mm. Due to the high di/dt of SiC devices,
the number of turns of the receiving coil can be chosen rather low. In this case, the number
of turns is set to five. The prototype is depicted in Figure 5.19. The plastic supporting
structure is made of Polylactic acid (PLA) and is manufactured with an Ultimaker S3
3D-printer. Enameled copper wire and a SubMiniature version B (SMB) connector with
an integrated termination resistor form the electrical part of the design. The result is
a very low-cost measurement device. The SMB connector is directly connected to the
oscilloscope via an SMB cable. The cable is terminated with 50 Ω at the oscilloscope.
The Rogowski coil requires proper termination such that overshoots are avoided for fre-
quencies near its resonant frequency [136]. For the initial determination of the termination
resistor, a simplified, lumped parameter model is shown in Figure 5.20, neglecting the re-
sistance of the coil wire. For high-frequency measurement devices, the lumped parameter
model may eventually be substituted with a distributed model to improve the accuracy
[136].
The model consists of the coil self-inductance Lrog , the parasitic capacitance Crog , and
the termination resistor Rterm . The voltage Urog is the induced voltage of the coupling
inductance caused by a current change di/dt in the copper tube. The second order system is
commonly described with the following transfer function Grog (s) in the Laplace domain:
74
Lrog
Urog Crog Rterm Uout
Figure 5.20: Simplified schematic for Rogowski coil.
x
Figure 5.21: Picture of the Rogowski simulation setup in ANSYS Q3D Extractor .
k
Grog (s) = (5.2)
1
ω0 2
· s2 + 2·ζ
ω0
·s+1
k is the gain of the system, ω0 is the angular frequency and ζ the damping ratio. The
transfer function of the model in Figure 5.20 is given by:
1
Grog (s) = Lrog
(5.3)
Lrog Crog · s2 + Rterm
·s+1
To determine the damping ratio for a critically damped system (ζ =1), the following is
obtained with Equation (5.2) and Equation (5.3):
k=1
1
Lrog Crog =
ω0 2
Lrog 2·ζ
= (5.4)
Rterm ω0
An ANSYS Q3D Extractor model of the Rogowski coil is created to determine the values
75
600 120 15
uDS
500 100 10
iD,shunt
Voltage in V
Voltage in V
400 80
Current in A
5
300 60
0
200 40
-5
100 20
0 0 -10
-15
0 100 200 300 400 500 0 100 200 300 400 500
(a) Measured drain-source voltage and current (b) Measured Rogowski coil signal
Figure 5.22: Double-pulse waveforms.
for the inductance Lrog and the capacitance Crog . The model of the coil is depicted
in Figure 5.21. The simulation gives Lrog = 39.4 nH and Crog = 0.417 pF at 100 MHz.
Accordingly, the angular frequency ω0 of the system is 7.8016 × 109 rad/s. To achieve a
damping ratio ζ of 1, a termination resistor of Rterm,crit = 153.7 Ω is required. The
value is sensitive to variations of Crog , which is a very small parasitic capacitance. During
experimental measurement, a value of 120 Ω for the termination resistor Rterm achieved the
best results. The calculated bandwidth of this idealized system is 567 MHz at −3 dB.
5.2.2.2 Post-Processing Procedure
Due to the usage of a Rogowski coil current measurement, post-processing steps are
necessary to determine the transient current flow during the switching instants. Since
the fundamental waveforms during double-pulse tests are confined and well known, an
automated post-processing algorithm is developed that calculates the current switching
transients from the Rogowski coil signal. The post-processing procedure is outlined before
the actual evaluation and discussion of the measurement results.
The raw data of an exemplary double-pulse test with a dc-link voltage of 400 V and a
current set-point of 50 A is shown in Figure 5.22. The waveforms are recorded with a
sample rate of 2.5 GS/s. Figure 5.22a shows the measured drain-source voltage uDS and
the current measured via a shunt, whereas Figure 5.22b depicts the raw measured voltage
signal of the Rogowski coil. The switching instants are clearly visible with the differential
Rogowski coil signal and stand out of the noise floor. The switch is turned off and on and
off within 20 µs. The maximum measured voltage of the Rogowski coil is about 10 V.
76
104 0
0
-200
-0.5
Integral in Vs
Integral in Vs
-400
-1
-600
-1.5
-800
-2 -1000
0 100 200 300 400 500 0 100 200 300 400 500
(a) Integrated Rogowski signal (b) High-pass filtered integrated Rogowski signal
Figure 5.23: Integration and filtering of measured Rogowski coil signal.
Integrating the Rogowski coil signal via trapezoidal integration results in the waveform
depicted in Figure 5.23a. The recorded signal does not contain white noise only, but incor-
porates an offset error. As a result, a large integration error is accumulated. The actual
switching instants are almost not noticeable. Filtering the raw signal with a high-pass
filter with a frequency of 10 kHz yields the integrated waveform depicted in Figure 5.23b.
The filter frequency is chosen such that the offset error is eliminated but the switching
waveforms of the double-pulse test are ideally not damped. The switching instants at a
time of approximately 250 µs are noticeable. However, there is still low-frequency noise.
In order to remove the remaining noise from the measured signal, an artificial signal is
synthesized. The artificial signal is computed from the Rogowski coil signal where the
values during the switching instants are overridden with the mean value of the noise floor.
The artificial signal is then integrated and subtracted from the integrated Rogowski coil
signal. The result of this procedure is shown in Figure 5.24a. As can be observed, the
remaining low-frequency noise is successfully removed. Especially during the time where
the device under test (DUT) is turned off, where it is known that the current must stay
at zero ampere, a flat current signal is observable. The switching transients including the
reverse-recovery peak during turn-on are clearly recognizable. As a next step, an offset
is applied to the signal such that the value during the turn-off period actually is zero as
depicted in Figure 5.24b.
Finally, the compensated, integrated signal of the Rogowski coil is matched and synchro-
nized with the inductor current right before the first turn-off event and after the turn-on
event. The inductor current can be measured with an external current probe. The probe
does not have to be a high bandwidth measurement device because the high-bandwidth
Rogowski coil measurement is used for the actual switching events. The inductor cur-
rent is only used to determine the current amplitude around the corresponding switching
events.
77
100 300
200
Integral in Vs
Integral in Vs
0
100
-100
0
-200 -100
276 278 280 282 284 286 276 278 280 282 284 286
(a) Compensated Rogowski signal (b) Compensated Rogowski signal with adjusted off-
set
Figure 5.24: Compensated and integrated Rogowski coil signals.
60
80
60
Current in A
Current in A
40
40
20 20
Inductor current iD,rogowski
Synchronization points 0 Synchronization points
0
0 100 200 300 400 500 276 278 280 282 284 286
(a) Inductor current (b) Calculated current waveform with Rogowski coil
Figure 5.25: Synchronization of the current.
Figure 5.25a shows the measured inductor current as well as the chosen synchronization
points. The synchronization points should be chosen as close as possible to the turn-off
and turn-on switching instants. However, for the turn-on event enough margin must be
provided such that all ringing has come to an end as otherwise the synchronization may be
inaccurate. The synchronization points are used to scale the amplitude of the Rogowski
coil-based signal to the inductor current right before and after the switching instants.
As a summary, the digital post-processing procedure works as follows:
1. Determination of the switching instants toff and ton based on the measured, differ-
ential Rogowski signal.
78
adapter
Rogowski
coil
shunt
Figure 5.26: Measurement setup with shunt and Rogowski measurement.
2. Filtering of the Rogowski signal with a high-pass filter of 10 kHz.
3. Subtracting of an artificial signal with the average noise of the Rogowski signal
inserted around toff and ton .
4. Compensating the offset of the integrated signal during the turn-off period of the
device between toff and ton to zero.
5. Scaling of the amplitude of the integrated signal to an externally measured current

amplitude at a time instant right before toff .
The final current waveform for the double-pulse test is shown in Figure 5.25b. The
current waveform is accurately captured during for the first turn-off and the turn-on
event. Before and afterwards, the current is not accurately computed. This is sufficient
for the evaluation of the double-pulse test. Remaining sources of errors are the accuracy
of the current probe that is used to match the current amplitude as well as an imperfect
scaling of the computed Rogowski signal due to noise, which results in a mismatch of the
current amplitude at the two synchronization points.
The presented digital post-processing procedure is a viable option to extract fast switching
transients of double-pulse measurements, but requires much more effort to be usable with
arbitrary waveforms during converter operation.
79
600 120 600 120

uDS uDS
500 100 500 100
iD,rogowski iD,rogowski
Voltage in V
Voltage in V
400 80 400 80
Current in A
Current in A
iD,shunt iD,shunt
300 60 300 60
200 40 200 40
100 20 100 20
0 0 0 0
0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160

Time in ns Time in ns
(a) Turn off (b) Turn on
Figure 5.27: Current waveform comparison with 4.7 Ω turn-on resistor.
5.2.2.3 Comparison to Measurement Based on Coaxial Shunt
For verification purposes of the Rogowski coil design and the post-processing procedure, a
test module is built that incorporates the Rogowski-based current measurement and a cur-
rent measurement based on a coaxial shunt with the T&M Research Products SDN-414-10
as shown by Figure 5.26. Both the Rogowski coil and the shunt are connected in series at
the source potential of the low-side switch as depicted for the current measurement in Fig-
ure 5.14b via an adapter. This allows a direct comparison of the two current measurement
techniques. The shunt has a calibrated resistance of 98.6 Ω and a specified “bandpass”
frequency of 2 GHz [166]. The resulting power module exhibits a higher stray inductance
of approximately 18 nH. Thus, tests are conducted at half of the nominal voltage for
safety reasons due to high over-voltages at turn-off.
The propagation delays for the coaxial cables used for the shunt and the Rogowski coil of
5.05 ns and 1.20 ns are compensated. Two exemplary measured waveform during turn-off
and turn-on are given in Figure 5.27 for RG,on = 4.7 Ω and in Figure 5.28 for RG,on =
2.2 Ω. The current measured and computed via the Rogowski coil is denoted with iD,rog
while the current measured via the shunt is denoted with iD,shunt .
The waveforms show that the computed current waveform is similar to the waveforms
measured via a shunt. The Rogowski coil successfully measures the current rise and
subsequent oscillations during turn-off and turn-on. With the smaller RG,on , the reverse-
recovery current peak increases and causes more voltage ringing afterwards. However, the
Rogowski-based solution does not reach the same measured amplitude of the first current
peak compared to the current measured via the shunt, especially for the reverse-recovery
peak during turn-on. A phase error can be determined as well. The measured values and
calculated errors are summarized in Table 5.2.
80
600 120 600 120

uDS uDS
500 100 500 100
Voltage in V
Voltage in V
400 80 400 80
Current in A
Current in A
iD,shunt iD,shunt
300 60 300 60
200 40 200 40
100 20 100 20
0 0 0 0
0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160

Figure 5.28: Current waveform comparison with 2.2 Ω turn-on resistor.
The measured delay between iD,rog and iD,shunt is approximately 1.2 ns. As the sample rate
of the oscilloscope is limited to 2.5 GS/s with a corresponding time resolution of 400 ps, the
value may not be accurate. This delay is especially critical for an accurate measurement
since the switching transients of utilized SiC devices are completed within 20 ns and cause
a large error. The integration boundaries for the switching energies are determined by 5 %
of the power loss peak, which is further explained in Section 5.2.3.1. The relative deviation
between the calculated switching energies is significant with about 20 % to 30 %. When
the delay between the two current waveform is compensated with a constant time delay,
Table 5.2: Calculated errors for shunt and Rogowski-based measurement.

parameter RG,on = 4.7 Ω RG,on = 2.2 Ω
delay ≈1.2 ns
maximum amplitude with iD,rog 87.4 A 99.6 A
maximum amplitude with iD,shunt 91 A 104.5 A
absolute amplitude error 3.6 A 4.9 A
relative amplitude error 3.9 % 4.7 %
turn-on energy Eon with iD,rog 219.6 µJ 144 µJ
turn-on energy Eon with iD,shunt 263.7 µJ 189.3 µJ
absolute error of Eon −44.1 µJ −45.3 µJ
relative error of Eon −20.1 % −31.5 %
turn-off energy Eoff with iD,rog 111.2 µJ 109.4 µJ
turn-off energy Eoff with iD,shunt 73.7 µJ 73.6 µJ
absolute error of Eoff 37.6 µJ 35.8 µJ
relative error of Eoff 33.8 % 32.7 %
81
Magnitude in dB
0
-5
-10
10
Phase in °
0
-10
-20
-30
10-1 100 101 102 103
Frequency in MHz
Figure 5.29: Calculated transfer function of Rogowski coil.
the results are within 5 % deviation from each other as shown in Appendix A.3.3.
Multiple sources of error can cause the observed errors between the measurement methods,
some of which are discussed in the following. Most of the suspected errors can only be
attributed to the shunt and do not apply to the Rogowski coil.
Limited Bandwidth of Rogowski Coil The Rogowski coil has a self-inductance and
parasitic capacitance as shown by Equation (5.3). Hence, the Rogowski acts as a low-pass
at higher frequencies. Figure 5.29 shows the bode plot of transfer function deduced from
the second-order equation for the system in Equation (5.3). It is observable that the low-
pass behavior starts to influence the amplitude of the transfer function at 100 MHz. As
mentioned previously, the bandwidth of the Rogowski coil is 567 MHz at −3 dB. While the
magnitude is still nearly constant up to approximately 100 MHz, the phase decrease starts
at much lower frequencies. A phase of −30° is passed at 222 MHz. When this transfer
function is applied to the current measured via the shunt to take the low-pass behavior
into account, only a minimal effect occurs. The calculated waveform does not match the
waveform measured directly via the Rogowski coil. The low-pass behavior only becomes
dominant at higher frequencies. Hence, the low-pass characteristic of the Rogowski coil
does not influence the measured current yet and cannot explain the differences between
the measured waveforms.
82
Skin and Proximity Effect Since the shunt measurement is a resistive measurement, it
is potentially susceptible to the skin effect [43], [72], [126], [180]. The approximation of
the skin depth δ is calculated with:
r
2 · ρel
δ= (5.5)
ω·µ
ρel is the specific resistivity of the material, ω the angular frequency of the current, and µ
the permeability of the material. The resonant frequency of the module is approximately
69 MHz as determined from Figure 5.27 and Figure 5.28. When utilizing Constantan ®
as the alloy for the shunt, the resulting skin depth δ is only 42.4 µm at a frequency of
69 MHz with ρel,Const. = 0.49 Ω mm2/m and an assumed µr = 1. When using Evanohm ®
with a higher resistivity of ρel,Evan. = 1.35 Ω mm2/m, the result is 70.4 µm. The thickness of
the metal foils used for shunts are in the range of a few µm to 100 µm and depends on the
actual design of the shunt. Consequently, the skin effect can influence the measurement by
increasing the ohmic resistance of the shunt at high frequencies, causing a larger voltage
drop of the shunt and an overestimation of the current. The influences become visible for
SiC or GaN devices with fast switching transients and high resonant frequencies, whereas
it can be neglected for current waveforms of Si IGBT devices with slower current rise
times.
The utilized shunt in this setup is further examined and decomposed to measure the
geometric design. Pictures are given in Appendix A.3.1. The resistance alloy foil is
measured to have a thickness between 15 µm and 20 µm, which is determined with an
optical microscope. The calibrated resistance of the shunt requires a resistance alloy with
a high resistivity due to the geometry, for example Evanohm ® . The thickness of the metal
foil is well below the calculated skin depth and the skin effect cannot have a significant
influence with this material. The skin effect only becomes significant at frequencies greater
than 1 GHz, where the calculated skin depth is 18.49 µm.
To further validate this and to include proximity effects, an ANSYS 2D Extractor model
of the coaxial structure is created and simulated. The model is depicted in Figure 5.30a.
The result of the simulation is given in Figure 5.30b. The resistance values is scaled to
the length of the shunt of 15 mm.
The resistance only increases slightly for frequencies below 1 GHz. At 100 MHz, the
increase in ac resistance is only 1.49 %, which does not explain the full difference between
the two current measurements. Furthermore, an increase in ac resistance does not explain
the observed phase error between the measurements. The skin effect and proximity do
not significantly influence the resistance of this specific shunt with a very thin resistance
foil, but may influence the results when other shunt geometries with thicker resistance
foils are used.
83
y
resistive
foil
0.12
0.115
Resistance in
x 0.11
0.105
0.1
10-1 100 101 102 103
brass tube insulator Frequency in MHz
(a) 2D simulation model (b) Simulated ac resistance
Figure 5.30: ANSYS 2D Extractor simulation.
Damping of the Coaxial Cables Coaxial cables exhibit a damping ratio especially at
higher frequencies and form a low-pass filter. The effects of the coaxial cable are not taken
into account with the presented waveforms, but the cable are kept short to minimize these
effects. A coaxial cable acting as a low-pass filter can explain the phase delay and the
lower amplitude between the measurements.
The cable length for the Rogowski is kept short to 25 cm to minimize influences of the
cable on the measurement signal. While the utilized RG316 cable has higher attenuation
compared to other types, the influence is only 0.07 dB at 100 MHz [57] due to the short
length. Since iD,rog lags behind iD,shunt , the Rogowski coil must be dampened in this case.
However, the coaxial cable utilized for the shunt measurement is longer than the one used
for the Rogowski coil. The shunt is connected via a RG58 coaxial cable with a length of
1 m. The resulting attenuation is 0.17 dB at 100 MHz [57], which is actually higher than
the attenuation of the cable used for the Rogowski coil.
Hence, the difference between the measured waveforms cannot be caused by the low-pass
characteristic of the cable used for the Rogowski coil. Nevertheless, the damping effects
of the coaxial cable should be taken into account in future measurements for higher
frequencies in the range of several hundred MHz as they start to influence the measured
signals. Better coaxial cables with lower attenuation should also be used in the future.
Parasitic Elements of the Shunt Coaxial shunts are designed such that the measure-
ment connection is located in the field-free region of the cylindrical geometry where the
electromagnetic field is canceled out by the opposite direction of the current flow at the
inner and outer cylinders. This enables a purely resistive measurement and shunts with
a very high bandwidth. A cross section of a coaxial shunt including the current flow
84
measurement z z
connector
insulator
resistive
foil
brass
tube
ishunt x y
(a) Cross section with added current flow (b) 3D simulation model
Figure 5.31: ANSYS Q3D Extractor model of coaxial shunt.
direction is given in Figure 5.31a. However, there are effects that limit the bandwidth
such as the propagation of the waves through the shunt [43]. Parasitic elements also oc-
cur within the shunt. The nested cylindrical tubes in close proximity in the shunt create
parasitic capacitances. The boundaries of the cylindrical geometry can cause magnetic
flux to be enclosed by the measuring loop. The placement of the shunt in an area with
external magnetic fields may also influence the measurement. The result is an inductive
component in the measurement path of the shunt. To examine some of these parasitic
elements, an ANSYS Q3D Extractor model of the shunt is created. The model is depicted
in Figure 5.31b.
The transfer function calculated from the extracted S-Parameters of the model is depicted
in Figure 5.32. There is a clear inductive behavior with a phase increase observable at
frequencies starting at approximately 10 MHz. The specified “bandpass” frequency of
2 GHz of the shunt can be read of the −3 dB point of the transfer function. The transfer
function has the characteristics of an under-damped system and the actual bandwidth of
the shunt is lower. The +3 dB point is located at 859 MHz.
Additionally, the shunt is analyzed with a Tektronix TTR506A vector network analyzer
(VNA) as a two-port network. Port 1 is the BNC port of the shunt where the sense
wire is attached and port 2 is the input port for the drain current iD . The VNA is
calibrated such that all influences of cables, adapters and connectors are eliminated. The
result of the Z-Parameter Z12 , which describes the impedance of port 2 to 1 with open
85
0.14
Impedance in
0.12
0.1
0.08
20
Phase in °
-20
100 101 102 103
Frequency in MHz
Figure 5.32: Simulated transfer function of the shunt.
1
Z12 parameter of shunt
0.8
Impedance in
Approximated transfer function

0.6
0.4
0.2
80
Phase in °
60
40
20
0
-20
100 101 102 103
Frequency in MHz
Figure 5.33: Transfer function of the shunt.
86
terminals, e.g. the transfer function of the current at port 2 to the voltage in port 1,
is depicted in Figure 5.33. An inductive behavior is observable starting at much lower
frequencies than simulated with extracted parameters of ANSYS Q3D Extractor . The
measured magnitudes are significantly higher than the simulated ones. For example, the
maximum magnitude of 0.144 V simulated at 1.05 GHz is already reached at 141 MHz
with the measurement and steadily increases towards higher frequencies. More details on
the VNA measurement are given in Appendix A.3.2.
The transfer function is dominated by an inductive component up to frequencies of ap-

proximately 200 MHz before smaller resonances are visible. As the oscillations of the
measured currents during the double-pulse test occur below 100 MHz, a simple transfer
function with an inductive component only is applied. The transfer function of the shunt
Gshunt (s) in the Laplace domain is given with:
Gshunt (s) = Rshunt + s · Lshunt (5.6)
Rshunt is the calibrated resistance of the shunt and Lshunt the parasitic coupling inductance.
This parasitic inductance of the coaxial shunt is not caused by its self-inductance. Instead,
it is the coupling inductance of the current to the sensing wires [206]. The simplified
transfer function Gshunt (s) assumes a constant current and, thus, neglects the increase of
the resistance due to the skin and proximity effects as outlined by Figure 5.30b. The
bode plot of simplified transfer function is depicted in Figure 5.33 with Rshunt = 98.6 mΩ
and Lshunt = 0.15 nH. The latter is determined empirically. The coupling inductance
in the transfer function is approximately larger by a factor of six compared to the one
obtained from ANSYS Q3D Extractor . The simplified transfer function closely follows
the amplitude of Z12 up to a frequency of 100 MHz. At higher frequencies, the measured
inductive component is slightly lower than with the assumed transfer function Gshunt (s).
Above 1 GHz, the measured amplitude exceeds the amplitude of transfer function Gshunt (s)
again. The phase differs already at lower frequencies compared to the measured parameter
Z12 . At 69 MHz, the phase difference is 11.9°.
Correcting the measurement by applying the inverse of this simplified transfer function
Gshunt (s)−1 to the previously shown current waveform of the shunt iD,shunt , the corrected
current waveform iD,shunt,corrected is obtained, depicted in Figure 5.34 and Figure 5.35. The
corrected waveform closely follows the measured current measured via the Rogowski coil.
Hence, the shunt does have an inductive coupling that is not resembled by the ANSYS
Q3D Extractor simulation, but can be measured. Likely reasons for this behavior are wave
characteristics, e.g. wave propagation [43], that are responsible for this behavior, which
are not resembled by the quasi-static simulation of ANSYS Q3D Extractor [90]. This
demonstrates that the measurement of WBG power electronics is slowly moving towards
radio-frequency engineering. Lumped models are not suitable anymore and distributed
elements must be considered.
87
120 120
100 100
iD,shunt iD,shunt
80 80
Current in A
Current in A
iD,shunt,corrected iD,shunt,corrected
60 60
40 40
20 20
0 0
0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160

Figure 5.34: Waveform comparison between Rogowski and shunt-based measurement

with 4.7 Ω turn-on resistor.
120 120
iD,rogowski
100 100
iD,shunt
80 80
Current in A
Current in A
iD,shunt,corrected
60 60
40 40
iD,rogowski
20 20
iD,shunt
0 0 iD,shunt,corrected
0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160
Figure 5.35: Waveform comparison between Rogowski and shunt-based measurement

with 2.2 Ω turn-on resistor.
Consequently, it can be stated that the coupling inductance within the measurement path
of the coaxial shunt, even if it is as small as the 0.15 nH of the simplified transfer function
of the shunt, is fatal for the usage of shunts with WBG devices. In addition to the high
insertion inductance of shunts that significantly alters the module layout characteristics,
the measured signals give false measurements due to the inductive coupling. While this
effect is probably negligible for Si devices with longer and slower switching transients,
it causes significant deviations during the fast switching transients of WBG and high-
frequency oscillations.
88
The transfer function of the shunt can be compensated to obtain more realistic measure-
ments, but this requires detailed knowledge of the shunt characteristics. The character-
istics can be retrieved by measurements with e.g. a VNA to obtain the S-Parameters
of the shunt. While the inverse of the simple transfer function Gshunt (s) with an induc-
tive component is sufficient for the presented use-case, more sophisticated compensations
methods based on the S-Parameters must be used in the future to correct the measured
signal when a shunt is used.
The differences between the current measured via shunt iD,shunt and via Rogowski coil
iD,rog can be attributed to the inductive coupling within the shunt. Additionally, it is
possible to deduce iD,rog from iD,shunt by inverting the derived transfer function of the
shunt. Hence, the measurement method via the passive Rogowski coil with a digital post-
processing procedure is deemed to be accurate or at least more realistic for double-pulse
measurement of WBG devices. Therefore, it is used during all following double-pulse
measurements, but it has to be kept in mind that also the Rogowski coil exhibits a phase
delay at frequencies above 10 MHz that influence the measurements.
89
1000 125
Voltage in V
Current in A
800 uDS 100
600 iD 75
400 50
200 25
0 0
0 10 20 30 40 50 60 70 80 90 100
Voltage in V
20
10
0
uGS
-10
0 10 20 30 40 50 60 70 80 90 100
Time in ns
Figure 5.36: Turn-on waveforms at 65.2 A and 4.7 Ω turn-on resistor.
5.2.3 Measurement Results
In this section, the measurement results conducted with the PCB-based power module
are presented. The post-processing procedure presented in Section 5.2.2 is utilized to
determine the transient current flow during the switching instants. The turn-on resistor
is varied with values of 0 Ω, 2.2 Ω and 4.7 Ω. The turn-off resistor is fixed to 0 Ω as
in the original module. The measurements are conducted at room temperature. The
measurement uncertainty experimentally determined at a voltage of 800 V and a current
set point of 50 A is 2 % for the turn-off energy and 1.2 % for the turn-on switching energy.
5.2.3.1 Waveforms
Figure 5.36 shows the turn-on waveform for a double-pulse test with a voltage 800 V
and a current 65.2 A with a turn-on resistor of 4.7 Ω. The total switching action within
the channel of the device is completed within 20 ns. The maximum measured voltage
transient is 52 V/ns. The voltage transient measured from 10 % to 90 % is 37.4 V/ns. The
current peak during turn-on reaches 101.8 A with the reverse-recovery of the high-side
body-diode. The maximum di/dt is measured to 8.97 A/ns. The di/dt measured from 10 % to
90 % of the total current slope is 5.96 A/ns. At the time of the maximum di/dt, the voltage
drop is 62 V. With the fundamental equation of an inductance Lσ :
90
1000 100
Voltage in V
Current in A
800 uDS 80
600 iD 60
400 40
200 20
0 0
0 10 20 30 40 50 60 70 80 90 100
Voltage in V
20 u
GS
10
0
-10
0 10 20 30 40 50 60 70 80 90 100
Time in ns
Figure 5.37: Turn-off waveforms at 79 A and 4.7 Ω turn-on resistor.
uL = Lσ · di/dt (5.7)
the corresponding stray inductance is evaluated to 8.14 nH. As the simulated stray in-
ductance of this module is 6.35 nH, this is an increase of 28.2 %. The stray inductance
of the capacitors must also be taken into account for the evaluation of the total stray
inductance of the module. The datasheet gives 3 nH for one single capacitor [39]. As four
capacitors are connected in parallel, the effective value is lower, although they are located
at different positions within the module with different stray inductances.
Figure 5.37 shows the turn-off waveform of the same test with a current of 79.0 A. The
voltage transient measured from 10 % to 90 % is 81.9 V/ns. The maximum over-voltage is
144 V despite a very steep maximum voltage slope of 106 V/ns. Hence, the module can
be safely operated at 800 V even at the steepest voltage slope as the voltage stays well
below the rated voltage of the device of 1200 V. As the stray inductance is even lower in
the original module, the voltage overshoot will be smaller. The resonant frequency fres of
the power module is calculated to 118.6 MHz. With the total parasitic capacitance Cpar ,
comprised of the device capacitance Coss of 220 pF and the switching node capacitance
CSW of 11 pF, the stray inductance calculates to 7.8 nH according to:
1
fres = p (5.8)
2π · Lσ Cpar
91
80 40
Instantaneous Instantaneous
power loss 30 power loss
60
Power in kW
Power in kW
Integration Integration
boundaries 20 boundaries
40
10
20
0
0
-10
0 20 40 60 80 100 0 20 40 60 80 100
(a) Turn on (b) Turn off
Figure 5.38: Instantaneous power with 4.7 Ω turn-on resistor.
This is a slightly higher value than calculated via the stray inductance during turn-on.
Comparing this to the simulation of PCB module in Section 5.2.1.1, this is an increase of
1.45 nH. The difference is attributed again to the stray inductance of the capacitors. Ex-
trapolating this to the original DBC module with a simulated stray inductance of 4.03 nH,
the total stray inductance of the module including the capacitors will be 5.48 nH.
The current and voltage waveform significantly overlap, indicating that the parasitic ca-
pacitance has a significant influence on the switching behavior [46]. If the device capac-
itance is large enough to overtake the whole current during the switching, the turn-off
would be intrinsically soft-switched [98]. However, the capacitance will be discharged
into the device during a hard-switched turn on. As a small gate-plateau is recognizable
between 50 ns and 60 ns, the device is limited by the internal gate resistance and is not
entirely soft-switched with a current of 79.0 A. Since only the internal resistance of 1.1 Ω
and the gate drivers internal impedance are used, the device itself is the limiting factor.
The voltage ringing of the gate-source voltage uGS is a coupled interference. Depending on
how the cable to the voltage probe has been designed and positioned during the double-
pulse measurement, the amplitude of the ringing has significantly changed. In extreme
cases, the voltage ringing has been measured so large that a parasitic turn-on must have
occurred, which has not been the case.
The calculated power loss during the switching instants are depicted in Figure 5.38. The
power loss during turn-on reaches 65.6 kW. The switching energy during turn-on is cal-
culated to 950 µJ. The switching energy during turn-off is calculated to 313 µJ.
The power loss is calculated from 5 % to 5 % of the maximum power peak. The integration
boundaries are depicted in Figure 5.38. Existing norms determine the integration bound-
aries for the switching energies based on thresholds of the current iD and the voltage uDS
for MOSFETs [61] or additionally the gate-emitter voltage for IGBTs [62]. The reason to
92
1000 150
Voltage in V
Current in A
800 uDS 120
600 iD 90
400 60
200 30
0 0
0 10 20 30 40 50 60 70 80 90 100
Voltage in V
20
10
0
uGS
-10
0 10 20 30 40 50 60 70 80 90 100
Time in ns
Figure 5.39: Turn-on waveforms at 65 A and 0.0 Ω turn-on resistor.
deviate from these established calculations is visible in the depicted instantaneous power
loss during the turn-off of the device. Due to the large oscillations of the drain-source
voltage uDS and the current iD , the calculated power loss exhibits large oscillations after
the channel of the MOSFET has turned off. While it is a damped oscillation dissipating
power that is neglected with this metric, it is mostly oscillating energy between the par-
asitic capacitance Cpar and the stray inductance Lσ of the module, i.e. reactive power.
Choosing an integral boundary for the switching energies based on other values than the
power slope itself can lead to a chosen boundary at the peak of the oscillation. This
in turn will cause a large calculation error as part of the reactive power is incorrectly
determined as a part of the switching energies. Additionally, imperfect deskewing of the
propagation delays of the measurement probes can lead to errors for the calculation.
Figure 5.39 shows the turn-on waveform for a double-pulse test at the same settings as
before, but without any additional turn-on resistor. The maximum di/dt reaches 16.74 A/ns,
which is approximately twice the speed as with a turn-on resistor of 4.7 Ω. The di/dt from
10 % to 90 % reaches 10.4 A/ns, which is also approximately twice. The current peak
125.9 A, which is an increase of more than 25 %. The maximum voltage transient is
112.5 V/ns, which is now comparable to the turn-off voltage transient. Meanwhile, the
voltage transient 56.1 V/ns measured from 10 % to 90 % is much lower due to the voltage
drop of Lσ in the beginning, which is taken into account with this metric. The gate-source
voltage uGS rises faster due to the lower turn-on resistance and slightly overshoots up to
2 V or 10 %. While this is still within the absolute maximum rating of the device, it poses
a potential issue for long-term operation. The additional stray inductance of the gate
driver PCB is causing this overshoot and should be minimized in a future design.
93
1000 100
Voltage in V
Current in A
800 uDS 80
600 iD 60
400 40
200 20
0 0
0 10 20 30 40 50 60 70 80 90 100
Voltage in V
20 u
GS
10
0
-10
0 10 20 30 40 50 60 70 80 90 100
Time in ns
Figure 5.40: Turn-off waveforms at 78.6 A and 0.0 Ω turn-on resistor.
The turn-off voltage waveforms depicted in Figure 5.40 remains unchanged compared to
the previous measurement, which is expected since the turn-off event is already carried out
with the internal resistance only. Minor differences are within the margin of error. The
maximum over-voltages during turn-off remain way below the voltage ratings of the device.
This is achieved with fastest current transient above 15 A/ns as well as voltage transient
above 100 V/ns. Hence, it can be stated that designs with a stray inductance in the range of
5 nH are sufficient to safely handle fast switching SiC devices. The stray inductance has to
be related to the number of paralleled devices and to the device current as the over-voltage
scales with the load current. However, the used device with a nominal dc load current
98 A is already utilized quite efficiently during the presented measurements. For paralleled
devices it must be ensured that the stray inductance per device and current remains
within the same range. Paralleling SiC devices additionally requires careful attention to
the balancing between the devices [101]. As the switching transients will likely be chosen
to be lower in commercial designs based on SiC devices, the shown effects, e.g. the voltage
overshoot and ringing, will be even less distinct. Especially in inverter applications, the
switching transients must be slowed down due to possible damage to windings [52], [53]
as well as EMI issues [118].
The power loss for the measurement with 0 Ω external resistance is depicted in Figure 5.41.
The calculated turn-off switching energy is 319.3 µJ, which is approximately the same
value as in the previous double-pulse measurement. The calculated turn-on switching
energy is 475.9 µJ. This is a significant reduction of 50 % compared to the measurement
with a 4.7 Ω turn-on resistor, but which is expected since the di/dt doubled. As the turn-
on switching losses are dominant in hard-switched, fast-switching SiC converters, the
94
80 40
Instantaneous Instantaneous
power loss 30 power loss
60
Power in kW
Power in kW
Integration Integration
boundaries 20 boundaries
40
10
20
0
0
-10
0 20 40 60 80 100 0 20 40 60 80 100
(a) Turn on (b) Turn off
Figure 5.41: Instantaneous power with 0.0 Ω turn-on resistor.
outcome on the efficiency of the converter and the temperature of the device will be quite
beneficial. Comparing Figure 5.41 to Figure 5.38, it is evident that the turn-on transition
is finished faster. The power peak is lower with 61 kW and the time is almost halved
compared to the turn-on transition with an additional 4.7 Ω resistor. However, this only
explains the lower switching energy partially. Another reason for the reduced switching
energy is the higher voltage drop of the stray inductance due to the higher di/dt. Hence,
the voltage applied across the switch is lower and causes a reduced switching energy as
well. This effect has already been observed in [38].
5.2.3.2 Comparison and Evaluation of the Results
The measurements of the prototype with different turn-on resistors of 0 Ω, 2.2 Ω and 4.7 Ω
are compared at room temperature of 25 °C at different currents. Figure 5.42 depicts the
turn-off switching energies Eoff . Since only the turn-on resistor is changed, all three
prototypes behave the same regarding their turn-off. Differences are within the margin of
error. Up to a current of approximately 40 A, the increase of turn-off energies per current
is slightly lower than in the subsequent measurement points. This is due to the already
mentioned parasitic capacitance of the device and the module that is charged during turn-
off. According to the datasheet, the stored energy Eoss in the device capacitance Coss is
about 80 µJ at 800 V [192]. Therefore, the measured turn-off switching energies consist
almost entirely of the energy in Coss at lower currents. As these energies are not real
switching energy during turn-off but stored energy, they should be attributed to the turn-
on energy for hard-switched applications because the capacitance is discharged into the
device at this point. In soft-switched applications, this energy is recovered minus ohmic
and dielectric losses. Up to currents of approximately 40 A, the turn-off is intrinsically
soft-switched. This is shown by the additional waveforms depicted in Appendix A.4.1
95
350
0
300
Turn-off energy in µJ
250
200
150
100
50
10 20 30 40 50 60 70 80
Current in A
Figure 5.42: Comparison of turn-off switching energies with different turn-on resistors.
Turn-off maximum dv/dt in V/ns
Turn-off 10-90% dv/dt in V/ns
120
0 0
80
100
80 60
60 40
40
20
20
20 40 60 80 20 40 60 80
Current in A Current in A
(a) Maximum (b) from 10 % to 90 %
Figure 5.43: Comparison of turn-off dv/dt.
where no gate plateau is visible during turn-off.
The capacitive behavior is also visible in the voltage transients dv/dt depicted in Fig-
ure 5.43. Up to a current of 40 A, the maximum and average dv/dt increases linearly with
the current. In this region, the output capacitance Coss is charged faster with increas-
ing current. Going to currents above 40 A, the maximum and average dv/dt increase per
current starts to flatten and saturates. The gate driver is not able to discharge the Miller-
capacitance CGD because of the internal resistance of the device, limiting a quicker voltage
96
Turn-off maximum di/dt in A/ns
Turn-off 10-90% di/dt in A/ns

12 6
0 0
10
8 4
6
4 2
2
0 0
20 40 60 80 20 40 60 80
Figure 5.44: Comparison of turn-off di/dt.
increase. Consequently, the device is operated in the saturation region, but only with a
fraction of the load current iD as the capacitance is still charged during this transition.
When this behavior dominates, the device is actively controlled by the gate driver and
switched like Si IGBTs albeit an order of magnitude faster.
Figure 5.44 shows the determined current transients di/dt during the test. The average di/dt
determined from 10 % to 90 % is approximately half of the maximum di/dt. The average
di/dt rises linearly with the current and is not actively controlled by the device. It is again
the result of the parasitic capacitance Cpar being charged. As the device capacitance
Coss cannot be changed, there is only limited opportunities to influence this behavior by
changing the ac switching node capacitance CSW . The stray inductance of the power
module is not the limiting factor. At a dc voltage of 800 V the stray inductance must be
greater than 60 nH to become the bottleneck during switching.
The calculated turn-on switching energies Eon are depicted in Figure 5.45. They rise
linearly with the load current iD as expected. The datasheet specifies 1400 µJ for Eon
[192] at 800 V with a current of 50 A and a gate resistor of 2.5 Ω. The measured switching
energy of the prototype is significantly lower, even for the turn-on at approximately 65 A
and a resistor of 4.7 Ω. The results confirm the conclusions of the comparison of the
two waveforms in the previous section. A turn-on resistor of 2.2 Ω reduces the switching
energy by approximately 30 % compared to 4.7 Ω. Removing the external turn-on resistor
completely, a reduction of Eon of approximately 50 % is achieved at higher load currents.
The turn-on energies are approximately twice the amount than the turn-off energies at
the same current with no external gate resistors. When designing hard-switched convert-
ers aiming for highest power densities, a reduction of Eon will significantly improve the
efficiency. While the turn-on switching energies including the turn-off energy are reduced
considerably compared to datasheet values, the switching energies are still in the range of
1 mJ at higher currents. When aiming at switching frequencies in the range of 300 kHz,
97
1000
0 Ohm
2.2 Ohm
800 4.7 Ohm
Turn-on losses in µJ
600
400
200
0
0 10 20 30 40 50 60 70
Current in A
Figure 5.45: Comparison of turn-on switching energies with different turn-on resistors.
Turn-on maximum dv/dt in V/ns
Turn-on 10-90% dv/dt in V/ns
120 80
0
70 2.2
100 4.7
60
80
50
60 0
2.2 40
4.7
40 30
0 20 40 60 0 20 40 60
Figure 5.46: Comparison of turn-on dv/dt.
the switching losses will sum up to about 300 W. This does not yet consider any additional
conduction losses.
The voltage transients dv/dt are given in Figure 5.46 for the turn-on. The maximum
measured voltage transient is constant at a given turn-on resistor. The turn-on switching
is actively controlled by the device and the gate-driver. This is a major difference to the
turn-off transition, where the parasitic capacitance Cpar largely dominates the switching
behavior [46]. Maximum voltage transients above 100 V/ns are achieved. The average dv/dt
98
Turn-on maximum di/dt in A/ns
Turn-on 10-90% di/dt in A/ns

20 12
0 0
2.2 10 2.2
4.7 4.7
15 8
6
10
4
2
5
0
0 20 40 60 0 20 40 60
Figure 5.47: Comparison of turn-on di/dt.
measured from 10 % to 90 % drops with an increasing current. This is because of the

larger voltage drop caused by the stray inductance Lσ and the higher current transient
di/dt, which is taken into account with the metric measured from 10 % to 90 %.
The current transient di/dt during turn-on is depicted in Figure 5.47. The different turn-on
resistors are able to manipulate the current transient. Despite that the voltage transient
is controlled at turn-on and kept constant, the current transient increases with the load
current iD . As the load current increases, the reverse-recovery peak of the body-diode rises
with the load current. The achieved di/dt is higher than the di/dt during turn-off because
the current during turn-on is the sum of the load current and the reverse-recovery current
of the complementary body-diode.
Figure 5.48a shows the maximum over-voltages during turn-off of the MOSFET. As men-
tioned previously, the maximum over-voltage is 144 V. Extrapolating this linearly to the
maximum dc load current of the device of 98 A, the over-voltage would still be at a rea-
sonable level below 200 V. The previously shown high di/dt during turn-on may be relevant
for the voltage across the body-diode of the complementary switch, which must also not
exceed the rated voltage of the device. Due to stray inductance and the large di/dt, it will
exhibit an over-voltage during its turn-off, i.e. when the complementary switch turns-on,
that may be even higher than the over-voltage of the MOSFETs [38]. The voltage across
the body-diode of the high-side switch cannot be measured during the same double-pulse
test because all channels of the oscilloscope of the test bench are already in use. Hence,
the voltage across the diodes are measured during a different test run. The voltage across
the diode is measured instead of uGS during these tests. The results are depicted in
Figure A.34. The over-voltage across the diode is in the same range as the measured
over-voltage during turn-off.
99
Turn-on maximum current in A

140
Turn-off over-voltage in V
0 0
150 120 2.2
4.7
100
100 80
60
50 40
20
20 40 60 80 0 20 40 60
(a) Over-voltage during turn-off (b) Current peak during turn-on
Figure 5.48: Comparison of maximum values.
Figure 5.48b shows the maximum current peak that is measured during the turn-on transi-
tion, which increases linearly with the load current iD . The body-diodes of the MOSFETs
contribute significantly to the turn-on energies, contrary to SiC SBD. With a 0.0 Ω turn-
on resistor, the current peak is twice the load current at 65 A, with the ratio becoming
higher going to lower load currents.
Additional measurement results of the prototype with a 2.2 Ω turn-on resistor at different
voltages can be found in Appendix A.4. The detailed investigation on the transient behav-
ior demonstrate the capabilities of the designed package. A safe operation is maintained
while achieving fastest switching transients for lowest switching losses.
100
5.3 Summary
5.3 Summary
In this chapter, a low-inductive power module with integrated dc-link capacitors and gate
drivers has been designed and tested in detail. Due to the optimization for a very high-
frequency dc-dc converter, the total dc-link capacitance of the power converter has been
integrated into the module. The low-inductive design has been achieved on a conventional
lateral layout and conventional manufacturing techniques can be used to build the power
module. The stray inductances and the parasitic capacitances of the design have been
evaluated based on simulations and static measurements. The stray inductance of the
power loop of the module is 4 nH. The total stray inductance including the additional
inductance of the dc-link capacitors is 5.5 nH.
For the detailed transient analysis of power module, double-pulse tests have been con-
ducted with a separate PCB-based module. With the detailed analysis of this module, it
has been shown that even smallest deviations from the original layout result in significant
changes of the parasitic properties when testing low-inductive power modules with fast SiC
devices. The low-inductive and accurate current measurement in the highly-integrated
power module has been carried out with a Rogowski coil approach. As the Rogowski
coil is only able to measure the current derivative, a digital post-processing procedure
has been developed that is able to accurately compute the current waveform during a
double-pulse test. The presented procedure allows using a low-cost and small device as a
high-bandwidth current sensor for these tests. It has further been revealed that double-
pulse measurements based on coaxial shunts are problematic not only because of their
large insertion inductance, but that the bandwidth of the shunt is insufficient due to an
inductive component within the measurement path. Measurement errors of the switching
energies greater than 20 % have been determined from measurement results obtained with
coaxial shunts.
The capabilities of the power module have been demonstrated with a detailed transient
analysis with the double-pulse tests. Fastest switching transients have been achieved while
maintaining a safe operation of the devices. Due to the optimization and high level of
integration, excellent electrical properties are achieved that enable a high-frequency oper-
ation with steepest current and voltage transients of 15 A/ns and 100 V/ns. Low switching
energies are achieved at 800 V in the range of 320 µJ during turn-off at 79 A and 476 µJ
during turn-on at a current of 65 A. Furthermore, the tests demonstrate that a stray
inductance of approximately 5 nH is sufficient for the safe operation of SiC devices at the
tested voltage and current ratings. A further reduction of the stray inductance does not
yield any benefits for the devices as over-voltages are at a safe level and oscillations are
minimized. The devices are electrically utilized to their full potential as only the internal
characteristics such as parasitic capacitances and the gate resistance limit the operation
speed. The result is a power module with low switching energies and low over-voltages
combined with an effective cooling structure that enables fast-switching dc-dc converter.
101
102
6 Highly-Integrated DC-DC-Converter
To overcome the limitation of a single, combined dc-link voltage of the battery, the charg-
ing infrastructure and the inverter in the electric drive-train as outlined in Chapter 1,
dc-dc converters are proposed for the integration into a modular drive-train for electric
vehicles [149], [159]. The dc-dc converter allows the decoupling the voltage level such
that the different but optimal voltage levels for each component can be utilized within
the drive-train. This use-case is chosen as the target application for a dc-dc converter
that is presented in this chapter. This use-case requires a bidirectional, galvanically non-
isolated synchronous boost converter that steps up the battery voltage from at least 400 V
to 800 V for the inverter and charging interface. As this converter is an additional compo-
nent compared to conventional drive-trains, the possible gains in system efficiency must
not be outweighed by excessive increases in size and weight and low efficiency of the com-
ponent. Hence, increasing the power density while maintaining a high efficiency is a key
element for such a converter.
The dc-dc converter presented in [149] is used as a reference to benchmark the prototype
presented in this chapter. The dc-dc converter is built using a commercially-available
SiC power module [193] with a switching frequency of 150 kHz. A multi-phase approach
is used to scale the power, resulting in a modular concept. The converter achieves a
volumetric power density of 25.7 kW/l calculated with a box around the converter, which
is already significantly higher than Si-based power converters.
For the converter that is developed in this chapter, the switching frequency is more than
doubled compared to the reference converter with a switching frequency fsw of 333 kHz
under hard-switching conditions. The input and output voltages remain at 400 V and
800 V, respectively. As the device utilization and power density shall be increased, the
Table 6.1: Target application.
Topology Synchronous boost converter

Input voltage Uin 400 V
Output voltage Uout 800 V
Power rating PNom 20 kW
Switching frequency fsw 333 kHz
103
SH
iL
L
Cout Uout
Uin Cin SL
Figure 6.1: Schematic of synchronous boost converter
power level of a single-phase dc-dc converter is targeted to be 20 kW. The specifications

are summarized in Table 6.1.
The developed synchronous boost converter is based on the application-specific power

module with an integrated cooling structure. Additional components are investigated
that complement the power module for a high-frequency dc-dc converter. Efficiency and
EMI measurements are conducted for the evaluation of the converter.
6.1 Component Design
The required main components for the synchronous boost converter are briefly investigated
in the following as depicted in the schematic in Figure 6.1. A high-frequency inductor
for the inductance L is designed and the input and output capacitors Cin and Cout are
outlined. The sensing circuit for the current through the inductor iL and the voltages
Uin and Uout and the control circuitry for the switches SL and SH are added to form a
complete converter system.
6.1.1 Inductor
Besides the commutation cell design with the active devices, magnetics are one of the
most critical components in power electronic converters. Volume and weight of magnetics
greatly benefit from increased switching frequencies. But a higher switching frequency
also imposes challenges on the design of magnetics regarding their losses and loss densities.
As the focus of this thesis is on the design of the commutation cell of the power module,
the power inductor follows a rather conventional design based on market-available ferrite
cores and litzwire. For further optimization, more sophisticated designs can be utilized
such as planar high-frequency inductors [137], [189]. For the application in a 20 kW
converter as specified in Table 6.1, a high-frequency inductor requires a design with a low
ac resistance and a high resonant frequency is required [108].
104
windings
... ...
6 5 5 6
3 4 4 3
2 1 1 2
ferrite core
(a) Winding order (b) Picture of power inductor
Figure 6.2: Design of inductor prototype.
A high-frequency inductor with an inductance of 30 µH is designed, which limits the

current ripple to about 20 A peak-to-peak during operation at a duty cycle of 50 %. This
is a design choice as a trade-off between inductor size and inductor losses, which increase
with the current ripple amplitude. The inductor is designed for the switching frequency
of 333 kHz of the converter, consisting of 630x0.1 mm litzwire and a PQ5035 core with
3F36 material made by Ferroxcube. Figure 6.2a illustrates the winding technique for one
half of the inductor that ensures low parasitic capacitances and low voltage drops between
each winding for a high resonant frequency. A picture of the resulting inductor is shown
in Figure 6.2b. The bobbin is 3D-printed with PLA and incorporates a spacer around the
air gap to reduce losses in the litzwire caused by fringing flux of the airgap. The total
weight of the inductor is 226 g. The box volume is 0.105 l.
The dc resistance of the inductor is measured to 4.9 mΩ. The series resistance and the
inductance as a function of frequency of the inductor prototypes are plotted in Figure 6.3.
The resonant frequency of the inductor is 11.1 MHz, which is considered high enough for
the operation at a switching frequency of 333 kHz. The resonant frequency of the power
inductor should at least be ten times higher than the switching frequency [108]. For the
last converter prototype, the inductor is potted with ISO-CAST A 765 MI airgap filler
material. While this improves the cooling of the inductor, the influence on the resonant
frequency is significant due to increased parasitic capacitances of the inductor. It drops to
about 6.7 MHz. This is still high enough for the considered application because there is a
factor of approximately 20 between the switching frequency and the resonant frequency.
The ferrite losses are estimated for the operation in a synchronous boost converter based
on [178]. The Steinmetz-parameter are interpolated from datasheet values for the switch-
ing frequency of 333 kHz [44]. The calculated result is 17.5 W. The dc copper losses
are estimated to 11.8 W based on the measured dc resistance and the root mean square
(RMS) value of the triangular current with 20 A peak-to-peak and a dc bias of 50 A. An
analytical approximation of the skin and proximity losses results in 8.0 W of additional
ac copper losses according to [12]. The sum of all estimated losses is 37.3 W.
105
100 12
unpotted
potted
10
80
Inductance in µH
Resistance in k
60
6
40
4
20
2
0 0
1 10
Frequency in MHz
Figure 6.3: Resistance and inductance of the inductors.
6.1.2 Control Circuits and Sensors
For the construction of the synchronous boost converter based on the developed power
module and power inductor, a control board is designed with which a fully functional
converter prototype is assembled. The control board features all necessary components
for the control of the synchronous boost converter. Figure 6.4 shows the PCB control
board of the prototype.
The control board incorporates a Texas Instruments C2000 TMS320F280049M MCU

[63]. The MCU provides the pulse-width modulation (PWM) unit of the dc-dc converter,
which is operated with a dead time of 150 ns. For the current sensor of the inductor current
iL , an Allegro MicroSystems ACS730 Hall sensor and later on an Allegro MicroSystems
ACS733 in its 65 A variant are used. Both are galvanically isolated and have a bandwidth
of 1 MHz. They differ in their package, conducting resistance and required power supply
voltage [1], [2]. The current sensors output an analog voltage that is read with A/D-
converters of the MCU. For the two voltage sensors for Uin and Uout , isolation amplifiers
are utilized that are connected to the A/D-converters of the MCU to provide galvanically
isolated voltage measurements similar to [186]. The control board also features the input
capacitance Cin and the power connectors for the input port. Two more power connectors
are used to connect the power ground connection to the power module and to the power
inductor. The gate drivers of the power module are attached via connectors on the bottom
side of the PCB carrying the supply voltage and logic input.
106
current
measurement
Cin
MCU
voltage measurement
Figure 6.4: Control board of final prototype.
6.1.3 Input and Output Capacitances
The installed input capacitance consists of nine CeraLink™ FlexAssembly FA3 500 V [39]
capacitors for a total capacitance of 27 µF as observable in Figure 6.4. The resulting
voltage ripple is calculated from the oscillating energy due to the magnetization and
demagnetization of the inductance L according to [93], [149]. This process is assumed to
be solely taking place between the inductor and the local capacitor.
2 2 !
∆iL ∆iL
Cin · (Uin 2 − (a · Uin )2 ) = L · iL + − iL − (6.1)
2 2
The coefficient a denotes the percentage of the input voltage after full magnetization.
With the inductor current ripple ∆iL = 20 A and the average inductor current iL = 50 A,
solving a gives 0.99305 or 0.7 % of voltage ripple occurring at the input of the converter.
The output capacitance Cout of the converter is completely formed by the integrated dc-
link capacitance. Four CeraLink™ FlexAssembly FA3 900 V capacitors are deploayed for
a total capacitance of 3 µF [39] .
The calculation of the output voltage ripple is conducted in a similar manner and the
result is 1.55 %. For the output voltage overshoot in case that the converter is shut down
at the peak current, e.g. the complete energy stored in the inductor is discharged into
the output capacitor, the following equation is used [149]:
107
Figure 6.5: Power module for converter prototype 3.
2
2 2
∆iL
Cout (b · Uout ) − Uout = L · iL + (6.2)
2
Solving for the coefficient b gives 1.028 or only 2.8 % of voltage overshoot.
6.2 Converter Prototypes
With the described components, synchronous boost converter prototypes are manufac-
tured. In total, three different types of converters are manufactured at different stages of
development. The differences between the converters are summarized in Table 6.2. Pic-
tures of the prototypes 1 and 2 are given in Figure A.45 and Figure A.46, respectively.
Table 6.2: Converter prototypes.
prototype 1 prototype 2 prototype 3

Turn-on gate resistor 4.7 Ω 2.2 Ω 0.0 Ω
Current sensor ACS730 ACS730 ACS733
Inductor unpotted unpotted potted
108
control and input

measurement capacitors
ICs
gate
drivers
power module inductor with cooler

(a) Schematic representation of the design (b) Assembled converter prototype
Figure 6.6: Converter prototype 3.
The power module used in the final converter, prototype 3, is depicted in Figure 6.5. It
is slightly modified to optimally account for the available space and connectors in the
converter. As a result, the power density of the converter is improved further as the
box volume is reduced. The turn-on gate resistor is completely removed in this module
and only the internal gate resistance of the device of 1.1 Ω remains. Hence, the goal
of utilizing the SiC devices up to their full potential is achieved on the system level as
well. Accelerating the switching transients further is not possible with the utilized SiC
devices.
The converter is designed for smallest dimensions. The schematic representation of the
design is shown in Figure 6.6a. The assembled prototype without case is depicted in
Figure 6.6b. The control board of the converter is located at the top of the design.
Below, the power module is located that is cooled with the milled micro-channel cooling
structure. The inductor is located beside the power module and is cooled via a similar
cooling structure, which is designed for lowest pressure drop as the expected total losses
and heat flux density are much lower. The cooler for the power inductor has very wide
channels and utilizes an Al2 O3 DBC for electrical insulation. The cooler is depicted in
Figure 6.7. The inlet and outlet for the fluid coolant are located at the bottom. Within
the bounding box of this converter, there is still empty space located between the control
board and the power module as the gate drivers do not fill out all of the space. This can
be further improved with redesigned gate drivers that are not aligned perpendicular to
the power module, but for example with a different connection to the power module.
The encased converter is shown in Figure 6.8. The outer dimensions of the box are
60 mm×60 mm×85 mm resulting in a total volume of 0.306 l. The weight of the converter
is 509 g.
109
(a) Cooling structure for (b) DBC for inductor (c) Assembled
inductor cooler cooler inductor cooler
Figure 6.7: Inductor cooler.
60 mm
m
60
m
m
85
Figure 6.8: Enclosed converter prototype.
6.2.1 Device Loss Estimation
To gain a realistic estimation of the power losses in the devices, a simulation program with
integrated circuit emphasis (SPICE) of the synchronous boost converter is carried out.
The model uses the altered SPICE model as shown Appendix A.4.3 and implements a basic
thermal circuit representing the micro-channel cooling structure with a thermal resistance
of 0.39 K/W. The simulation includes the temperature dependency of the devices, losses
in the body-diode during dead time and the switching losses of the MOSFETs based on
the SPICE model. The losses are distinguished between conduction and switching losses
based on the same 5 % threshold of the power peak as used in the double-pulse test. Thus,
the conduction losses can slightly vary due to different power peaks taken into account.
The simulation results are shown in Table 6.3 for the three turn-on gate resistor values
that have also been examined during the double-pulse tests.
110
The total device losses are 384.2 W with no external gate turn-on resistor. The low-side
switch with a switching loss of 251.1 W causes the most significant fraction. There is a
clear imbalance between the conduction losses of 99.9 W and the total switching losses
of 284.3 W, which is almost a ratio of one to three. This is the result of the converter
design for highest switching frequency and power density. Lowering the switching energies
of the devices is key to maintain a high efficiency for this converter. Due to the high
switching frequency, switching losses are the dominant source of losses. Hence, the largest
improvements of the efficiency of the converter are achieved with lowered switching losses.
The high-side exhibits almost no switching losses as it is turned on and off under soft-
switching conditions in boost mode at nominal operations. The inductor current is always
positive and the body-diode of the high-side MOSFET conducts before the MOSFET is
activated for synchronous rectification. The effect of the different turn-on resistor are
predominately reflected in the switching losses of the low-side switch with 251.1 W for
0 Ω, 285.3 W for 2.2 Ω, and 327.3 W for 4.7 Ω. Roughly 30 W to 40 W higher switching
losses are obtained with each step.
This is not crucial in relation to the overall power rating of the converter of 20 kW.
However, when looking at the heat flux density and junction temperature of the low-
side switch, the lowest gate resistance is a key enabler to ensure a safe operation of the
converter. With the modeled thermal resistance of 0.39 K/W, the simulated losses for a
turn-on resistor of 4.7 Ω result in a junction temperature of 171.4 °C. This is just below
the rated operating temperature of 175 °C of the device and leaves no margin for an
increased coolant temperature or slight over-power conditions. This result is calculated
for a coolant temperature of 25 °C and an assumed even distribution of the conduction
losses among the two switches. The simulated losses for a turn-on resistor of 0.0 Ω result
in a junction temperature of 142.4 °C. This provides a margin of more than 30 °C to the
maximum junction temperature. Hence, a low value of gate resistor and the resulting low
switching losses are extremely important to maintain a safe junction temperature of the
low-side switch at full load.
Table 6.3: Simulated converter losses.
turn-on resistor 0Ω 2.2 Ω 4.7 Ω

Total losses 384.2 W 425.53 W 461.75 W
Total switching losses PSW 284.3 W 323.5 W 365.3 W
Total conduction losses PCond 99.9 W 102 W 96.4 W
Low-side switching losses PSW,lowside 251.1 W 285.3 W 327.3 W
High-side switching losses PSW,highside 33.2 W 38.2 W 38 W
111
Differential mode
100 CISPR25 class 1
VLISN in dBµV
80
60
40
20
0.15 1 10 100
Frequency in MHz
Figure 6.9: Differential-mode EMI spectrum of the converter prototype 3.
6.2.2 EMI Measurements
The conducted electromagnetic emissions of the prototype 3 are measured at a light load
of 300 W in boost mode operation with a line impedance stabilization network (LISN).
The setup is not a conformal setup according to the norms, but gives a first impression on
the EMI of the converter. The measured peak values for differential mode are depicted in
Figure 6.9 including the limits of EN 55025/CISPR25 class 1 [41]. The differential mode
disturbances are successfully limited to EN 55025/CISPR25 class 1 limits.
The measured peak values for common mode are depicted in Figure 6.10 including the
limits of EN 55025/CISPR25 class 1. Here, the result of the fast switching transients is
visible. The maximum allowed amplitudes for the frequency range of 150 kHz to 300 kHz
are not exceeded and the switching frequency of 333 kHz is higher. However, all following
limits are exceeded. Especially the limits defined for 5.9 MHz to 6.2 MHz are surpassed by
approximately 20 dB µV. The limits for 76 MHz to 108 MHz are marginally surpassed.
With fast switching transients above 100 V/ns, the electromagnetic compatibility (EMC)
becomes an issue for SiC converters [118]. Additional filters must be incorporated that
will lower the power density. While the power module already features integrated Y-
capacitors, a systematic design for EMC is required in the future to achieve the best
performance in integrated systems. Otherwise, the size of EMI filters will severely impact
the power density of the converters.
112
Common mode
100 CISPR25 class 1
VLISN in dBµV
80
60
40
20
0.15 1 10 100
Frequency in MHz
Figure 6.10: Common-mode EMI spectrum of the converter prototype 3.
6.2.3 Efficiency Measurements
Efficiency measurements are conducted with the three different prototypes in boost mode
operation. The measurements are carried out with a ZES ZIMMER LMG500 power
analyzer [201] with LEM IT 200-S ULTRASTAB current transducers [97] at an input
voltage of 400 V and a fixed duty cycle d of 50 %. Figure 6.11 shows the results of the
efficiency measurements with the calculated maximum measurement errors according to
the manual of the power analyzer.
Converter prototype 1 yields the worst efficiency due to the higher turn-on resistor and the
non-integrated design. Prototype 2 exhibits an increased efficiency of almost 1 percentage
point higher due the lower switching losses. Prototype 3 only increases the efficiency
slightly despite the further reduced gate resistance. An increase of only 0.1 percentage
point is achieved. Compared to prototype 2, prototype 3 is built with an inductor that is
potted with the filler material for better thermal performance. As Figure 6.3 shows, the
potted inductor has a higher ac resistance and lower resonant frequency due to the added
capacitance of the filler material. The parasitic capacitance causes higher losses during
operation in SiC based boost converters [200]. Hence, the lower switching losses are offset
by increased inductor losses.
For prototype 2, a stable operation point at 21 323 kW of output power is achieved.

However, the efficiency measurement is a false measurement as the input current sensor
has been saturating at this power level during the measurement of prototype 2.
113
99.5
Prototype 1
99 Prototype 2
Prototype 3
98.5
Efficiency in %
98
97.5
97
96.5
96
0 5000 10000 15000 20000 25000
Output power in W
Figure 6.11: Measured efficiency of prototypes at Uin = 400 V, fsw = 333 kHz and d =
50 %.
The peak efficiency of prototype 3 is at almost 99 % in the resonant-pole operation at ap-

proximately 2 kW, where the low-side switch is turned on under soft-switching conditions.
At medium load, the efficiency stays over 98 % despite the hard-switched operation and
a high switching frequency of 333 kHz. The peak efficiency of 98.2 % is achieved between
10 kW and 15 kW. The maximum achieved output power is 22 955 W with an efficiency
of 97.79 %. It has to be noted that the output power could not be raised higher as the
utilized voltage source is limited to 60 A of output current at a voltage of 400 V. While
the maximum power has been transferred with the converter repeatedly and stably, the
dropping efficiency indicates that the output power of the converter cannot be raised much
higher. As most of the losses occur in the active low-side MOSFET, the heat flux density
and junction temperature in the device will reach a critical level with the given cooling
structure. The achieved power density at this power level is 75.02 kW/l or 45.10 kW/kg.
Figure 6.12 shows the measured power loss of the final converter prototype 3. The bound-
ary when transitioning from a soft turn-on operation to a hard turn-on operation with
increased switching losses is clearly visible between 2.5 kW and 3 kW. The measured
total losses are 426.1 W at an output power of 20 427 W. Based on the simulations in
Section 6.2.1, the total device losses have been estimated to 384.2 W at nominal power of
20 000 W. The losses of the power inductor have been estimated to 37.3 W in Section 6.1.1.
Hence, the measured power losses is in good agreement with the sum of estimated losses
of 421.5 W for the main components. At the maximum output power, the total power
loss of the converter is over 500 W.
114
600
Prototype 3
500
Power loss in W
400
300
200
100
0
0 5000 10000 15000 20000 25000
Output power in W
Figure 6.12: Measured power loss prototype 3.
6.2.4 Comparison of Converter Prototype
Other converters based SiC devices deploy coupled-inductors to improve the power den-
sity [31], [77] to 20.1 kW/l and 40 kW/l. The switching frequencies are 60 kHz and 90 kHz,
respectively. Even though coupled inductors are utilized that reduce the size of the power
inductors, the developed converter prototype 3 outmatches the power density due to the
higher switching-frequency of the converter. The efficiency of the converter prototype 3
and the converter presented in [77] are in a similar range with 98.1 %.
The converters presented in [186], [188] are designed for a similar power and voltage
rating, but utilize smaller discrete devices with a lower voltage rating of 1000 V. A
two-phase synchronous boost converter design is presented with innovative, optimized
high-frequency inductors based on planar ferrite cores and copper foils as conductors and
3D-printed miniature fluid coolers. Due to the two-phase approach that uses smaller but
double the amount of SiC MOSFETs, the switching frequency can be chosen as high as
400 kHz. At a switching frequency of 450 kHz, the prototype achieves a power density of
98 kW/l, but at a lower efficiency 97.5 % at medium load [187].
The aforementioned SiC converter that serves as a reference achieves a power density
of 25.7 kW/l [149], [159]. The converter uses the same SiC MOSFETs as the converter
presented in this chapter, but deploys them in a commercially-available SiC module. This
water-cooled converter already exhibits an approximately three times higher power density
than similar Si-based converter, e.g. 7.8 kW/l in [18] or 6.2 kW/l in [93]. Compared to this
115
reference converter, the volumetric power density of the developed prototype 3 is tripled
with a volumetric power density of 75 kW/l. The measured efficiency is about the same
and only lower by approximately 0.2 % despite the increase of the switching frequency by
a factor greater than two. This large increase in power density is achieved using the same
SiC devices as in the power module of the reference converter, but with a module layout
that is optimized for this application. Otherwise, the electrical design is very similar
between the reference converter and the converter built for this thesis. Hence, this shows
the advantage of the converter based on the application-specific power module that fully
utilizes the SiC devices. Due to the increased switching frequency, the size of the passive
components is significantly reduced. The power inductor of the reference converter is a
PM62/49 core with a volume of the ferrite of 62 000 mm3 [168]. The power inductor of the
converter prototype 3 is a PQ50/35 core with a volume of the ferrite of 27 800 mm3 [45],
which is less than half the volume of the reference converter. Still, the power inductor
of prototype 3 is the single largest and heaviest component within the converter with a
weight of 226 g, which is 55.6 % of the total weight of the converter. The box volume of
the power inductor accounts for 34.2 % of the total volume of converter prototype 3.
The increased switching frequency is one key element for higher power density of power
electronics converters. With a package that allows the utilization of fast SiC devices to
their full potential such as the presented application-specific power module, a leap in
the power density of power electronic converters is demonstrated. Future improvements
regarding the power density of converters are gained with innovative designs of passive
components such as the aforementioned inductors based on planar ferrite cores and copper
foils as conductors. Another possibility are coupled inductors of multi-phase converters
to reduce the size of power inductors. For a two-phase synchronous boost converter based
on the same application-specific power module, coupled inductors reduce the volume by
20.7 % and the weight by 24 % [51].
116
6.3 Summary
6.3 Summary
In this chapter, components have been designed to form a synchronous boost converter
in combination with the application-specific power module. The components include a
power inductor, sense and control circuits and capacitors. The power inductor follows a
conventional design based on litzwire and achieves a high resonant frequency of 6 MHz.
On the basis of the application-specific power module, a highly-compact synchronous
boost converter has been designed with a volume of 0.306 l. A maximum output power
of 23 kW has been achieved under hard-switching conditions of the SiC devices at a
switching frequency of 333 kHz. Due to the electrically and thermally balanced design
of the power module, a leap in the power density of a power electronic converter is
achieved on a system level. The achieved volumetric power density is 75 kW/l while the
gravimetric power density is 45 kW/kg. The high power density highlights the potentials
of an electrically and thermally optimized, application-specific power module with fully
utilized SiC devices. For the development of electric vehicles and more electric aircrafts,
such modules present a unique opportunity to develop fast switching dc-dc converters
with highest power densities.
Efficiency measurements have been conducted that further demonstrate the advantages
of the converter design based on the integrated power module. At approximately 50 %
load, an efficiency of 98.2 % is achieved despite the design for highest power density. The
maximum efficiency close to 99 % is achieved in quasi-resonant and zero-voltage switching
operation of the converter with a soft turn-on at 2 kW. At maximum power, the efficiency
is at 97.8 %. Hence, it is possible to achieve a high efficiency despite the very high switching
frequency and hard-switched operation due to the utilization of the SiC devices up to their
full potential.
117
118
7 Conclusions and Outlook
The objective of this thesis has been to utilize the full potentials of SiC devices by freeing
the devices of the limitations imposed by the package design. With an optimized pack-
aging, the advantages of SiC devices should be demonstrated with a power electronics
converter on a system level. As the design of power electronic packages is a multi-physics
design optimization, several aspects of the packages have been separately examined during
this thesis.
First, thermal aspects of an integrated package with micro-channel cooling structures

integrated into the baseplate have been investigated. The structures have comparably
large dimensions compared to the ones presented in literature. The structures have been
simulated and analyzed with CFD simulations. Prototypes have verified the thermal
performance of the structure via thermal impedance measurements, showing their low
thermal resistance and a very fast transient response within 1 s to 2 s. The thermal
resistance has been measured to be as low as 0.39 K/W with these structures.
As the fast transient thermal response has been identified as a potential issue for the
lifetime of integrated power modules, thermal buffers have been investigated. Thermal
buffers specifically add thermal capacity to the devices without influencing the thermal
resistance. They dampen thermal cycles and, consequently, enhance the lifetime of power
modules. Simulations based on realistic mission profiles and empirical lifetime models
have been carried out and have showed a manifold increase of lifetime due to the thermal
buffers. For the integrated structure, an increase in lifetime by a factor of four has been
achieved. For conventional module with attached heat sinks, the increase in lifetime is a
factor of six.
The electrical layout of the power module has been designed under the premise of a
conventional lateral DBC layout. The dc-link capacitors and gate drivers have been inte-
grated to the DBC for a design with low stray inductances and low parasitic capacitances.
The stray inductance of the power loop is 4 nH. With the stray inductance of the dc-link
capacitors included, the total stray inductance is 5.5 nH. The transient behavior is inves-
tigated by double-pulse measurements to verify that the maximum performance of the
devices is achieved. The waveforms and various metrics such as the switching losses are
calculated from the double-pulse measurements and verify the low-inductive and low loss
design with fast switching transients.
A low-inductive current measurement based on a Rogowski coil design integrated into
119
commutation cell has been adapted for the transient double-pulse measurement of the in-
tegrated power module. It uses a digital post-processing procedure to calculate the current
during the double-pulse measurements. The accuracy of the developed passive Rogowski
coil with the post-processing procedure has been benchmarked against the established
current measurement based on coaxial shunts and the differences have been investigated.
A difference of the switching energies larger than 20 % has been calculated between the
current measurement with the Rogowski coil and the coaxial shunt. The difference has
been investigated based on simulations and measurements and attributed to an inductive
coupling of the shunt that falsifies the measurements of fast SiC devices.
A synchronous boost converter has been constructed based on the developed, highly-
integrated application-specific power module. A high-frequency inductor and a control
board with the input dc-link capacitors and peripherals such as a MCU and isolated
voltage and current sensors have been designed. In combination with the power module,
the synchronous boost converter has been operated up to full power. The efficiency as well
as EMI have been measured to demonstrate the capabilities and potentials of fully-utilized
SiC devices on a system level.
7.1 Contributions
In the following, the contributions of this thesis are summarized.
Thermal Aspects A low volume cooling structure integrated into the baseplate has
been developed based on micro-channels. Compared to the structures presented in lit-
erature, coarser micro-channels have been investigated that lower the requirements on
the cleanness of the fluid and the maximum particle size in the fluid. Despite the coarser
dimensions, it has been demonstrated that these structures are able to effectively cool SiC
devices with high current densities and high heat flux densities with a single-sided cooling
structure. The cooling structure with its low volume and low thermal resistance are a key
enabler for converters with a high power density. The cooling structure has an extremely
fast transient response due to the low amount of materials and thermal capacity.
Lifetime Thermal buffers insert additional thermal capacity into the design of power
modules without influencing the thermal resistance. They provide a solution to increase
the thermal capacity for highly-integrated cooling structures with low thermal capacity.
The design of the thermal buffers and their influence has been systematically investigated
to achieve a better understanding of their advantages. Simulations of different mission
profiles have highlighted the lifetime improvements of power modules that are optimized
for the actual mission profiles and applications. It has been illustrated how they can be
implemented in future power module designs for power modules with long-lifetime. Even
120
7.1 Contributions
small thermal buffers result in an increased lifetime of power modules by a factor of four
or more. It is a simple yet powerful solution for enhancing lifetime and a cost-effective
alternative to increasing semiconductor die area or other lifetime enhancing techniques.
Thermal buffers provide an additional design parameter to enhance the lifetime of power
modules. They can be used to tailor power modules to the specific lifetime requirements
of the mission profile and applications.
Accuracy of Transient Measurements of WBG Devices In this work, a low-inductive,

completely passive Rogowski coil design has been developed with low volume and low cost.
The measured, derivative signal of the current is integrated in a digital post-processing
procedure. This design is able to accurately measure current transients up to several
100 MHz during double-pulse measurements. The comparison to a current measurement
based on coaxial shunts has revealed that the coaxial shunt suffers from limited bandwidth
due to an inductive coupling of the current to the sensing port. In addition to the large
input impedance of the coaxial shunts, this makes them unsuitable to measure transients
of WBG devices at high frequencies. Double-pulse measurements of WBG devices are
starting to be influenced by wave characteristics and, hence, are slowly moving towards
radio-frequency engineering.
Application-Specific Power Module It has been demonstrated that a low-inductive,

highly-integrated power module can be designed based on a lateral layout and conven-
tional manufacturing techniques by optimizing it for a specific application. Due to the
high switching frequency, the power module integrates the total dc-link capacitance onto
the DBC that minimizes the parasitic inductance of the commutation loop. The to-
tal stray inductance of the power module is approximately 5.5 nH, which includes the
stray inductance of dc-link capacitors. The SiC devices are fully utilized as an external
gate resistor is omitted and the internal characteristics of the devices limit the switching
speed. Switching transients over 100 V/ns and 15 A/ns have been achieved in practice. The
switching transients are dominated by the parasitic capacitances of the SiC devices itself
because influences and effects of the parasitic elements of the packaging are successfully
minimized. At this current and voltage rating, a lower stray inductance is not required
for the devices. Consequently, the semiconductor devices are leveraged to their fullest
potential and provide lowest switching energies.
Power Electronic Converters Several key aspects of the application-specific power mod-
ule achieve the high power density of the power converter. A low thermal resistance allows
the switching frequency of the power converter to be considerably increased. This makes
it possible to integrate the full dc-link capacitor within the half-bridge power module
that creates a low-inductive commutation loop. This low-inductive layout enables the
utilization of the full potential of the SiC devices by switching as fast as possible while
maintaining a safe operation with low over-voltages and oscillations. This results in lower
121
switching losses, which amplifies the previous effects and gives an opportunity to further
increase the switching frequency. The resulting converter achieves a very high power den-
sity. A volumetric power density of 75 kW/l and a gravimetric power density of 45 kW/kg
have been achieved. The efficiency of the dc-dc converter is 98.2 % at medium load de-
spite the very high switching frequency. The full benefits of SiC devices are transferred
into the application with this module resulting in a leap of the achieved power density
compared to state-of-the-art converters. Compared to the reference converter that uses
the same SiC devices, the power density is tripled. Despite the increased switching fre-
quency and smaller passive devices that are achieved with the converter prototype, the
power inductors remain the largest component of the converter. Future advancements of
dc-dc converters regarding power density will be achieved with the development of better
passive devices such as capacitors and especially inductors.
7.2 Future Work
Thermal Aspects The materials of the DBC and the device sizes determine about 50 %
of the thermal resistance of the presented cooling structure. The micro-channel structure
contributes the other 50 % to the total thermal resistance. Thus, future investigations
should focus on optimizing the geometry for baseplate-integrated cooling structures for
an even lower total thermal resistance. Different geometries should be explored for their
integration into the baseplate, for example the pin fin structure, to lower thermal resis-
tance even further. Optimized 3D-printed structures with a high surface roughness that
are manufactured from materials with a high thermal conductivity are another promising
alternative.
Lifetime The simulations of the influence of the added thermal capacity with thermal
buffers must be experimentally verified by power cycling tests. Furthermore, the degra-
dation mechanisms of highly-integrated power module must be investigated based on
accelerated-aging tests. Future potentials for an enhanced lifetime should be explored
by optimizing power modules to the specific mission profiles and target application and
taking the suitable measures. The thermal cycles causing the most degradation in the
mission profile mainly have a cycle time of several seconds up to a few hundred seconds.
In combination with integrated cooling structures with a very fast transient response,
there is additional potential to be exploited by actively controlling the cooling system.
When the pumping power and thus cooling performance is adjusted for the thermal cycles
with long cycle times, large gains in lifetime can be expected by lowering the temperature
amplitude of the cycles.
122
7.2 Future Work
Accuracy of Double-Pulse Measurements A detailed analysis has been conducted on

the differences between the current measurement based on the Rogowski coil and based
on the coaxial shunt during double-pulse tests. Accurate double-pulse measurements of
WBG devices are very different to measurements with Si devices. Even smallest changes
in the setup have large effects on the measurements. The consideration as quasi-stationary
electromagnetic waves is no longer valid and ave characteristics and their effects should
be analyzed in the future. A systematic evaluation of the influence of voltage and current
probes, cables and experimental setup should be examined for a full assessment on the
accuracy of double-pulse measurements of WBG devices.
Application-Specific Power Module Incremental updates are possible for the application-
specific power module to allow a further increase in power density. The 3rd generation
SiC MOSFETs from Wolfspeed have been released and promise better electrical charac-
teristics such as a lower Rds,on at the same die size. However, the commercially-available
MOSFETs of this generation exhibit a higher internal gate-resistance because of their
presumable target applications of inverter. This will make it difficult to achieve the fast
transients with off-the-shelf 3rd generation SiC MOSFETs. A further optimization is
possible when capacitors with higher capacitance are available, as a lot of the DBC area
is occupied by the capacitors.
Power Electronic Converters While the power densities of power electronic converters
leap forward with the advent of WBG devices, the design of passive components lacks
behind. Only incremental improvements on the system level will be achieved with better
optimized active devices and packages. Future improvements in the power density of
power electronic converters will be achieved with advanced designs of passive components.
Mainly inductors, which are still the largest remaining component in power converters,
provide potentials for further increased power densities and cost reduction in the long-
term. Coupled magnetics in multi-phase converters are such an opportunity to be explored
in the future in combination with WBG devices.
123
124
A Appendix
A.1 Cooling of SiC MOSFETs
A.1.1 Material Parameters for Simulation
The following parameters are used throughout the ANSYS Fluent simulations. They are
derived from [28], [29], [40], [48], [96], [103].
Table A.1: Thermal material properties

Material ρ in kg/m3 cp in J/kg·K κ in W/m·K µ in Pa · s
60 % water 40 % ethylene glycol mixture 1040 3870 0.45 0.002
Al 2700 897 237
Cu 8978 381 394
Al2 O3 3960 850 24
AlN 3260 740 170
Si3 N4 3170 660 90
Solder (Sn62 P b36 Ag2 ) 8500 288 50.9
Sintered Silver 10490 244 250
Si 2330 710 130
SiC 3210 670 370
A.1.2 Thermal Impedance Measurements
For the evaluation of the thermal performance of a semiconductor package and its cool-
ing structure, the static thermal resistance and the transient thermal impedance must
be measured as depicted in Figure A.1 [162]. ϑj is the junction temperature and ϑref is
the reference temperature temperature, for example the heatsink temperature, ambient
temperature or the temperature of the fluid at the inlet. Ploss is the loss dissipated from
the semiconductor. The reference temperature ϑref is usually measured via a thermocou-
ple. The state-of-the-art method to determine the junction temperature ϑj is an indirect
measurement utilizing TSEPs, which use the device as the sensor itself. Using TSEPs has
the drawback that they are only able to measure an average temperature. In general, this
temperature is not uniform across the junction [138]. Therefore, the indirectly measured
temperature is called VJT. Various TSEPs are suitable to determine the VJT [6]. The
standard method for IGBTs and diodes is to use a small dc sensing current and measure
125
A Appendix
solder chip ϑj
DBC
Ploss
Rth
heatsink thermocouple ϑref
Figure A.1: Thermal resistance.
climatic chamber
S
Isense vce (ϑj ) Idc vce (ϑj )

Vge Vge Isense
ice ice
(a) Calibration (b) Actual measurement
Figure A.2: Schematic measurement setup.
the corresponding collector-emitter voltage vce (ϑj ). Thereby, a small sensing current Isense
is preferable since it does not cause any significant additional heating of the device as long
as the current density does not exceed 100 mA/cm2 [103]. To determine vce (ϑj ), the DUT
must first be calibrated under an adjustable and well-defined temperature environment
before the actual measurement, making this methodology a two-step approach. These two
steps, the calibration and the measurement, are shortly explained in the following and
depicted for an IGBT. The procedure is also applicable to diodes, which do not require a
gate-emitter voltage, or body-diodes of turned-off MOSFETs.
The calibration process is carried out in a climatic chamber. The setup for this is shown
in Figure A.2a. The DUT is placed inside the climatic chamber while everything else, e.g.
the current source which provides the sensing current and the measurement equipment to
determine vce (ϑj ), is placed outside. In case of an IGBT, the gate voltage Vge must also
be applied to turn the device on. During the calibration procedure, Isense is applied to
the DUT at different temperatures in steady-state and vce (ϑj ) is measured. Additionally,
the DUT must be warmed up homogeneously to ensure an accurate calibration. For Si
devices, the obtained vce (ϑj ) trajectory usually has a linear slope with a negative coefficient
of −2 mV/K [6].
For the thermal impedance measurement the DUT is heated using a dc load current Idc
to generate the desired losses. The setup is shown in Figure A.2b. The sensing current
Isense is always applied to the DUT by an additional constant current source. After
thermal steady-state is reached, the load current Idc is switched off or commutated to a
free-wheeling path. Then, vce (ϑj ) is measured with only Isense applied to the DUT.
The measurement of vce (ϑj ) must be conducted shortly after the load current is switched
126
current voltage
switch measurement
ice
Idc
Isense
vce
ϑj
100 µs t
Figure A.3: Sketch of the voltage, current and temperature waveforms during measure-
ment.
die-attach
layer micro-channel
die
DBC
solder
baseplate
Figure A.4: Etched micro-channel cooler.
off to prevent any significant cooling of the DUT. However, it still must reach an electrical
equilibrium [138]. Therefore, a measurement delay of 100 µs after current turn-off is chosen
as depicted in Figure A.3. With the measured vce (ϑj ), the VJT is determined using the
calibration data.
A.1.3 Additional Measurements of Milled Micro-Channel Structure
The measurements in Table A.2 are conducted with the same prototype as in Chapter 3.
The fluid coolant is pure water.
127
A Appendix
Table A.2: Measurement results of milled cooling structure with water.

volume flow 0.2 L/min 0.41 L/min 0.59 L/min 0.73 L/min 0.83 L/min
inlet 25.1 °C 25.1 °C 25.8 °C 25.7 °C 26.8 °C
power loss 243.6 W 244.8 W 245.4 W 245.5 W 245.8 W
steady-state
124.6 °C 116.7 °C 112.5 °C 11.3 °C 108.4 °C
temperature
pump power 0.04 W 0.22 W 0.51 W 0.92 W 1.45 W
thermal
0.41 K/W 0.37 K/W 0.35 K/W 0.35 K/W 0.34 K/W
resistance
heat-transfer
coefficient
A.1.4 Etched Micro-Channel Cooling Structure
Microchannel structures can be chemically etched into the back side of a DBC substrate
into the baseplate of the module as shown by Figure A.5. Whether these structures can
effectively cool small SiC devices with high heat flux densities is investigated. Etching the
micro-channels into the backside of the DBC has the advantage that this can potentially
be integrated into one process step for the creating the layout on the top side. However,
the achievable accuracies and minimum geometries are limited due to the diffusion process.
For the experimental verification of the simulations results, a prototype is manufactured
that consist of a single SiC MOSFET silver-sintered onto an AlN DBC. A microchannel
structure with 9 channels is etched into an AlN substrate as depicted in Figure A.5 and
used as verification. The prototypes are designed for a single SiC MOSFET sintered onto
the top side of AlN DBC with dedicated areas for the gate and Kelvin-source contact.
The etched substrate is depicted Figure A.5a and Figure A.5b while the manufactured
prototypes is shown in Figure A.5c.
The manufacturing of such a prototype using silver-sintering as die-attach bonding tech-

nique is problematic due to the pressure applied on the micro-channels etched into the
DBC. As a result, the bottom side of the DBC is not flat, causing a non-homogeneous pres-
sure distribution. As the AlN ceramic is brittle, it cracks during the process. A negative
structure of the micro-channel structure is etched that can be put into the micro-channel
structure for the sintering process. This achieves uniformly distributed pressure during
the sintering process on the bottom side of the DBC and allows bonding the die to the
128
(a) bottom view of (b) top view of DBC (c) Assembled prototype
DBC
Figure A.5: Etched prototype.
100
160
140
Temperature in °C
120
100 10-1
80
60 10-2
40
20
0 10-3
0 1 2 3 4 5 10-3 10-2 10-1 100 101
Time in s Time in s
(a) Transient thermal response (b) Thermal impedance
Figure A.6: Measurement results of etched micro-channel cooler.
substrate without cracks. However, this process is likely not suitable for mass production
and poses doubts on the long-term stability of the DBC with the etched micro-channels.
The thermal impedance of the etched micro-channel cooler is measured. Figure A.6 shows
the measurement for a power loss of 293 W with a pressure drop of 1.05 bar and a volume
flow of 0.68 L/min. The measurement is conducted with the water glycole mixture. The
measured thermal resistance is 0.4209 K/W.
The heat-transfer coefficient calculated according to Equation (3.6) is 6.31 W/cm2 K when
the die area is used as a reference. This can be explained by an overestimated pressure drop
along the inlet and outlet tubes, resulting in a higher volume flow during the measurement.
Furthermore, the heat conduction of the top side interconnections is neglected in the
simulation and the prototype exhibits a larger copper area around the chip than simulated.
129
A Appendix
The junction temperature measurement for different pressure drops and volume flows is
shown in Table A.3. As a compromise between pressure drop and a good heat-transfer
coefficient, a pressure drop in the range of 0.3 bar to 0.5 bar is favorable. The heat-transfer
coefficient increases to 7.93 W/cm2 K at 0.51 bar while the pump power is kept limited at
0.38 W. The thermal resistance drops to 0.48 K/W. Calculating the junction temperature
with an inlet temperature of 25 °C and a power loss of 300 W, the result is 169 °C, which
is below the maximum junction temperature. Doubling the pressure drop to more than
1 bar only increases the heat-transfer coefficient slightly and reaches 9.17 W/cm2 K. 300 W
of power loss can be dissipated with a junction temperature of 151 °C. The calculated
pump power reaches 1.18 W at 1.03 bar.
Aspects of this section have been investigated and are already published in [160].
A.1.5 3D-printed Cooling Structure as Baseplate Replacement
Additive manufacturing makes it possible to create basically arbitrary and very fine struc-
tures. Furthermore, a high surface roughness is automatically achieved during the 3D-
printing process for an increased surface area for the fluid. This makes it potentially
attractive for coolers as very small structures optimized for best cooling performance can
be manufactured.
To examine the feasibility of 3D-printed coolers, a prototype is manufactured by IQ

evolution GmbH for the same single SiC MOSFET as used in the micro-channel structures.
Table A.3: Measurement results of etched cooling structure.

volume flow 0.19 L/min 0.33 L/min 0.44 L/min 0.57 L/min 0.69 L/min
inlet temperature 20.7 °C 20.4 °C 20.6 °C 20.4 °C 20.3 °C
power loss 238.9 W 241.5 W 242.9 W 243.8 W 243.9 W
steady-state
166.1 °C 149.6 °C 138.3 °C 130.9 °C 122.5 °C
temperature
pump power 0.04 W 0.14 W 0.38 W 0.73 W 1.18 W
thermal
0.61 K/W 0.53 K/W 0.48 K/W 0.45 K/W 0.42 K/W
resistance
heat-transfer
coefficient
130
(a) 3D-printed cooler (b) Prototype with attached cooler
Figure A.7: 3D-printed prototype.
The prototype is depicted in Figure A.7. The cooler is designed such that it replaces the
baseplate of the power module and, thus, also provides a very low-volume cooling solution.
It is soldered to the backside of the module.
The 1.4404 stainless steel surface is electro-chemically nickel and gold-plated to create a
solderable surface finish. The fluid coolers has an internal pin-fin structure. The usage
of stainless steel makes this a potentially very robust solution regarding corrosion and
long-term stability. But due to the low thermal conductivity of stainless steel of about
15 W/m K compared to copper with a thermal conductivity greater than 300 W/m K, the
thermal resistance may be higher as the heat conduction into the cooler is limited and
heat-spreading is reduced. However, the wall thickness of the cooler is in the range of
only 150 µm, which limits effects of the low thermal conductivity.
The thermal impedance of the 3D-printed cooler is measured as before. Figure A.8 shows
the measurement for a power loss of 243 W with a pressure drop of 1.02 bar and a volume
flow of 0.8 mL/min. The measurement is conducted with pure water as coolant. The pump
power is 1.36 W. Similar to the micro-channel cooling structure, the 3D-printed cooler
requires a higher pressure drop but lower volume flow compared to state-of-the-art cooling
solutions for power electronics. The achieved steady-state resistance is 0.48 K/W. This is
about 0.09 K/W higher than the milled micro-channel structure or 23 %. The 3D-printed
cooler exhibits a similar, very fast transient response that indicates that only a very low
thermal capacity is available.
The previously presented micro-channel structure is made of copper and, therefore, has
an advantage due to the thermal conductivity of copper. Additionally, the fluid coolant
is in direct contact with the copper of the DBC, whereas the 3D-printed cooler is only
thermally-attached via the solder layer with a higher thermal resistance. The 3D-printed
cooler is also designed such that the surface is homogeneously cooled. The micro-channel
131
A Appendix
100

160
140
Temperature in °C
120
100 10-1
80
60 10-2
40
20
0 10-3
0 1 2 3 4 5 10-3 10-2 10-1 100 101
Time in s Time in s
(a) Transient thermal response (b) Thermal impdeance
Figure A.8: Measurement results of 3D-printed cooler.
cooler are designed and optimized to cool directly beneath the SiC MOSFETs, but not
anywhere else.
While the 3D-printed cooler achieves a slightly lower cooling performance compared to
the micro-channel cooler heavily-optimized for the specific devices, the 3D-printed cooler
is suitable to effectively cool large surfaces in power electronic modules with very low
volume requirements. Further improvements to this cooling structure may be achieved
when a micro-channel cooling structure as outlined in the previous and optimized for the
specific device dimensions is combined with the 3D-printing process.
A prototype of 3D-printed cooler for a 62 mm half-bridge module is investigated in [20].
132
A.2 Thermal and Lifetime simulation
A.2.1 Additional Data of WLTC for Integrated Power Module
104
Number of cycles
2
10
100
0 25 50 0 25 50 0 25 50 0 25 50 0 25 50 0 25 50 0 25 50
Figure A.9: Histogram of calculated temperature cycles for MOSFET1 for WLTC.
133
A Appendix
Temperature amplitude in °C 50
40
30
20
10
0
0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20
Individual cycle
Figure A.10: Temperature amplitude of most significant thermal cycles for MOSFET1
for WLTC.
1600
1400
1200
Cycle time in s
1000
800
600
400
200
0
0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20
Individual cycle
Figure A.11: Cycle time of most significant thermal cycles for MOSFET1 for WLTC.
134
A.2.2 Lublin Cycle Results with Integrated Power Module with SiC
Buffers
The following lifetime simulation are conducted with the integrated power module with
thermal buffers made of SiC on top. The results are similar to the thermal buffers made
of copper. Due to the lower thermal capacity of SiC, the achievable increase in lifetime
during the Lublin cycle is a factor of three compared to a factor of four with thermal
buffers of copper.
104
Number of cycles
2
10
100
0 30 60 0 30 60 0 30 60 0 30 60 0 30 60 0 30 60 0 30 60
Figure A.12: Histogram of calculated temperature cycles.
135
A Appendix
5 1

without
4 0.8 0.5 mm
1 mm
without 2 mm
3 0.6
0.5 mm 3 mm
1 mm 4 mm
2 0.4
2 mm 5 mm
3 mm
1 4 mm 0.2
5 mm
0 0
Devices Devices
(a) Without buffer (b) With buffer
Figure A.13: Calculated cycles to failure and degradation.
0.35 1

0.3
0.8
Degradation in p.u.
0.25
0.2 0.6
0.15 0.4
0.1
0.2
0.05
0 0
0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20
Individual cycle
Figure A.14: Degradation of most significant thermal cycles.
136
60
50
40
30
20
10
0
0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20
Individual cycle
Figure A.15: Magnitude of models with thermal buffers referenced to no buffers.
700
600
500
Cycle time in s
400
300
200
100
0
0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20
Individual cycle
Figure A.16: Cycle time of most significant thermal cycles.
137
A Appendix
A.2.3 Lublin Cycle Results with Conventional Power Module
The following simulation results follow the same procedure as described in Chapter 4 for
a commercially-available power module [193] attached to a fluid heatsink with a thermal
resistance of 0.02 K/W. The power module uses the same semiconductor as the integrated
power module developed during this thesis [192]. The power module with the different
thermal buffer sizes is simulated with the same load profile as the integrated structure in
Chapter 4.
100
10-1
without
0.5 mm
10-2 1 mm
2 mm
3 mm
4 mm
5 mm
10-3 -4
10 10-3 10-2 10-1 100 101
Time in s
Figure A.17: Thermal impedance of integrated structure with an without buffers.
138
100
without
-1 0.5 mm
10
1 mm
2 mm
10-2
3 mm
4 mm
10-3
0
Phase in °
-20
-40
-60
-80
10-2 10-1 100 101 102 103 104
Frequency in Hz
Figure A.18: FRF of thermal model with and without thermal buffers.
0.9
0.8
0.7
0.6 0.5 mm
1 mm
0.5 2 mm
3 mm
4 mm
0.4
10-2 10-1 100 101 102 103 104
Frequency in Hz
Figure A.19: Magnitude of thermal model with thermal buffers referenced to no buffers.
139
A Appendix
104 104 104 104 104 104 104

Number of cycles
102 102 102 102 102 102 102
100 100 100 100 100 100 100

0 50 0 50 0 50 0 50 0 50 0 50 0 50
Figure A.20: Histogram of calculated temperature cycles.
1
without
6 0.5 mm
0.8
1 mm
without 2 mm
4 0.6
0.5 mm 3 mm
1 mm 4 mm
0.4
2 mm 5 mm
2 3 mm
4 mm 0.2
5 mm
0 0
Devices Devices
(a) Without buffer (b) With buffer
Figure A.21: Calculated cycles to failure and degradation.
140
0.25 1

0.2 0.8
Degradation in p.u.
0.15 0.6
0.1 0.4
0.05 0.2
0 0
0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20
Individual cycle
Figure A.22: Degradation of most significant thermal cycles.
90
80
70
60
50
40
30
20
10
0
0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20
Individual cycle
Figure A.23: Magnitude of models with thermal buffers referenced to no buffers.
141
A Appendix
700
600
500
Cycle time in s
400
300
200
100
0
0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20 0 10 20
Individual cycle
Figure A.24: Cycle time of most significant thermal cycles.
142
A.3 Double-Pulse Measurements
A.3.1 Decomposition of Shunt
A T&M Research Products SDN-414-10 is decomposed to obtain the geometry of the

device. The outer brass case is cut in half and the inner part with the resistive foil is
removed as depicted in Figure A.25. The thickness of the resistive foil is measured with
an optical microscope in Figure A.26.
(a) Cut brass case (b) Inner part
Figure A.25: Decomposed shunt.
A.3.2 S-Parameter Measurement of Shunt
The S-parameters of the T&M Research Products SDN-414-10 are measured with a Tek-
tronix TTR506A VNA. A BNC connector is soldered to the leads of the input connector
for the current, which is shown in Figure A.27. A SOLT calibration (short, open, load,
through) is carried out including all cable, adapters and both BNC connectors of the
shunt such that only the characteristics of the shunt geometry are measured with the
VNA. The measurement is depicted in Figure A.28.
The measured S-Parameters are converted to Z-Parameters. The relevant parameter Z21
that describes the voltage at port 1 for a current in port 2, is given in Figure A.29. At
1.61 GHz a resonance is visible. At this frequency, a quarter of the wavelength λ/4 is 31 mm,
143
A Appendix
Figure A.26: Resistive foil examined with microscope.
Figure A.27: Shunt with attached BNC port for VNA measurement.
which roughly corresponds to the total length of the shunt from one BNC connector to
the other.
A.3.3 Shunt Measurements With Compensated Delay
The phase increase due to the inductive behavior of the shunt has a significant influence
on the determined switching losses. When the phase increase is compensated with a fixed
time delay, the waveforms depicted in Figure A.30 and Figure A.31 are obtained.
144
Figure A.28: VNA measurement setup of shunt.
For the measurement with RG,on = 4.7 Ω, the shunt-based measurement gives 104.8 µJ for
turn-off and 219.6 µJ for turn-on. The Rogowski coil-based measurement gives 111.2 µJ
for turn-off and 219.6 µJ for turn-on. Thereby, the relative error for the turn-off losses is
−6.1 % and 2.66 % for turn-on.
Due to the smaller turn-on resistance, the reverse-recovery current peak increases and
causes more voltage ringing afterwards. The Rogowski coil is able to successfully measure
the current rise and fall and the following oscillations. However, an amplitude error
between the measurement based on the Rogowski coil and the shunt can be observed at
each peak of the oscillations. At the first peak, the error is 4.89 A or 4.68 %.
145
A Appendix
102
Impedance in
101
100
-1
10
200
Phase in °
-200
100 101 102 103
Frequency in MHz
Figure A.29: Resistive examined with microscope.
600 120 600 120

uDS uDS
500 100 500 100
Voltage in V
Voltage in V
400 80 400 80
Current in A
Current in A
iD,shunt iD,shunt
300 60 300 60
200 40 200 40
100 20 100 20
0 0 0 0
0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160

Figure A.30: Waveform comparison between Rogowski and shunt-based measurement.
For the measurement with RG,on = 2.2 Ω, the shunt-based measurement gives 105.3 µJ for
turn-off and 148.1 µJ for turn-on. The Rogowski coil-based measurement gives 109.4 µJ
for turn-off and 144 µJ for turn-on. Thereby, the relative error for the turn-off losses is
−3.87 % and 2.78 % for turn-on.
The Rogowski coil-based and the shunt-based measurement are repeated several times
and compared at currents up to 50 A. The errors are within the same range. Hence, when
shunts are used with WBG devices, the phase increase should at least be compensated to
146
600 120 600 120

uDS uDS
500 100 500 100
Voltage in V
Voltage in V
400 80 400 80
Current in A
Current in A
iD,shunt iD,shunt
300 60 300 60
200 40 200 40
100 20 100 20
0 0 0 0
0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160

Figure A.31: Waveform comparison between Rogowski and shunt-based measurement.
achieve more realistic results and minimize measurement errors.
147
A Appendix
A.4 Power module
A.4.1 Additional Waveforms
The turn-on waveforms in Figure A.32 and turn-off waveforms Figure A.33 are measured
using an external turn-on resistor RG,on of 2.2 Ω.
1000 75
Voltage in V
Current in A
800 uDS 60
600 iD 45
400 30
200 15
0 0
0 10 20 30 40 50 60 70 80 90 100
Voltage in V
20
10
0
uGS
-10
0 10 20 30 40 50 60 70 80 90 100
Time in ns
Figure A.32: Turn-on waveforms at 40 A and RG,on = 2.2 Ω.
A.4.2 Additional Measurement Results
Due to being limited to a 4 channel oscilloscope, the measured over-voltages across the
diodes depicted in Figure A.34 are measured during different test runs, but with the same
settings. the over-voltage is highly-dependent on the load current for no external turn-on
resistor. It decreases considerably going to higher currents. Overall, the over-voltages are
within a safe level.
The following results are obtained with the double-pulse test bench with the prototype
with 2.2 Ω external turn-on resistor. The results are being presented for the sake of
completeness without further discussion.
148
A.4 Power module
1000 50
Voltage in V
Current in A
800 uDS 40
600 iD 30
400 20
200 10
0 0
0 10 20 30 40 50 60 70 80 90 100
Voltage in V
20 uGS
10
0
-10
0 10 20 30 40 50 60 70 80 90 100
Time in ns
Figure A.33: Turn-off waveforms at 40 A and RG,on = 2.2 Ω.
160
0 Ohm
140 2.2 Ohm
4.7 Ohm
Diode over-voltage in V
120
100
80
60
40
20
0 10 20 30 40 50 60 70 80
Current in A
Figure A.34: Comparison of diode over-voltages.
149
A Appendix
250
10 A
30 A
200 50 A
Turn-off losses in µJ
150
100
50
0
200 300 400 500 600 700 800
Voltage in V
Figure A.35: Comparison of turn-off losses at different voltages.
500
10 A
30 A
400 50 A
Turn-on losses in µJ
300
200
100
0
200 300 400 500 600 700 800
Voltage in V
Figure A.36: Comparison of turn-on losses at different voltages.
150
A.4 Power module
Turn-off maximum dv/dt in V/ns
Turn-off 10-90% dv/dt in V/ns

100 80
10 A 10 A
80 30 A 30 A
50 A 60 50 A
60
40
40
20
20
0 0
200 400 600 800 200 400 600 800
Voltage in V Voltage in V
Figure A.37: Comparison of turn-off dv/dt.

Turn-on maximum dv/dt in V/ns
Turn-on 10-90% dv/dt in V/ns
80 60
10 A
70 50 30 A
50 A
60 40
50 30
10 A
40 30 A 20
50 A
30 10
200 400 600 800 200 400 600 800
Figure A.38: Comparison of turn-on dv/dt.
151
A Appendix
Turn-off maximum di/dt in A/ns
Turn-off 10-90% di/dt in A/ns

12 8
10 A 10 A
10 30 A 30 A
50 A 6 50 A
8
6 4
4
2
2
0 0
200 400 600 800 200 400 600 800
Figure A.39: Comparison of turn-off di/dt.

Turn-on maximum di/dt in A/ns
Turn-on 10-90% di/dt in A/ns
11 8
10 A 10 A
10 30 A 30 A
50 A 50 A
9 6
8
4
7
6
2
5
200 400 600 800 200 400 600 800
Figure A.40: Comparison of turn-on di/dt.
152
A.4 Power module
Turn-on maximum current in A

120 100
Turn-off over-voltage in V
10 A 10 A
100 30 A 30 A
50 A 80 50 A
80
60 60
40
40
20
0 20
200 400 600 800 200 400 600 800
(a) Over-voltage during turn-off (b) Current peak during turn-on
Figure A.41: Comparison of maximum values.
153
A Appendix
1000 100
Voltage in V
Current in A
800 uDS 80
600 i
D
60
400 iD,channel 40
200 20
0 0
0 10 20 30 40 50 60 70 80 90 100
Voltage in V
20 u
GS
10
0
-10
0 10 20 30 40 50 60 70 80 90 100
Time in ns
Figure A.42: Simulated turn-off waveforms.
A.4.3 Simulating Double-Pulse Test with SPICE
For further analysis and loss simulations, the vendor-provided SPICE models of the uti-
lized devices [192] are used in a SPICE simulation implemented in SIMetrix . However,
the models are only mathematical representations of the device and their switching be-
havior and do not necessarily represent the reality. For the utilized devices, it has been
found that the models are not accurate [152]. Especially the reverse-recovery of diodes is
not implemented correctly in standard SPICE models. SIMetrix with its focus on power
electronics circuit offers a soft-recovery diode model, which follows a SPICE model that
includes reverse-recovery in diodes as described in [95]. The model can be parameterized
from datasheet values. The device models are fitted such that the simulated switching
losses during the double-pulse test approximately match those obtained via the double-
pulse measurements.
The vendor-provided device models are separated into several subcircuits, for example
the Miller-capacitance CGD , the body-diode and the drain-source capacitance CDS . This
allows the separation of the current in the device channel from the total device current.
The result for a turn-off current of 79 A and a turn-on current of 65 A with no external
gate resistor are shown in Figure A.42 and Figure A.43. The current values are the same
as in Figure 5.40 and Figure 5.40 from the measurements.
The simulation shows similar waveforms compared to the measured values. However, the
switching transient are faster than the measured values, although an extra common gate
154
A.4 Power module
1000 200
Voltage in V
Current in A
800 uDS 160
600 i
D
120
400 iD,channel 80
200 40
0 0
0 10 20 30 40 50 60 70 80 90 100
Voltage in V
20
10
0
uGS
-10
0 10 20 30 40 50 60 70 80 90 100
Time in ns
Figure A.43: Simulated turn-on waveforms.
resistor is already added to the model to slow the switching. Otherwise, the switching
transients would have been more than twice as fast as measured. As a result, the gate
voltage waveforms look different compared to the measured values. The turn-off energy
228.7 µJ and the turn-on energy 531.3 µJ, which is an underestimation of the turn-off
energy and an overestimation of the turn-on energy. Especially the turn-on energy is
dependent on the modeling of the reverse-recovery effect of the body-diodes. Although
the utilized soft-recovery model gives considerably better results than the standard model,
precise measurements of the diode current are necessary to correctly parameterize the
model. This could not be carried out due to the lack of a current sensor for the high-side
body-diode and datasheet values have been used.
The modeling of the device with separated subcurcuits allows extracting the current in the
channel of the device and to calculate the actual device losses without any stored energy
of the capacitances. The channel current iDchannel is also depicted in Figure A.42 and
Figure A.43. The charging of the capacitor is observable during turn-off where the channel
current is lower than the total drain current iD . The difference between the currents is
charging the output capacitance Coss of the device. During turn-on, the discharge current
is added on top of the drain current measured outside of the device. The calculated turn-
off energy 155.4 µJ and the turn-on energy 601.4 µJ are with the channel current. This is
a difference of approximately 70 µJ less for turn-off and 70 µJ more for turn-on. The sum
of the switching loss is the approximately the same as when calculated with the drain
current, showing the charging and discharging of the capacitance. While the total losses
are the same, the energy of the capacitor is dissipated at turn-on but measured at turn-off
during a double-pulse test, which is especially important for soft-switched applications.
155
A Appendix
The switching trajectories are shown in Figure A.44 that also show the difference be-
tween the total drain current iD measured outside of the device and the channel current
iDchannel .
100 200
ideal ideal
80 iD iD
150
Current in A
Current in A
60 iD,channel iD,channel
40 100
20
50
0
-20 0
0 200 400 600 800 1000 0 200 400 600 800 1000
(a) Turn-off trajectory. (b) Turn-on trajectory.
Figure A.44: Switching trajectories.
156
A.5 Converter
A.5 Converter
Figure A.45: Initial technology demonstrator with custom power module.
Figure A.46: Integrated converter with custom power module.
157
158
B Acronyms
3D three dimensional
Al aluminum
Al2 O3 aluminum oxide
AlN aluminum nitride
AMB active metal brazed
CFD computational fluid dynamics

CTE coefficient of thermal expansion
Cu copper
DBC direct bonded copper

DUT device under test
EMC electromagnetic compatibility

EMI electromagnetic interference
FRF frequency response function
GaN gallium nitride
HTCC high temperature cofired ceramics
IC integrated circuit
IGBT insulated-gate bipolar transistor
IPM intelligent power module
LISN line impedance stabilization network

LTCC low temperature cofired ceramics
MCU microcontroller
MOSFET metal-oxide semiconductor field-effect transistor
PCB printed circuit board

PLA Polylactic acid
PWM pulse-width modulation
159
Acronyms
RMS root mean square
SBD Schottky-barrier diode

Si silicon
Si3 N4 silicon nitride
SiC silicon carbide
SMB SubMiniature version B
SOD state-of-degradation
SPICE simulation program with integrated circuit emphasis
TIM thermal interface material

TSEP temperature sensitive electrical parameter
VJT virtual junction temperature

VNA vector network analyzer
WBG wide-bandgap
WLTC Worldwide harmonized Light duty driving Test Cycle
160
C Symbols
AC ac node
Adie semiconductor die area
βi empirical technology parameter of LESIT model

Ub blocking voltage
CDC dc-link capacitor

CDC− capacitance between the DC- terminal and the heat
sink
CDC+ capacitance between the DC+ terminal and the heat
sink
CDS drain-source capacitance
CGD gate-drain capacitance
CGS gate-source capacitance
Γ ratio of the fin to channel width
H height of micro-channel
N number of channels
W width of micro-channel structure
Cin input capacitance
Coss MOSFET output capacitance
Cout output capacitance
Cpar total parasitic capacitance of the module during
switching
Crog parasitic capacitance of Rogowski coil
CSW capacitance between the SW terminal and the heat
sink
ζ damping ratio of second order system

∆iL ripple current in the inductor
ρ volumetric mass density
∆p pressure drop
Dwire bond wire diameter
di/dt current transient
dv/dt voltage transient
µf dynamic viscosity
Eoff turn-off switching energy
161
Symbols
Eon turn-on loss energy including diode turn-off losses

Eoss stored energy in Coss
fres resonant frequency

fsw switching frequency
k gain of second order system

Grog (s) transfer function of the Rogowski coil
Gshunt (s) transfer function of the shunt
Gshunt (s)−1 inverse transfer function of the shunt
Dh hydraulic diameter
cp specific heat capacity
h heat transfer coefficient
iC capacitor current
iD instantaneous drain current
Idc dc load current
iD,rog instantaneous drain current measured via Rogowski
coil
iD,shunt instantaneous drain current measured via shunt
iD,shunt,corrected instantaneous drain current measured via shunt and
corrected with inverse transfer function
iL instantaneous inductor current
Iwire current per bond wire
iph phase current
ishunt instantaneous current measured via shunt
ϑj junction temperature
ν kinematic viscosity
K empirical technology parameter of LESIT model
LDC stray inductance of dc-link capacitor

LG gate inductance
l length of conductor
L inductance of the power inductor
Lrog inductance of Rogowski coil
Lshunt parasitic inductance within the measurement path of
the shunt
Lσ stray inductance
µr relative permeability
Nf number of cycles to failure
162
Symbols
Nf,ref number of cycles to failure of reference cycle

Nf,cycle number of cycles to failure of a complete driving cycle
PCond conduction losses

µ permeability
Ploss power loss/heat flow
PNom nominal power
Ppump pumping power
PSW switching losses
Q volumetric flow rate
Rds,on MOSFET on state resistance

ρel electrical resistivity
Re Reynolds number
Recrit critical Reynolds number
RG,int internal gate resistance
RG,on gate turn-on resistance
Rshunt calibrated resistance of the shunt
Rterm termination resistor
Rth thermal resistance
SH high-side MOSFET
δ skin depth
SL low-side MOSFET
κ thermal conductivity
α0 temperature coefficient of electrical resistance
tcycle power-on-time during the cycle
tcycle,ref power-on-time during of the reference cycle
∆ϑ temperature difference
toff turn-off time
ton turn-on time
ϑref reference temperature
uC capacitor voltage
Udc dc-link voltage
uDS drain-source voltage
Uf forward voltage of diode
uGS low-side gate-source voltage
Uin input voltage
uL voltage accross an inductor L
Uout output voltage
Urog induced voltage in Rogowski coil
163
Symbols
v velocity
ω angular frequency
λ wavelength
ω0 natural angular frequency of second order system
Z12 impedance parameter of two-port network from port

2 to port 1
Zth (jω) thermal impedance
Zth,ref (jω) reference thermal impedance
164
List of Figures
2.1 Conventional package structure. . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 SiC power module from Wolfspeed [193]. . . . . . . . . . . . . . . . . . . . 8
2.3 35 nH power module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Voltage waveforms during switching with high stray inductance. . . . . . . 8
(a) Turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
(b) Turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Layouts of lateral SiC power modules . . . . . . . . . . . . . . . . . . . . . 9
(a) Layout of [193] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
(b) Layout of [167] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
(c) Layout of [32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Micro-channel cooler milled into baseplate. . . . . . . . . . . . . . . . . . . 16

3.2 Temperature rendering of the cooling structure. . . . . . . . . . . . . . . . 18
3.3 Cross-sectional contour plot of temperature. . . . . . . . . . . . . . . . . . 20
3.4 View of the geometry parameters changed during the parameter sweep and
the simulation results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
(a) DBC structure top view . . . . . . . . . . . . . . . . . . . . . . . . . 22
(b) Simulation results of the parameter sweep . . . . . . . . . . . . . . . 22
3.5 Investigated parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 Results of parameter sweep. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
(a) Solder layer thickness . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
(b) baseplate thickness . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7 Investigated channel parameters. . . . . . . . . . . . . . . . . . . . . . . . 24
3.8 Channel width and height simulation results. . . . . . . . . . . . . . . . . . 25
(a) Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 25
(b) Pumping power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9 Milled prototype. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
(a) DBC with MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
(b) Milled baseplate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
(c) Assembled prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10 Contour plot on cross section with different volume flow. . . . . . . . . . . 28
(a) 0.52 l/min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
(b) 0.84 l/min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.11 Transient simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
(a) transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
(b) impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
165
List of Figures
3.12 Exemplary calibration and impedance measurement. . . . . . . . . . . . . 30

(a) calibration of forward voltage . . . . . . . . . . . . . . . . . . . . . . 30
(b) impedance measurement . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.13 Setup of the thermal impedance measurements. . . . . . . . . . . . . . . . 31
3.14 Calculated temperature and thermal impedance. . . . . . . . . . . . . . . . 31
(b) calculated thermal impedance . . . . . . . . . . . . . . . . . . . . . . 31
3.15 Measurements at different volume flows. . . . . . . . . . . . . . . . . . . . 32
(b) calculated thermal impedance . . . . . . . . . . . . . . . . . . . . . . 32
4.1 Structure of a module with a thermal buffer. . . . . . . . . . . . . . . . . . 38

4.2 Structure of integrated module with a thermal buffer. . . . . . . . . . . . . 38
4.3 Simulated transient junction temperature. . . . . . . . . . . . . . . . . . . 40
(a) Simulated junction temperature . . . . . . . . . . . . . . . . . . . . . 40
(b) Simulated temperature difference . . . . . . . . . . . . . . . . . . . . 40
4.4 Prototype with thermal buffer on top of die. . . . . . . . . . . . . . . . . . 41
4.5 Measurement of prototype with and without thermal buffer. . . . . . . . . 41
(a) Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 41
(b) Thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.6 Visualization of the model and its temperature increase. . . . . . . . . . . 42
(a) Temperature without buffer . . . . . . . . . . . . . . . . . . . . . . . 42
(b) Temperature with buffer . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.7 Thermal impedance of MOSFET1 for different buffer heights and without
buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.8 FRF of MOSFET1 for different buffer heights and without buffer. . . . . . 44
4.9 Relative magnitude for different buffer heights referenced to model without
buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.10 Lublin driving cycle data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
(a) Speed profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
(b) Calculated amplitudes . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.11 WLTC driving cycle data . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
(a) Speed profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
(b) Calculated amplitudes . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.12 Histogram of calculated temperature cycles for MOSFET1. . . . . . . . . . 49
4.13 Calculated cycles to failure and degradation for Lublin cycle. . . . . . . . . 50
(a) Calculated cycles to failure . . . . . . . . . . . . . . . . . . . . . . . 50
(b) Calculated degradation . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.14 Degradation of most significant thermal cycles for Lublin cycle. . . . . . . 51
4.15 Temperature amplitude of most significant thermal cycles for MOSFET1
for Lublin cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.16 Cycle time of most significant thermal cycles for MOSFET1 for Lublin cycle. 52
4.17 Calculated cycles to failure and degradation for WLTC. . . . . . . . . . . . 53
(a) Calculated cycles to failure . . . . . . . . . . . . . . . . . . . . . . . 53
(b) Calculated degradation . . . . . . . . . . . . . . . . . . . . . . . . . . 53
166
List of Figures
4.18 Degradation of most significant thermal cycles for WLTC. . . . . . . . . . 54
5.1 Layout of the commutation cell. . . . . . . . . . . . . . . . . . . . . . . . . 59

5.2 Manufactured prototype of integrated power module. . . . . . . . . . . . . 60
5.3 Cooling structure of the power module. . . . . . . . . . . . . . . . . . . . . 61
(a) Micro-channel cooling structure. . . . . . . . . . . . . . . . . . . . . . 61
(b) Attached micro-channel cooling structure. . . . . . . . . . . . . . . . 61
5.4 Parasitic elements in the power module. . . . . . . . . . . . . . . . . . . . 62
5.5 ANSYS Q3D Extractor model of the power loop. . . . . . . . . . . . . . . 63
5.6 Simulated stray inductance of the power loop. . . . . . . . . . . . . . . . . 63
5.7 Dummy prototype. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.8 Measured stray inductance of the power loop. . . . . . . . . . . . . . . . . 64
5.9 ANSYS Q3D Extractor model of the gate loop. . . . . . . . . . . . . . . . 64
5.10 Simulated stray inductance of the gate loop. . . . . . . . . . . . . . . . . . 65
5.11 Measured stray inductance of the gate loop. . . . . . . . . . . . . . . . . . 65
5.12 Parasitic capacitances in the power module. . . . . . . . . . . . . . . . . . 66
5.13 Principle of double-pulse measurement. . . . . . . . . . . . . . . . . . . . . 67
(a) Schematic of double-pulse measurement. . . . . . . . . . . . . . . . . 67
(b) Schematic current and voltage waveforms . . . . . . . . . . . . . . . 67
5.14 Power module for double-pulse tests. . . . . . . . . . . . . . . . . . . . . . 68
(a) Manufactured prototype . . . . . . . . . . . . . . . . . . . . . . . . . 68
(b) Location of current measurement for double-pulse . . . . . . . . . . . 68
5.15 ANSYS Q3D Extractor model of power module for double-pulse tests. . . . 70
(a) DBC-based module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
(b) PCB-based module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.16 ANSYS Q3D Extractor model with visualized eddy-currents on the backside. 71
5.17 Picture of the double-pulse test setup. . . . . . . . . . . . . . . . . . . . . 72
5.18 Power module connected in double-pulse test setup. . . . . . . . . . . . . . 73
5.19 Manufactured Rogowski coil current probe. . . . . . . . . . . . . . . . . . . 74
(a) Rogowski coil receiver . . . . . . . . . . . . . . . . . . . . . . . . . . 74
(b) Ω-shaped copper tube . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.20 Simplified schematic for Rogowski coil. . . . . . . . . . . . . . . . . . . . . 75
5.21 Picture of the Rogowski simulation setup in ANSYS Q3D Extractor . . . . . 75
5.22 Double-pulse waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
(a) Measured drain-source voltage and current . . . . . . . . . . . . . . . 76
(b) Measured Rogowski coil signal . . . . . . . . . . . . . . . . . . . . . . 76
5.23 Integration and filtering of measured Rogowski coil signal. . . . . . . . . . 77
(a) Integrated Rogowski signal . . . . . . . . . . . . . . . . . . . . . . . . 77
(b) High-pass filtered integrated Rogowski signal . . . . . . . . . . . . . . 77
5.24 Compensated and integrated Rogowski coil signals. . . . . . . . . . . . . . 78
(a) Compensated Rogowski signal . . . . . . . . . . . . . . . . . . . . . . 78
(b) Compensated Rogowski signal with adjusted offset . . . . . . . . . . 78
5.25 Synchronization of the current. . . . . . . . . . . . . . . . . . . . . . . . . 78
(a) Inductor current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
(b) Calculated current waveform with Rogowski coil . . . . . . . . . . . . 78
167
List of Figures
5.26 Measurement setup with shunt and Rogowski measurement. . . . . . . . . 79

5.27 Current waveform comparison with 4.7 Ω turn-on resistor. . . . . . . . . . . 80
(a) Turn off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
(b) Turn on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.28 Current waveform comparison with 2.2 Ω turn-on resistor. . . . . . . . . . . 81
(a) Turn off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
(b) Turn on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.29 Calculated transfer function of Rogowski coil. . . . . . . . . . . . . . . . . 82
5.30 ANSYS 2D Extractor simulation. . . . . . . . . . . . . . . . . . . . . . . . 84
(a) 2D simulation model . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
(b) Simulated ac resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.31 ANSYS Q3D Extractor model of coaxial shunt. . . . . . . . . . . . . . . . 85
(a) Cross section with added current flow . . . . . . . . . . . . . . . . . . 85
(b) 3D simulation model . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.32 Simulated transfer function of the shunt. . . . . . . . . . . . . . . . . . . . 86
5.33 Transfer function of the shunt. . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.34 Waveform comparison between Rogowski and shunt-based measurement
with 4.7 Ω turn-on resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
(a) Turn off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
(b) Turn on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.35 Waveform comparison between Rogowski and shunt-based measurement
with 2.2 Ω turn-on resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
(a) Turn off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
(b) Turn on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.36 Turn-on waveforms at 65.2 A and 4.7 Ω turn-on resistor. . . . . . . . . . . . 90
5.37 Turn-off waveforms at 79 A and 4.7 Ω turn-on resistor. . . . . . . . . . . . . 91
5.38 Instantaneous power with 4.7 Ω turn-on resistor. . . . . . . . . . . . . . . . 92
(a) Turn on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
(b) Turn off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.39 Turn-on waveforms at 65 A and 0.0 Ω turn-on resistor. . . . . . . . . . . . . 93
5.40 Turn-off waveforms at 78.6 A and 0.0 Ω turn-on resistor. . . . . . . . . . . . 94
5.41 Instantaneous power with 0.0 Ω turn-on resistor. . . . . . . . . . . . . . . . 95
(a) Turn on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
(b) Turn off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.42 Comparison of turn-off switching energies with different turn-on resistors. . 96
5.43 Comparison of turn-off dv/dt. . . . . . . . . . . . . . . . . . . . . . . . . . . 96
(a) Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
(b) from 10 % to 90 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.44 Comparison of turn-off di/dt. . . . . . . . . . . . . . . . . . . . . . . . . . . 97
(a) Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
(b) from 10 % to 90 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.45 Comparison of turn-on switching energies with different turn-on resistors. . 98
5.46 Comparison of turn-on dv/dt. . . . . . . . . . . . . . . . . . . . . . . . . . . 98
(a) Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
(b) from 10 % to 90 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
168
List of Figures
5.47 Comparison of turn-on di/dt. . . . . . . . . . . . . . . . . . . . . . . . . . . 99

(a) Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
(b) from 10 % to 90 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.48 Comparison of maximum values. . . . . . . . . . . . . . . . . . . . . . . . . 100
(a) Over-voltage during turn-off . . . . . . . . . . . . . . . . . . . . . . . 100
(b) Current peak during turn-on . . . . . . . . . . . . . . . . . . . . . . . 100
6.1 Schematic of synchronous boost converter . . . . . . . . . . . . . . . . . . 104

6.2 Design of inductor prototype. . . . . . . . . . . . . . . . . . . . . . . . . . 105
(a) Winding order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
(b) Picture of power inductor . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3 Resistance and inductance of the inductors. . . . . . . . . . . . . . . . . . 106
6.4 Control board of final prototype. . . . . . . . . . . . . . . . . . . . . . . . 107
6.5 Power module for converter prototype 3. . . . . . . . . . . . . . . . . . . . 108
6.6 Converter prototype 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
(a) Schematic representation of the design . . . . . . . . . . . . . . . . . 109
(b) Assembled converter prototype . . . . . . . . . . . . . . . . . . . . . 109
6.7 Inductor cooler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
(a) Cooling structure for inductor cooler . . . . . . . . . . . . . . . . . . 110
(b) DBC for inductor cooler . . . . . . . . . . . . . . . . . . . . . . . . . 110
(c) Assembled inductor cooler . . . . . . . . . . . . . . . . . . . . . . . . 110
6.8 Enclosed converter prototype. . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.9 Differential-mode EMI spectrum of the converter prototype 3. . . . . . . . 112
6.10 Common-mode EMI spectrum of the converter prototype 3. . . . . . . . . 113
6.11 Measured efficiency of prototypes at Uin = 400 V, fsw = 333 kHz and d =
50 %. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.12 Measured power loss prototype 3. . . . . . . . . . . . . . . . . . . . . . . . 115
A.1 Thermal resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

A.2 Schematic measurement setup. . . . . . . . . . . . . . . . . . . . . . . . . . 126
(a) Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
(b) Actual measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
A.3 Sketch of the voltage, current and temperature waveforms during measure-
ment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
A.4 Etched micro-channel cooler. . . . . . . . . . . . . . . . . . . . . . . . . . . 127
A.5 Etched prototype. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
(a) bottom view of DBC . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
(b) top view of DBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
(c) Assembled prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
A.6 Measurement results of etched micro-channel cooler. . . . . . . . . . . . . . 129
(a) Transient thermal response . . . . . . . . . . . . . . . . . . . . . . . 129
(b) Thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
A.7 3D-printed prototype. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
(a) 3D-printed cooler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
(b) Prototype with attached cooler . . . . . . . . . . . . . . . . . . . . . 131
169
List of Figures
A.8 Measurement results of 3D-printed cooler. . . . . . . . . . . . . . . . . . . 132

(a) Transient thermal response . . . . . . . . . . . . . . . . . . . . . . . 132
(b) Thermal impdeance . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
A.9 Histogram of calculated temperature cycles for MOSFET1 for WLTC. . . . 133
A.10 Temperature amplitude of most significant thermal cycles for MOSFET1
for WLTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
A.11 Cycle time of most significant thermal cycles for MOSFET1 for WLTC. . . 134
A.12 Histogram of calculated temperature cycles. . . . . . . . . . . . . . . . . . 135
A.13 Calculated cycles to failure and degradation. . . . . . . . . . . . . . . . . . 136
(a) Without buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
(b) With buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
A.14 Degradation of most significant thermal cycles. . . . . . . . . . . . . . . . . 136
A.15 Magnitude of models with thermal buffers referenced to no buffers. . . . . 137
A.16 Cycle time of most significant thermal cycles. . . . . . . . . . . . . . . . . 137
A.17 Thermal impedance of integrated structure with an without buffers. . . . . 138
A.18 FRF of thermal model with and without thermal buffers. . . . . . . . . . . 139
A.19 Magnitude of thermal model with thermal buffers referenced to no buffers. 139
A.20 Histogram of calculated temperature cycles. . . . . . . . . . . . . . . . . . 140
A.21 Calculated cycles to failure and degradation. . . . . . . . . . . . . . . . . . 140
(a) Without buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
(b) With buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
A.22 Degradation of most significant thermal cycles. . . . . . . . . . . . . . . . . 141
A.23 Magnitude of models with thermal buffers referenced to no buffers. . . . . 141
A.24 Cycle time of most significant thermal cycles. . . . . . . . . . . . . . . . . 142
A.25 Decomposed shunt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
(a) Cut brass case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
(b) Inner part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
A.26 Resistive foil examined with microscope. . . . . . . . . . . . . . . . . . . . 144
A.27 Shunt with attached BNC port for VNA measurement. . . . . . . . . . . . 144
A.28 VNA measurement setup of shunt. . . . . . . . . . . . . . . . . . . . . . . 145
A.29 Resistive examined with microscope. . . . . . . . . . . . . . . . . . . . . . 146
A.30 Waveform comparison between Rogowski and shunt-based measurement. . 146
(a) Turn off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
(b) Turn on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
A.31 Waveform comparison between Rogowski and shunt-based measurement. . 147
(a) Turn off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
(b) Turn on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
A.32 Turn-on waveforms at 40 A and RG,on = 2.2 Ω. . . . . . . . . . . . . . . . . 148
A.33 Turn-off waveforms at 40 A and RG,on = 2.2 Ω. . . . . . . . . . . . . . . . . 149
A.34 Comparison of diode over-voltages. . . . . . . . . . . . . . . . . . . . . . . 149
A.35 Comparison of turn-off losses at different voltages. . . . . . . . . . . . . . . 150
A.36 Comparison of turn-on losses at different voltages. . . . . . . . . . . . . . . 150
A.37 Comparison of turn-off dv/dt. . . . . . . . . . . . . . . . . . . . . . . . . . . 151
(a) Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
(b) from 10 % to 90 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
170
List of Figures
A.38 Comparison of turn-on dv/dt. . . . . . . . . . . . . . . . . . . . . . . . . . . 151

(a) Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
(b) from 10 % to 90 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
A.39 Comparison of turn-off di/dt. . . . . . . . . . . . . . . . . . . . . . . . . . . 152
(a) Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
(b) from 10 % to 90 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
A.40 Comparison of turn-on di/dt. . . . . . . . . . . . . . . . . . . . . . . . . . . 152
(a) Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
(b) from 10 % to 90 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
A.41 Comparison of maximum values. . . . . . . . . . . . . . . . . . . . . . . . . 153
(a) Over-voltage during turn-off . . . . . . . . . . . . . . . . . . . . . . . 153
(b) Current peak during turn-on . . . . . . . . . . . . . . . . . . . . . . . 153
A.42 Simulated turn-off waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 154
A.43 Simulated turn-on waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 155
A.44 Switching trajectories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
(a) Turn-off trajectory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
(b) Turn-on trajectory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
A.45 Initial technology demonstrator with custom power module. . . . . . . . . 157
A.46 Integrated converter with custom power module. . . . . . . . . . . . . . . . 157
171
172
List of Tables
3.1 Geometry parameters for simulation . . . . . . . . . . . . . . . . . . . . . . 17

3.2 Simulation results for different material combinations . . . . . . . . . . . . 21
3.3 Simulation results for different DBC copper thicknesses . . . . . . . . . . . 23
3.4 Simulation with different number of channels . . . . . . . . . . . . . . . . . 25
3.5 Simulation results for the prototype. . . . . . . . . . . . . . . . . . . . . . 27
3.6 Simulation results of milled cooling structure. . . . . . . . . . . . . . . . . 28
3.7 Measurement results of milled cooling structure. . . . . . . . . . . . . . . . 33
4.1 Material parameters for thermal buffers . . . . . . . . . . . . . . . . . . . . 39
5.1 Simulated stray inductances of power modules. . . . . . . . . . . . . . . . . 71

5.2 Calculated errors for shunt and Rogowski-based measurement. . . . . . . . 81
6.1 Target application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

6.2 Converter prototypes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3 Simulated converter losses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
A.1 Thermal material properties . . . . . . . . . . . . . . . . . . . . . . . . . . 125

A.2 Measurement results of milled cooling structure with water. . . . . . . . . 128
A.3 Measurement results of etched cooling structure. . . . . . . . . . . . . . . . 130
173
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188
Aachener Beiträge des ISEA
ABISEA Band 1 ABISEA Band 7 ABISEA Band 14

Eßer, Albert Langheim, Jochen Backhaus, Klaus
Berührungslose, kombinierte Einzelradantrieb für Spannungseinprägendes
Energie- und Informations- Elektrostraßenfahrzeuge Direktantriebssystem mit
übertragung für bewegliche 1. Aufl. 1993, 213 S. schnelllaufender
Systeme ISBN 3-86073-123-8 geschalteter
1. Aufl. 1992, 129 S. (vergriffen) Reluktanzmaschine
ISBN 3-86073-046-0 1. Aufl. 1995, 146 S.
ABISEA Band 8 ISBN 3-86073-234-X
ABISEA Band 2 Fetz, Joachim (vergriffen)
Vogel, Ulrich Fehlertolerante Regelung
Entwurf und Beurteilung von eines Asynchron- ABISEA Band 15
Verfahren zur Doppelantriebes für ein Reinold, Harry
Hochausnutzung des Rad- Elektrospeicherfahrzeug Optimierung dreiphasiger
Schiene-Kraftschlusses 1. Aufl. 1993, 136 S. Pulsdauermodulations-
durch Triebfahrzeuge ISBN 3-86073-124-6 verfahren
1. Aufl. 1992, 131 S. (vergriffen) 1. Aufl. 1996, 107 S.
ISBN 3-86073-060-6 ISBN 3-86073-235-8
ABISEA Band 9
ABISEA Band 3 Schülting, Ludger ABISEA Band 16
Reckhorn, Thomas Optimierte Auslegung Köpken, Hans-Georg
Stromeinprägendes induktiver Bauelemente für Regelverfahren für
Antriebssystem mit den Mittelfrequenzbereich Parallelschwingkreis-
fremderregter Synchron- 1. Aufl. 1993, 126 S. umrichter
maschine ISBN 3-86073-174-2 1. Aufl. 1996, 125 S.
1. Aufl. 1992, 128 S. (vergriffen) ISBN 3-86073-236-6
ISBN 3-86073-061-4
ABISEA Band 10 ABISEA Band 17
ABISEA Band 4 Skudelny, H.-Ch. Mauracher, Peter
Ackva, Ansgar Stromrichtertechnik Modellbildung und
Spannungseinprägendes 4. Aufl. 1997, 259 S. Verbundoptimierung bei
Antriebssystem mit ISBN 3-86073-189-0 Elektrostraßenfahrzeugen
Synchronmaschine und 1. Aufl. 1996, 192 S.
direkter Stromregelung ABISEA Band 11 ISBN 3-86073-237-4
1. Aufl. 1992, 137 S. Skudelny, H.-Ch.
ISBN 3-86073-062-2 Elektrische Antriebe ABISEA Band 18
3. Aufl. 1997, 124 S. Protiwa, Franz-Ferdinand
ABISEA Band 5 ISBN 3-86073-231-5 Vergleich dreiphasiger
Mertens, Axel Resonanz-Wechselrichter in
Analyse des ABISEA Band 12 Simulation und Messung
Oberschwingungsverhaltens Schöpe, Friedhelm 1. Aufl. 1997, 178 S.
von taktsynchronen Delta - Batterie-Management für ISBN 3-86073-238-2
Modulationsverfahren zur Nickel-Cadmium
Steuerung von Pulsstrom- Akkumulatoren ABISEA Band 19
richtern bei hoher Taktzahl 1. Aufl. 1994, 148 S. Brockmeyer, Ansgar
1. Aufl. 1992, 178 S. ISBN 3-86073-232-3 Dimensionierungswerkzeug
ISBN 3-86073-069-X (vergriffen) für magnetische Bau-
elemente in Stromrichter-
ABISEA Band 6 ABISEA Band 13 anwendungen
Geuer, Wolfgang v. d. Weem, Jürgen 1. Aufl. 1997, 175 S.
Untersuchungen über das Schmalbandige aktive Filter ISBN 3-86073-239-0
Alterungsverhalten von Blei- für Schienentriebfahrzeuge
Akkumulatoren am Gleichspannungs-
1. Aufl. 1993, 97 S. fahrdraht
ISBN 3-86073-097-5 1. Aufl. 1995, 126 S.
ISBN 3-86073-233-1

Apeldoorn, Oscar Karden, Eckhard Schönknecht, Andreas
Simulationsgestützte Bewer- Using low-frequency Topologien und Regelungs-
tung von Steuerverfahren für impedance spectroscopy for strategien für das induktive
netzgeführte Stromrichter characterization, monitoring, Erwärmen mit hohen
mit verringerter Netzrück- and modeling of industrial Frequenz-Leistungs-
wirkung batteries produkten
1. Aufl. 1997, 134 S. 1. Aufl. 2002, 137 S. 1. Aufl. 2004, 157 S.
ISBN 3-86073-680-9 ISBN 3-8265-9766-4 ISBN 3-8322-2408-4

Lohner, Andreas Karipidis, Claus-Ulrich Tolle, Tobias
Batteriemanagement für A Versatile DSP/ FPGA Konvertertopologien für ein
verschlossene Blei-Batterien Structure optimized for aufwandsarmes, zwei-
am Beispiel von Unter- Rapid Prototyping and stufiges Schaltnetzteil zum
brechungsfreien Digital Real-Time Simulation Laden von Batterien aus
Stromversorgungen of Power Electronic and dem Netz
1. Aufl. 1998, 126 S. Electrical Drive Systems 1. Aufl. 2004, 148 S.
ISBN 3-86073-681-7 1. Aufl. 2001, 164 S. ISBN 3-8322-2676-1
ISBN 3-8265-9738-9
Reinert, Jürgen ABISEA Band 28 Götting, Gunther
Optimierung der Betriebs- Kahlen, Klemens Dynamische Antriebs-
eigenschaften von Antrieben Regelungsstrategien für regelung von Elektro-
mit geschalteter Reluktanz- permanentmagnetische straßenfahrzeugen unter
maschine Direktantriebe mit mehreren Berücksichtigung eines
1. Aufl. 1998, 153 S. Freiheitsgraden schwingungsfähigen
ISBN 3-86073-682-5 1. Aufl. 2002, 154 S. Antriebsstrangs
ISBN 3-8322-1222-1 1. Aufl. 2004, 157 S.
ABISEA Band 23 ISBN 3-8322-2804-7
Nagel, Andreas ABISEA Band 29
Leitungsgebundene Inderka, Robert B. ABISEA Band 35
Störungen in der Direkte Drehmoment- Dieckerhoff, Sibylle
Leistungselektronik: regelung Geschalteter Transformatorlose Strom-
Entstehung, Ausbreitung Reluktanzantriebe richterschaltungen für Bahn-
und Filterung 1. Aufl. 2003, 182 S. fahrzeuge am 16 2/3Hz Netz
1. Aufl. 1999, 140 S. ISBN 3-8322-1175-6 1. Aufl. 2004, 147 S.
ISBN 3-86073-683-3 ISBN 3-8322-3094-7
ABISEA Band 30
ABISEA Band 24 Schröder, Stefan ABISEA Band 36
Menne, Marcus Circuit-Simulation Models of Hu, Jing
Drehschwingungen im An- High-Power Devices Based Bewertung von DC-DC-
triebsstrang von Elektro- on Semiconductor Physics Topologien und Optimierung
straßenfahrzeugen - 1. Aufl. 2003, 123 S. eines DC-DC-Leistungs-
Analyse und aktive ISBN 3-8322-1250-7 moduls für das 42-V-Kfz-
Dämpfung Bordnetz
1. Aufl. 2001, 169 S. ABISEA Band 31 1. Aufl. 2004, 148 S.
ISBN 3-86073-684-1 Buller, Stephan ISBN 3-8322-3201-X
Impedance-Based Simu-
ABISEA Band 25 lation Models for Energy ABISEA Band 37
von Bloh, Jochen Storage Devices in Detjen, Dirk-Oliver
Multilevel-Umrichter zum Advanced Automotive Characterization and
Einsatz in Mittelspannungs- Power Systems Modeling of Si-Si Bonded
Gleichspannungs- 1. Aufl. 2003, 138 S. Hydrophobie Interfaces for
Übertragungen ISBN 3-8322-1225-6 Novel High-Power BIMOS
1. Aufl. 2001, 137 S. Devices
ISBN 3-86073-685-X 1. Aufl. 2004, 135 S.
ISBN 3-8322-2963-9

Walter, Jörg Fiedler, Jens König, Andreas
Simulationsbasierte Zuver- Design of Low-Noise High Temperature DC-to-DC
lässigkeitsanalyse in der Switched Reluctance Drives Converters for Downhole
modernen Leistungs- 1. Aufl. 2007, 176 S. Applications
elektronik ISBN 978-3-8322-5864-1 1. Aufl. 2009, 154 S.
1. Aufl. 2004, 121 S. ISBN 978-3-8322-8489-3
ISBN 3-8322-3481-0 ABISEA Band 45
FuengwarodsakuI, Nisai ABISEA Band 52
ABISEA Band 39 Predictive PWM-based Dick, Christian Peter
Schwarzer, Ulrich Direct Instantaneous Torque Multi-Resonant Converters
IGBT versus GCT in der Control for Switched as Photovoltaic Module-
Mittelspannungsanwendung Reluctance Machines Integrated Maximum Power
- ein experimenteller und 1. Aufl. 2007, 141 S. Point Tracker
simulativer Vergleich ISBN 978-3-8322-6210-5 1. Aufl. 2010, 182 S.
1. Aufl. 2005, 170 S. ISBN 978-3-8322-9199-0
ISBN 3-8322-4489-1 ABISEA Band 46
Meyer, Christoph ABISEA Band 53
ABISEA Band 40 Key Components for Future Kowal, Julia
Bartram, Markus Offshore DC Grids Spatially resolved
IGBT-Umrichtersysteme für 1. Aufl. 2007, 187 S. impedance of nonlinear
Windkraftanlagen: Analyse ISBN 978-3-8322-6571-7 inhomogeneous devices:
der Zyklenbelastung, Mo- using the example of lead-
dellbildung, Optimierung und ABISEA Band 47 acid batteries
Lebensdauervorhersage Fujii, Kansuke 1. Aufl. 2010, 203 S.
1. Aufl. 2006, 185 S. Characterization and ISBN 978-3-8322-9483-0
ISBN 3-8322-5039-5 Optimization of Soft-
Switched Multi-Level ABISEA Band 54
ABISEA Band 41 Converters for STATCOMs Roscher, Michael Andreas
Ponnaluri, Srinivas 1. Aufl. 2008, 199 S. Zustandserkennung von
Generalized Design, ISBN 978-3-8322-6981-4 LiFeP04-Batterien für
Analysis and Control of Hybrid- und Elektro-
Grid side converters with ABISEA Band 48 fahrzeuge
integrated UPS or Islanding Carstensen, Christian 1. Aufl. 2011, 186 S.
functionality Eddy Currents in Windings ISBN 978-3-8322-9738-1
1. Aufl. 2006, 163 S. of Switched Reluctance
ISBN 3-8322-5281-9 Machines ABISEA Band 55
1. Aufl. 2008, 179 S. Hirschmann, Dirk
ABISEA Band 42 ISBN 978-3-8322-7118-3 Highly Dynamic
Jacobs, Joseph Piezoelectric Positioning
Multi-Phase Series ABISEA Band 49 1. Aufl. 2011, 146 S.
Resonant DC-to-DC Bohlen, Oliver ISBN 978-3-8322-9746-6
Converters Impedance-based battery
1. Aufl. 2006, 185 S. monitoring ABISEA Band 56
ISBN 3-8322-5532-X 1. Aufl. 2008, 190 S. Rigbers, Klaus
ISBN 978-3-8322-7606-5 Highly Efficient Inverter
ABISEA Band 43 Architectures for Three-
Linzen, Dirk ABISEA Band 50 Phase Grid Connection
Impedance-Based Loss Thele, Marc of Photovoltaic Generators
Calculation and Thermal A contribution to the 1. Aufl. 2011, 244 S.
Modeling of Electrochemical modelling of the charge ISBN 978-3-8322-9816-9
Energy Storage Devices for acceptance of lead-acid
Design Considerations of batteries - using frequency ABISEA Band 57
Automotive Power Systems and time domain based Kasper, Knut
1. Aufl. 2006, 185 S. concepts Analysis and Control of the
ISBN 3-8322-5706-3 1. Aufl. 2008, 165 S. Acoustic Behavior of
ISBN 978-3-8322-7659-1 Switched Reluctance Drives
1. Aufl. 2011, 205 S.
ISBN 978-3-8322-9869-2

Köllensperger, Peter Neuhaus, Christoph R. Richter, Sebastian
The Internally Commutated Schaltstrategien für Digitale Regelung von PWM
Thyristor - Concept, Design Geschaltete Reluktanz- Wechselrichtern mit
and Application antriebe mit kleinem niedrigen Trägerfrequenzen
1. Aufl. 2011, 214 S. Zwischenkreis 1. Aufl. 2014, 126 S.
ISBN 978-3-8322-9909-5 1. Aufl. 2012, 133 S. ISBN 978-3-8440-2641-2
ISBN 978-3-8440-1487-7
Schoenen, Timo ABISEA Band 65 Bösing, Matthias
Einsatz eines DC/DC-Wand- Butschen, Thomas Acoustic Modeling of
lers zur Spannungs- Dual-ICT- A Clever Way to Electrical Drives - Noise and
anpassung zwischen Antrieb Unite Conduction and Vibration Synthesis based
und Energiespeicher in Switching Optimized on Force Response
Elektro-und Hybrid- Properties in a Single Wafer Superposition
fahrzeugen 1. Aufl. 2012, 168 S. 1. Aufl. 2014, 188 S.
1. Aufl. 2011, 128 S. ISBN 978-3-8440-1771-7 ISBN 978-3-8440-2752-5
ISBN 978-3-8440-0622-3
ABISEA Band 60 Plum, Thomas Waag, Wladislaw
Hennen, Martin Design and Realization of Adaptive algorithms for
Switched Reluctance Direct High-Power MOS Turn-Off monitoring of lithium-ion
Drive with Integrated Thyristors batteries in electric vehicles
Distributed Inverter 1. Aufl. 2013, 113 S. 1. Aufl. 2014, 232 S.
1. Aufl. 2012, 141 S. ISBN 978-3-8440-1884-4 ISBN 978-3-8440-2976-5
ISBN 978-3-8440-0731-2
ABISEA Band 61 Kiel, Martin Sanders, Tilman
van Treek, Daniel Impedanzspektroskopie an Spatially Resolved Electrical
Position Sensorless Torque Batterien unter besonderer In-Situ Measurement
Control of Switched Berücksichtigung von Techniques for Fuel Cells
Reluctance Machines Batteriesensoren für den 1. Aufl. 2014, 126 S.
1. Aufl. 2012, 144 S. Feldeinsatz ISBN 978-3-8440-3121-8
ISBN 978-3-8440-1014-5 1. Aufl. 2013, 226 S.
ISBN 978-3-8440-1973-5 ABISEA Band 74
ABISEA Band 62 Baumhöfer, Thorsten
Bragard, Michael ABISEA Band 68 Statistische Betrachtung
The Integrated Emitter Turn- Brauer, Helge experimenteller Alterungs-
Off Thyristor. An Innovative Schnelldrehender untersuchungen an Lithium-
MOS-Gated High-Power Geschalteter Reluktanz- Ionen Batterien
Device antrieb mit extremem 1. Aufl. 2015, 157 S.
1. Aufl. 2012, 164 S. Längendurchmesser- ISBN 978-3-8440-3423-3
ISBN 978-3-8440-1152-4 verhältnis
1. Aufl. 2013, 192 S. ABISEA Band 75
ABISEA Band 63 ISBN 978-3-8440-2345-9 Andre, Dave
Gerschler, Jochen B. Systematic Characterization
Ortsaufgelöste Modellbil- ABISEA Band 69 of Ageing Factors for High-
dung von Lithium-Ionen- Thomas, Stephan Energy Lithium-Ion Cells
Systemen unter spezieller A Medium-Voltage Multi- and Approaches for Lifetime
Berücksichtigung der Level DC/DC Converter with Modelling Regarding an
Batteriealterung High Voltage Transformation Optimized Operating
1. Aufl. 2012, 334 S. Ratio Strategy in Automotive
ISBN 978-3-8440-1307-8 1. Aufl. 2014, 226 S. Applications
ISBN 978-3-8440-2605-4 1. Aufl. 2015, 196 S.
ISBN 978-3-8440-3587-2

Merei, Ghada Lunz, Benedikt Lehner, Susanne
Optimization of off-grid Deutschlands Stromver- Reliability Assessment of
hybrid PV-wind-diesel power sorgung im Jahr 2050 Lithium-Ion Battery Systems
supplies with multi- Ein szenariobasiertes with Special Emphasis on
technology battery systems Verfahren zur vergleich- Cell Performance
taking into account battery enden Bewertung von Distribution
aging Systemvarianten und 1. Aufl. 2017, 184 S.
1. Aufl. 2015, 184 S. Flexibilitätsoptionen ISBN 978-3-8440-5090-5
ISBN 978-3-8440-4148-4 1. Aufl. 2016, 187 S.
ISBN 978-3-8440-4627-4 ABISEA Band 89
ABISEA Band 77 Käbitz, Stefan
Schulte, Dominik ABISEA Band 83 Untersuchung der Alterung
Modellierung und experi- Hofmann, Andreas G. von Lithium-Ionen-Batterien
mentelle Validierung der Direct Instantaneous Force mittels Elektroanalytik und
Alterung von Blei-Säure Control: Key to Low-Noise elektrochemischer
Batterien durch inhomogene Switched Reluctance Impedanzspektroskopie
Stromverteilung und Traction Drives 1. Aufl. 2016, 258 S.
Säureschichtung 1. Aufl. 2016, 228 S. DOI: 10.18154/RWTH-2016-
1. Aufl. 2016, 165 S. ISBN 978-3-8440-4715-8 12094
ISBN 978-3-8440-4216-0
ABISEA Band 78 Budde-Meiwes, Heide Witzenhausen, Heiko
Schenk, Mareike Dynamic Charge Elektrische Batteriespeicher-
Simulative Untersuchung Acceptance of Lead-Acid modelle: Modellbildung,
der Wicklungsverluste in Batteries for Micro-Hybrid Parameteridentifikation und
Geschalteten Reluktanz- Automotive Applications Modellreduktion
maschinen 1. Aufl. 2016, 157 S. 1. Aufl. 2017, 266 S.
1. Aufl. 2016, 126 S. ISBN 978-3-8440-4733-2 DOI: 10.18154/RWTH-2017-
ISBN 978-3-8440-4282-5 03437
ABISEA Band 85
ABISEA Band 79 Engel, Stefan P. ABISEA Band 91
Wang, Yu Thyristor-Based High-Power Münnix, Jens
Development of Dynamic On-Load Tap Changers Einfluss von Stromstärke
Models with Spatial Control under Harsh Load und Zyklentiefe auf
Resolution for Electro- Conditions graphitische Anoden
chemical Energy Converters 1. Aufl. 2016, 156 S. 1. Aufl. 2017, 171 S.
as Basis for Control and ISBN 978-3-8440-4986-2 DOI: 10.18154/RWTH-2017-
Management Strategies 01915
1. Aufl. 2016, 188 S. ABISEA Band 86
ISBN 978-3-8440-4303-7 Van Hoek, Hauke ABISEA Band 92
Design and Operation Pilatowicz, Grzegorz
ABISEA Band 80 Considerations of Three- Failure Detection and
Ecker, Madeleine Phase Dual Active Bridge Battery Management
Lithium Plating in Lithium- Converters for Low-Power Systems of Lead-Acid
Ion Batteries: Applications with Wide Batteries for Micro-
An Experimental and Voltage Ranges Hybrid Vehicles
Simulation Approach 1. Aufl. 2017, 231 S. 1. Aufl. 2017, 212 S.
1. Aufl. 2016, 154 S. ISBN 978-3-8440-5011-0 DOI: 10.18154/RWTH-2017-
ISBN 978-3-8440-4525-3 09156
ABISEA Band 87
ABISEA Band 81 Diekhans, Tobias ABISEA Band 93
Zhou, Wei Wireless Charging of Drillkens, Julia
Modellbasierte Auslegungs- Electric Vehicles - a Pareto- Aging in Electrochemical
methode von Tempe- Based Comparison of Power Double Layer Capacitors:
rierungssystemen für Electronic Topologies An Experimental and
Hochvolt-Batterien in 1. Aufl. 2017, 151 S. Modeling Approach
Personenkraftfahrzeugen ISBN 978-3-8440-5048-6 1. Aufl. 2017, 179 S.
1. Aufl. 2016, 175 S. DOI: 10.18154/RWTH-2018-
ISBN 978-3-8440-4589-5 223434

Magnor, Dirk Masomtob, Manop Warnecke, Alexander J.
Globale Optimierung netz- A New Conceptual Design Degradation Mechanisms in
gekoppelter PV-Batterie- of Battery Cell with an NMC Based Lithium-Ion
systeme unter besonderer Internal Cooling Channel Batteries
Berücksichtigung der 1. Aufl. 2017, 167 S. 1. Aufl. 2017, 158 S.
Batteriealterung DOI: 10.18154/RWTH-2018- DOI: 10.18154/RWTH-2017-
1. Aufl. 2017, 210 S. 223281 09646
DOI: 10.18154/RWTH-2017-
06592 ABISEA Band 100 ABISEA Band 106
Marongiu, Andrea Taraborrelli, Silvano
ABISEA Band 95 Performance and Aging Bidirectional Dual Active
Iliksu, Merve Diagnostic on Lithium Iron Bridge Converter using a
Elucidation and Comparison Phosphate Batteries for Tap Changer for Extended
of the Effects of Lithium Electric Vehicles and Voltage Ranges
Salts on Discharge Vehicle-to-Grid Strategies 1. Aufl. 2017, 94 S.
Chemistry of Nonaqueous 1. Aufl. 2017, 222 S. DOI: 10.18154/RWTH-2018-
Li-O2 Batteries DOI: 10.18154/RWTH-2017- 228242
1. Aufl. 2018, 160 S. 09944
DOI: 10.18154/RWTH-2018- ABISEA Band 107
223782 ABISEA Band 101 Sarriegi, Garikoitz
Gitis, Alexander SiC and GaN
ABISEA Band 96 Flaw detection in the coating Semiconductors: The Future
Schmalstieg, Johannes process of lithium-ion Enablers of Compact and
Physikalisch- battery electrodes with Efficient Converters for
elektrochemische acoustic guided waves Electromobility
Simulation von Lithium- 1. Aufl. 2017, 109 S. 1. Aufl. 2017, 106 S.
Ionen-Batterien: DOI: 10.18154/RWTH-2017- DOI: 10.18154/RWTH-2018-
Implementierung, 099519 227548
Parametrierung und
Anwendung ABISEA Band 102 ABISEA Band 108
1. Aufl. 2017, 168 S. Neeb, Christoph Senol, Murat
DOI: 10.18154/RWTH-2017- Packaging Technologies for Drivetrain Integrated Dc-Dc
04693 Power Electronics in Converters utilizing Zero
Automotive Applications Sequence Currents
ABISEA Band 97 1. Aufl. 2017, 132 S. 1. Aufl. 2017, 134 S.
Soltau, Nils DOI: 10.18154/RWTH-2018- DOI: 10.18154/RWTH-2018-
High-Power Medium- 224569 226170
Voltage DC-DC Converters:
Design, Control and ABISEA Band 103 ABISEA Band 109
Demonstration Adler, Felix Kojima, Tetsuya
1. Aufl. 2017, 176 S. A Digital Hardware Platform Efficiency Optimized Control
DOI: 10.18154/RWTH-2017- for Distributed Real-Time of Switched Reluctance
04084 Simulation of Power Machines
Electronic Systems 1. Aufl. 2017, 142 S.
ABISEA Band 98 1. Aufl. 2017, 156 S. DOI: 10.18154/RWTH-2018-
Stieneker, Marco DOI: 10.18154/RWTH-2017- 226697
Analysis of Medium-Voltage 10761
Direct-Current Collector ABISEA Band 110
Grids in Offshore Wind ABISEA Band 104 Lewerenz, Meinert
Parks Becker, Jan Dissection and Quantitative
1. Aufl. 2017, 144 S. Flexible Dimensionierung Description of Aging of
DOI: 10.18154/RWTH-2017- und Optimierung hybrider Lithium-Ion Batteries Using
04667 Lithium-Ionenbatterie- Non-Destructive Methods
speichersysteme mit Validated by Post-Mortem-
verschiedenen Auslegungs- Analyses
zielen 1. Aufl. 2018, 139 S.
1. Aufl., 2017, 157 S. DOI: 10.18154/RWTH-2018-
DOI: 10.18154/RWTH-2017- 228663
09278

Büngeler, Johannes Biskoping, Matthias Ayeng’o, Sarah Paul
Optimierung der Verfüg- Discrete Modeling and Control Optimization of number of PV
barkeit und der Lebens- of a versatile Power Electronic cells connected in series for a
dauer von Traktionsbatterien Test Bench with Special direct-coupled PV system with
für den Einsatz in Flurförder- Focus on Central Photovoltaic lead-acid and lithium-ion
fahrzeugen Inverter Testing batteries
1. Aufl. 2018, 171 S. 1. Aufl. 2018, 236 S. 1. Aufl. 2019, 114 S.
DOI: 10.18154/RWTH-2018- DOI: 10.18154/RWTH-2019- DOI: 10.18154/RWTH-2019-
226569 03346 01843

Wegmann, Raphael Schubert, Michael Koschik, Stefan Andreas
Betriebsstrategien und High-Precision Torque Control Permanenterregte Synchron-
Potentialbewertung hybrider of Inverter-Fed Induction maschinen mit verteilter
Batteriespeichersysteme in Machines with Instantaneous Einzelzahnsteuerung -
Elektrofahrzeugen Phase Voltage Sensing Regelkonzepte und Betriebs-
1. Auflage 2018, 184 S. 1. Aufl. 2019, 221 S. strategien für hochintegrierte
DOI: 10.18154/RWTH-2018- DOI: 10.18154/RWTH-2018- Antriebssysteme
228833 231364 1. Aufl. 2019, 158 S.
DOI: 10.18154/RWTH-2019-
ABISEA Band 113 ABISEA Band 119 03446
Nordmann, Hannes Van der Broeck, Christoph
Batteriemanagementsysteme Methodology for Thermal ABISEA Band 124
unter besonderer Berück- Modeling, Monitoring and Farmann, Alexander
sichtigung von Fehlererken- Control of Power Electronic A comparative study of
nung und Peripherieanalyse Modules reduced-order equivalent
1. Aufl. 2018, 222 S. 1. Aufl. 2019, 290 S. circuit models for state-of-
DOI: 10.18154/RWTH-2018- DOI: 10.18154/RWTH-2019- available-power prediction of
228763 01370 lithium-ion batteries in electric
vehicles
ABISEA Band 114 ABISEA Band 120 1. Aufl. 2019, 214 S.
Engelmann, Georges Hust, Friedrich Emanuel DOI: 10.18154/RWTH-2019-
Reducing Device Stress and Physico-chemically motivated 04700
Switching Losses Using parameterization and
Active Gate Drivers and modelling of real-time capable ABISEA Band 125
Improved Switching Cell lithium-ion battery models – Mareev, Ivan
Design a case study on the Tesla Analyse und Bewertung von
1. Aufl. 2018, 195 S. Model S battery batteriegetriebenen, ober-
DOI: 10.18154/RWTH-2018- 1. Aufl. 2019, 203 S. leitungsversorgten und
228973 DOI: 10.18154/RWTH-2019- brennstoffzellengetriebenen
00249 Lastkraftwagen für den
ABISEA Band 115 Einsatz im Güterfernverkehr
Klein-Heßling, Annegret ABISEA Band 121 in Deutschland
Active DC-Power Filters for Ralev, Iliya 1. Aufl. 2019, 158 S.
Switched Reluctance Drives Accurate Torque Control of DOI: 10.18154/RWTH-2019-
during Single-Pulse Operation Position Sensorless Switched 04698
1. Aufl. 2018, 166 S. Reluctance Drives
DOI: 10.18154/RWTH-2018- 1. Aufl. 2019, 154 S. ABISEA Band 126
231030 DOI: 10.18154/RWTH-2019- Qi, Fang
03071 Online Model-predictive
ABISEA Band 116 Thermal Management of
Burkhart, Bernhard Inverter-fed Electrical
Switched Reluctance Machines
Generator for Range Extender 1. Aufl. 2019, 154 S.
Applications - Design, Control DOI: 10.18154/RWTH-2019-
and Evaluation 08304
1. Aufl. 2018, 194 S.
DOI: 10.18154/RWTH-2019-
00025

Kairies, Kai-Philipp Titiz, Furkan Kaan Sabet, Pouyan Shafiei
Auswirkungen dezentraler A Three-phase Low-voltage Analysis of Predominant
Solarstromspeicher auf Grid-connected Current Processes in Electrochemical
Netzbetreiber und Source Inverter Impedance Spectra and
Energieversorger 1. Aufl. 2019, 128 S. Investigation of Aging
1. Aufl. 2019, 140 S. DOI: 10.18154/RWTH-2020- Processes of Lithium-Ion
DOI: 10.18154/RWTH-2019- 00458 Batteries with Layered Oxide
06706 Cathodes and Graphitic
ABISEA Band 134 Anodes
ABISEA Band 128 Wünsch, Martin 1. Aufl. 2020, 136 S.
Fleischer, Michael Separation der Kathoden- DOI: 10.18154/RWTH-2020-
Traction control for Railway alterung in Lithium-Ionen- 07683
Vehicles Batteriezellen mittels
1. Aufl. 2019, 162 S. elektrochemischer ABISEA Band 139
DOI: 10.18154/RWTH-2019- Impedanzspektroskopie Angenendt, Georg
10570 1. Aufl. 2019, 177 S. Operation, Optimization and
DOI: 10.18154/RWTH-2019- Additional Market
ABISEA Band 129 11017 Participation of Households
Teuber, Moritz with PV Battery Storage
Lifetime Assessment and ABISEA Band 135 System and Power-to-Heat
Degradation Mechanisms in Badeda, Julia Application
Electric Double-Layer Modeling and Steering of 1. Aufl. 2020, 221 S.
Capacitors Multi-Use Operation with DOI: 10.18154/RWTH-2020-
1. Aufl. 2019, 150 S. Uninterruptible Power Supply 05200
DOI: 10.18154/RWTH-2019- Systems - utilizing the
10071 example of lead-acid batteries ABISEA Band 140
1. Aufl. 2020, 282 S. Oberdieck, Karl Friedrich
ABISEA Band 130 DOI: 10.18154/RWTH-2020- Measurement and Mitigation
Bußar, Christian 05456 of Electromagnetic Emissions
Investigation of Optimal of Propulsion Inverters for
Transformation Pathways ABISEA Band 136 Electric Vehicles
towards 2050 for the Kleinsteinberg, Björn 1. Aufl. 2020, 181 S.
Successful Implementation of Energy Efficiency Increase of DOI: 10.18154/RWTH-2020-
a Sustainable Reduction of a Vanadium Redox Flow 09215
Carbon Emissions from Battery with a Power-Based
Power Generation Model ABISEA Band 141
1. Aufl. 2019, 204 S. 1. Aufl. 2020, 163 S. Bubert, Andreas Martin
DOI: 10.18154/RWTH-2019- DOI: 10.18154/RWTH-2020- Optimierung des elektrischen
09975 06092 Antriebsstrangs von
Elektrofahrzeugen mit
ABISEA Band 131 ABISEA Band 137 Betrachtung parasitärer
Wienhausen, Arne Hendrik Cai, Zhuang Ströme innerhalb der
High Integration of Power Optimization of dimension and elektrischen Maschine
Electronic Converters enabled operation strategy for a wind- 1. Aufl. 2020, 215 S.
by 3D Printing battery energy system in DOI: 10.18154/RWTH-2020-
1. Aufl. 2019, 146 S. German electricity market 09556
DOI: 10.18154/RWTH-2019- under consideration of battery
08746 ageing process ABISEA Band 142
1. Aufl. 2020, 144 S. Fleischer, Christian Georg
ABISEA Band 132 DOI: 10.18154/RWTH-2020- Model-Driven Software
Kwiecien, Monika 06525 Development and Verification
Electrochemical Impedance Solutions for Safety Critical
Spectroscopy on Lead-Acid
Battery Management Systems
Cells during Aging 1. Aufl. 2021, 356 S.
1. Aufl. 2019, 138 S. DOI: 10.18154/RWTH-2021-
DOI: 10.18154/RWTH-2019-
00436
09480

Arzberger, Arno Münderlein, Jeanette
Thermografische Methoden Numerische Methodik zur
zur zerstörungsfreien Auslegung eines Hybriden
Messung der anisotropen Speichersystems mit
Wärmeleitfähigkeit von Multinutzen“
Lithium-Ionen Zellen 1. Aufl. 2020, 221 S.
1. Aufl. 2020, 131 S. DOI: 10.18154/RWTH-2021-
DOI: 10.18154/RWTH-2021- 00867
00479
ABISEA Band 150
ABISEA Band 144 Merten, Michael
Lange, Tobias Participation of Battery
Oberwellenbasierte Model- Storage Systems in the
lierung, Regelung und Aus- Secondary Control Reserve
legung von Permanent- Market
magnet- und Reluktanz- 1. Aufl. 2020, 187 S.
Synchronmaschinen DOI: 10.18154/RWTH-2021-
1. Aufl. 2020, S. 01029
DOI: 10.18154/RWTH-2021-
ABISEA Band 151
ABISEA Band 145 Ge, Lefei
Weiss, Claude Performance Enhancement
Fault Tolerant Switched of Switched Reluctance
Reluctance Machines with Machines for High-speed
Distributed Inverters – Back-up Generators
Modeling and Control 1. Aufl. 2020, 152 S.
1. Aufl. 2020, S. DOI: 10.18154/RWTH-2020-
DOI: 10.18154/RWTH-2021- 11546

Huck, Moritz Neubert, Markus
Modelling the Transient Modeling, Synthesis and
Behaviour of Lead-Acid Operation of Multiport-Active
Batteries: Electrochemical Bridge Converters
Impedance of Adsorbed 1. Aufl. 2020, 227 S.
Species DOI: 10.18154/RWTH-2020-
1. Aufl. 2020, 151 S. 10814
DOI: 10.18154/RWTH-2020-
08362 ABISEA Band 153
Schülting, Philipp
ABISEA Band 147 Optimierte Auslegung von
Willenberg, Lisa hochintegrierten und
Volumenausdehnung und bidirektionalen Onboard
ihre Auswirkungen auf die GaN-Ladegeräten
Alterung einer zylindrischen 1. Aufl. 2020, 158 S.
Lithium-Ionen-Batterie DOI: 10.18154/RWTH-2020-
1. Aufl. 2020, S. 09771
DOI: 10.18154/RWTH-2021-
ABISEA Band 154
ABISEA Band 148 Sewergin, Alexander
Rogge, Matthias Design Challenges and
Electrification of Public Solutions for the Practical
Transport Bus Fleets with Application of SiC Power
Battery Electric Busses Mo-duls – Exemplified by an
1. Aufl. 2020, 161 S. Automotive DC-DC Con-
DOI: 10.18154/RWTH-2021- verter
02146 1. Aufl. 2021, S.
DOI: 10.18154/RWTH-2021-
This work investigates the design optimization of tailor-made
power modules for power electronic applications yielding a
maximum device utilization of modern wide bandgap devices.
The superior electrical characteristics of silicon carbide devices

enable converters with higher current densities, faster switch-
ing transients and increased switching frequencies. Due to the
higher current densities, the cooling of silicon carbide devices is
challenging. Micro-channels investigated in this thesis provide a
low-volume but effective cooling solution that is able to dissipate
highest heat flux densities. A low-inductive power module is de-
signed with micro-channels integrated into the baseplate. The
module is optimized for the target application and topology of
a synchronous boost converter operated at a very high switch-
ing frequency. The low-inductive design allows utilizing the full
potential of silicon carbide devices that otherwise are limited by
the parasitic inductances and capacitances of the module. To
demonstrate the advantages of the presented approach on a
system level, the power module is combined with passive com-
ponents, sensors and a control circuitry to build a dc-dc convert-
er. Despite its hard-switching operation mode, it achieves a high
switching frequency of 333 kHz and an efficiency of 98.2 %. The
converter reaches a power density of 75 kW/l.
The resulting power converter highlights the potential of electri-

cally and thermally optimized, application-specific power mod-
ules that integrate the silicon carbide devices with gate-drivers,
cooling structures and capacitors. For the development of elec-
tric vehicles and more electric aircrafts, such modules present
a unique opportunity to realize fast switching dc-dc converters
with highest power densities.
ISSN 1437-675X

Doncker学生博士论文 Exploiting the Full Potential of Silicon Carbide Devices via Optimized Highly Integrated Power Modules

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Alexander Stippich

Exploiting the Full Potential of

Aachener Beiträge des ISEA Band 155

Von der Fakultät für Elektrotechnik und Informationstechnik

Diese Dissertation ist auf den Internetseiten

Copyright Alexander Stippich and ISEA 2021

Institute for Power Electronics and Electrical Drives (ISEA)

Die vorliegende Dissertation entstand während meiner Tätigkeit als Wissenschaftlicher

Aachen, April 2021 Alexander Stippich

2 State of the Art and Literature Review 7

3 Micro-Channel Cooling Structures for SiC MOSFETs 15

4 Thermal Buffers for Enhanced Lifetime 37

5 Application-Specific Power Module 57

6 Highly-Integrated DC-DC-Converter 103

7 Conclusions and Outlook 119

List of Figures 165

List of Tables 173

A conventional drive-train architecture of electric vehicles exhibits a single high-voltage

Outline of this Thesis

This thesis is structured in 6 major chapters, which are briefly summarized.

Chapter 2: State of the Art and Literature Review

Chapter 3: Cooling Structures for SiC MOSFETs

Based on the literature review, a micro-channel cooling structure is investigated as a

Chapter 4: Thermal Buffers for Enhanced Lifetime

Chapter 5: Application-Specific Power Module

Using conventional manufacturing techniques only, a low-inductive, highly-integrated SiC

Chapter 6: Highly-Integrated DC-DC-Converter

Chapter 7: Conclusion and Outlook

interface material baseplate

Figure 2.1: Conventional package structure.

Packaging of power semiconductors is a multi-physics design problem. Packaging requires

A schematic representation of a state-of-the-art package design for insulated-gate bipolar

Figure 2.2: SiC power module from Wolf-

For demonstration purposes, a comparable 35 nH half-bridge power module is manufac-

DC+ bond wire

Figure 2.5: Layouts of lateral SiC power modules

2.1 Literature Review of Packaging Technologies

As a consequence of the non-optimal electrical performance outlined in the previous sec-

2.1.1 Conventional Packaging Techniques

In [183], a full-bridge module is designed for an unidirectional bridgeless-boost topology for

As a summary, low-inductive power modules can be achieved with conventional packaging

2.1.2 Advanced Packaging Techniques

2.2 Literature Review of Fluid Cooling Structures

Due to the advancement in additive manufacturing, cooling structures can be fabricated

Figure 3.1: Micro-channel cooler milled into baseplate.

3.1 Simulation of Micro-Channel Structure

Conventional solder with a thermal conductivity of 50.9 W/mK and a thickness of 50 µm

Table 3.1: Geometry parameters for simulation

Figure 3.2: Temperature rendering of the cooling structure.

Figure 3.3: Cross-sectional contour plot of temperature.

3.1.1 Investigation of Different Materials

Table 3.2: Simulation results for different material combinations

junction temperature thermal resistance

3.1.2 Geometry Analysis

Figure 3.5: Investigated parameters.

Table 3.3: Simulation results for different DBC copper thicknesses

copper thickness junction temperature thermal resistance

Figure 3.6: Results of parameter sweep.

Figure 3.7: Investigated channel parameters.

Junction temperature in °C Pumping power in W

Figure 3.8: Channel width and height simulation results.

Table 3.4: Simulation with different number of channels

3.2 Experimental Verification