Sie sind auf Seite 1von 39

www.vinafix.vn

http://laptop-motherboard-schematic.blogspot.com/

www.vinafix.vn http://laptop-motherboard-schematic.blo gspot.com/
5 4 3 2 1 Sandy Bridge Processor (DMI,PEG,FDI) Sandy Bridge Processor (CLK,MISC,JTAG) U15A U15A
5
4
3
2
1
Sandy Bridge Processor (DMI,PEG,FDI)
Sandy Bridge Processor (CLK,MISC,JTAG)
U15A
U15A
U15B
U15B
J22
PEG_COMP
PEG_ICOMPI
J21
PEG_ICOMPO
PEG_COMP connect to PIN H22&J22 W:4mils/S:15mils/L: 500mils.
PEG_COMP connect to PIN J21 W:12mils/S:15mils/L: 500mils.
B27
H22
6
DMI_TXN0
DMI_RX#[0]
PEG_RCOMPO
B25
A28
6
DMI_TXN1
DMI_RX#[1]
PEG_RX#[0
7]
14
BCLK
CLK_CPU_BCLKP
8
A25
C26
A27
6
DMI_TXN2
DMI_RX#[2]
7
H_SNB_IVB#
SNB_IVB#
BCLK#
CLK_CPU_BCLKN
8
B24
K33
PEG_RX#0
6
DMI_TXN3
DMI_RX#[3]
PEG_RX#[0]
M35
PEG_RX#1
PEG_RX#[1]
B28
L34
PEG_RX#2
SNB_IVB# N.A at SNB EDS #27637 0.7v1
SKTOCC#
AN34
6
DMI_TXP0
DMI_RX[0]
PEG_RX#[2]
TP4TP4
SKTOCC#
D
B26
PEG_RX#3
D
J35
A16
CLK_DPLL_SSCLKP
6
DMI_TXP1
DMI_RX[1]
PEG_RX#[3]
DPLL_REF_SSCLK
A24
J32
PEG_RX#4
A15
CLK_DPLL_SSCLKN
6
DMI_TXP2
DMI_RX[2]
PEG_RX#[4]
DPLL_REF_SSCLK#
B23
H34
PEG_RX#5
6
DMI_TXP3
DMI_RX[3]
PEG_RX#[5]
H31
PEG_RX#6
PEG_RX#[6]
G21
G33
PEG_RX#7
TP_CATERR#
AL33
6
DMI_RXN0
DMI_TX#[0]
PEG_RX#[7]
TP2TP2
CATERR#
E22
G30
6
DMI_RXN1
DMI_TX#[1]
PEG_RX#[8]
F21
F35
Placement close to EC.
6
DMI_RXN2
DMI_TX#[2]
PEG_RX#[9]
D21
E34
6
DMI_RXN3
DMI_TX#[3]
PEG_RX#[10]
E32
R386
R386
43_4
43_4
H_PECI
AN33
R8
CPU_DRAMRST#
PEG_RX#[11]
29
EC_PECI
PECI
SM_DRAMRST#
G22
D33
6
DMI_RXP0
DMI_TX[0]
PEG_RX#[12]
D22
D31
6
DMI_RXP1
DMI_TX[1]
PEG_RX#[13]
F20
B33
6
DMI_RXP2
DMI_TX[2]
PEG_RX#[14]
C21
C32
R146
R146
56.2/F_4
56.2/F_4
H_PROCHOT#_R
AL32
AK1
SM_RCOMP_0
R143
R143
140/F_4
140/F_4
6
DMI_RXP3
DMI_TX[3]
PEG_RX#[15]
PEG_RX[0
7]
14
29,33
H_PROCHOT#
PROCHOT#
SM_RCOMP[0]
A5
SM_RCOMP_1
R318
R318
26.1/F_4
26.1/F_4
SM_RCOMP[1]
J33
PEG_RX0
A4
SM_RCOMP_2
R316
R316
200/F_4
200/F_4
PEG_RX[0]
SM_RCOMP[2]
L35
PEG_RX1
PEG_RX[1]
K34
PEG_RX2
R148
R148
0_4
0_4
PM_THRMTRIP#_R
AN32
PEG_RX[2]
9,29
PM_THRMTRIP#
THERMTRIP#
A21
H35
PEG_RX3
6
FDI_TXN0
FDI0_TX#[0]
PEG_RX[3]
H19
H32
PEG_RX4
6
FDI_TXN1
FDI0_TX#[1]
PEG_RX[4]
SM_RCOMP[0] W:20mils/S:20mils/L: 500mils,
SM_RCOMP[1] W:20mils/S:20mils/L: 500mils,
SM_RCOMP[2] W:15mils/S:20mils/L: 500mils,
E19
G34
PEG_RX5
6
FDI_TXN2
FDI0_TX#[2]
PEG_RX[5]
F18
G31
PEG_RX6
6
FDI_TXN3
FDI0_TX#[3]
PEG_RX[6]
B21
F33
PEG_RX7
AP29
XDP_PRDY#
6
FDI_TXN4
FDI1_TX#[0]
PEG_RX[7]
PRDY#
TP12TP12
C20
F30
AP27
XDP_PREQ#
CPU XDP
6
FDI_TXN5
FDI1_TX#[1]
PEG_RX[8]
PREQ#
TP11TP11
D18
E35
6
FDI_TXN6
FDI1_TX#[2]
PEG_RX[9]
E17
E33
AR26
XDP_TCLK
6
FDI_TXN7
FDI1_TX#[3]
PEG_RX[10]
TCK
TP8TP8
F32
AR27
XDP_TMS
PEG_RX[11]
TMS
TP10TP10
D34
R377
R377
0_4
0_4
PM_SYNC_R
AM34
AP30
XDP_TRST#
PEG_RX[12]
6
PM_SYNC
PM_SYNC
TRST#
TP13TP13
A22
E31
6
FDI_TXP0
FDI0_TX[0]
PEG_RX[13]
G19
C33
AR28
XDP_TDI_R
6
FDI_TXP1
FDI0_TX[1]
PEG_RX[14]
TDI
TP39TP39
E20
B32
AP26
XDP_TDO
6
FDI_TXP2
FDI0_TX[2]
PEG_RX[15]
TDO
TP7TP7
C
G18
R378
R378
0_4
0_4
H_PWRGOOD_R
C
AP33
6
FDI_TXP3
FDI0_TX[3]
9
H_PWRGOOD
UNCOREPWRGOOD
B20
M29
C_PEG_TX#0
R375
R375
*1K_4
*1K_4
6
FDI_TXP4
FDI1_TX[0]
PEG_TX#[0]
+3V
C19
M32
C_PEG_TX#1
R384
R384
10K_4
10K_4
6
FDI_TXP5
FDI1_TX[1]
PEG_TX#[1]
D19
M31
C_PEG_TX#2
AL35
XDP_DBRST#
6
FDI_TXP6
FDI1_TX[2]
PEG_TX#[2]
DBR#
XDP_DBRST# 6
F17
L32
C_PEG_TX#3
9/15 SI for H/W.
PM_DRAM_PWRGD_R
V8
6
FDI_TXP7
FDI1_TX[3]
PEG_TX#[3]
SM_DRAMPWROK
L29
C_PEG_TX#4
PEG_TX#[4]
J18
K31
C_PEG_TX#5
AT28
XDP_BPM0
6
FDI_FSYNC0
FDI0_FSYNC
PEG_TX#[5]
BPM#[0]
TP40TP40
J17
K28
C_PEG_TX#6
R404
R404
*75/F_4
*75/F_4
AR29
XDP_BPM1
6
FDI_FSYNC1
FDI1_FSYNC
PEG_TX#[6]
+1.05V_VTT
BPM#[1]
TP41TP41
J30
C_PEG_TX#7
U18
U18
AR30
XDP_BPM2
CPU RESET#
PEG_TX#[7]
BPM#[2]
TP43TP43
H20
J28
3
4
CPU_PLTRST#
R400
R400
*43_4
*43_4
CPU_PLTRST#_RCPU_PLTRST#_R
AR33
AT30
XDP_BPM3
6
FDI_INT
FDI_INT
PEG_TX#[8]
GND OUT
RESET#
BPM#[3]
TP42TP42
H29
AP32
XDP_BPM4
PEG_TX#[9]
BPM#[4]
TP5TP5
+3VS5
J19
G27
2
AR31
XDP_BPM5
6
FDI_LSYNC0
FDI0_LSYNC
PEG_TX#[10]
8,14,24,27,29,30
PLTRST#
IN
C560
C560
BPM#[5]
TP45TP45
H17
E29
AT31
XDP_BPM6
6
FDI_LSYNC1
FDI1_LSYNC
PEG_TX#[11]
BPM#[6]
TP44TP44
F27
1
5
R401
R401
AR32
XDP_BPM7
PEG_TX#[12]
NC
VCC
BPM#[7]
TP46TP46
D28
PEG_TX#[13]
F26
*74LVC1G07GW
*74LVC1G07GW
750/F_4
750/F_4
PEG_TX#[14]
0.1U/10V_4
0.1U/10V_4
E25
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
PEG_TX#[15]
eDP_COMP
A18
rpga989-47989-socket
rpga989-47989-socket
eDP_COMPIO
A17
M28
C_PEG_TX0
R402
R402
1.5K/F_4
1.5K/F_4
DGG^9000005
DGG^9000005
eDP_ICOMPO
PEG_TX[0]
INT_eDP_HPD_Q
B16
M33
C_PEG_TX1
IC SOCKET RPGA 989P(P1.0,M/H3.0)
IC SOCKET RPGA 989P(P1.0,M/H3.0)
eDP_HPD
PEG_TX[1]
SM_DRAMPWROK Processor Input.
DDR3 DRAM RESET
M30
C_PEG_TX2
PEG_TX[2]
L31
C_PEG_TX3
PEG_TX[3]
+3VS5
+3VS5
C15
L28
C_PEG_TX4
eDP_AUX
PEG_TX[4]
D15
K30
C_PEG_TX5
R311
R311
1K_4
1K_4
R313
R313
*0_4
*0_4
eDP_AUX#
PEG_TX[5]
+1.5VSUS
+1.5V_CPU
K27
C_PEG_TX6
PEG_TX[6]
J29
C_PEG_TX7
PEG_TX[7]
C17
J27
R312
R312
1K_4
1K_4
3
1
CPU_DRAMRST#
eDP_TX[0]
PEG_TX[8]
12,13
DDR3_DRAMRST#
F16
H28
R49
R49
U2
U2
C27
C27
eDP_TX[1]
PEG_TX[9]
C16
G28
10K_4
10K_4
1
5
0.1U/10V_4
0.1U/10V_4
eDP_TX[2]
PEG_TX[10]
NC
VCC
G15
E28
R40
R40
CPU_DRAMRST#_R
Q24
Q24
eDP_TX[3]
PEG_TX[11]
B
PM_DRAM_PWRGD_PU
200/F_4
200/F_4
2N7002
2N7002
B
F28
PEG_TX[12]
2 IN
C18
D27
R315
R315
0_4
0_4
eDP_TX#[0]
PEG_TX[13]
8 DRAMRST_CNTRL_PCH
E16
E26
3 PM_DRAM_PWRGD_C
4
R42
R42
130/F_4
130/F_4
PM_DRAM_PWRGD_R
R314
R314
eDP_TX#[1]
PEG_TX[14]
GND OUT
D16
D25
R37
R37
C442
C442
4.99K/F_4
4.99K/F_4
eDP_TX#[2]
PEG_TX[15]
F15
R48
R48
*74LVC1G07GW
*74LVC1G07GW
0.047U/10V_4
0.047U/10V_4
eDP_TX#[3]
*0_4
*0_4
*39_4
*39_4
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
PM_DRAM_PWRGD
6
rpga989-47989-socket
rpga989-47989-socket
DGG^9000005
DGG^9000005
2
MAIN_ONG
4,38
IC SOCKET RPGA 989P(P1.0,M/H3.0)
IC SOCKET RPGA 989P(P1.0,M/H3.0)
R47
R47
0_4
0_4
PM_DRAM_PWRGD_R
+1.05V_VTT 4,6,7,8,10,29,32,33
eDP_COMP connect to PIN A18 W:4mils/S:15mils/L: 500mils.
eDP_COMP connect to PIN A17 W:12mils/S:15mils/L: 500mils.
R43
R43
Q3
Q3
+1.5V_CPU
4
*3K/F_4
*3K/F_4
*2N7002
*2N7002
+3VS5
6,7,8,9,10,22,26,31,32,38,39
+3V
6,7,8,9,10,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,38,39
FDI disable
(DIS only stuff)
PEG x16 disable (UMA only remove)
Embedded Display PLL Clock
DP & PEG Compensation
Processor pull-up (CPU)
14
PEG_TX[0
7]
14 PEG_TX#[0
7]
+1.05V_VTT
Ra
3/26 DB change
Part reference.
R67
R67
10K_4
10K_4
INT_eDP_HPD_Q
+1.05V_VTT
C_PEG_TX0
C483
C483
0.1U/10V_4
0.1U/10V_4
PEG_TX0
C_PEG_TX#0
C488
C488
0.1U/10V_4
0.1U/10V_4
PEG_TX#0
CLK_DPLL_SSCLKP
H_PROCHOT#
R145
R145
62_4
62_4
CLK_DPLL_SSCLKP
8
C_PEG_TX1
C489
C489
0.1U/10V_4
0.1U/10V_4
PEG_TX1
C_PEG_TX#1
C490
C490
0.1U/10V_4
0.1U/10V_4
PEG_TX#1
CLK_DPLL_SSCLKN
R319
R319
24.9/F_4
24.9/F_4
eDP_COMP
XDP_TDO
R155
R155
51_4
51_4
CLK_DPLL_SSCLKN
8
+1.05V_VTT
C_PEG_TX2
C492
C492
0.1U/10V_4
0.1U/10V_4
PEG_TX2
C_PEG_TX#2
C496
C496
0.1U/10V_4
0.1U/10V_4
PEG_TX#2
XDP_TMS
R159
R159
51_4
51_4
C_PEG_TX3
C498
C498
0.1U/10V_4
0.1U/10V_4
PEG_TX3
C_PEG_TX#3
C500
C500
0.1U/10V_4
0.1U/10V_4
PEG_TX#3
XDP_TDI_R
R403
R403
51_4
51_4
DEL
C_PEG_TX4
C501
C501
0.1U/10V_4
0.1U/10V_4
PEG_TX4
C_PEG_TX#4
C503
C503
0.1U/10V_4
0.1U/10V_4
PEG_TX#4
eDP_COMPIO and ICOMPO signals should be shorted
near balls and routed with typical impedance <25 mohms
XDP_PREQ#
R158
R158
*51_4
*51_4
A
C_PEG_TX5
C504
C504
0.1U/10V_4
0.1U/10V_4
PEG_TX5
C_PEG_TX#5
C507
C507
0.1U/10V_4
0.1U/10V_4
PEG_TX#5
XDP_TCLK
R156
R156
51_4
51_4
A
C_PEG_TX6
C508
C508
0.1U/10V_4
0.1U/10V_4
PEG_TX6
C_PEG_TX#6
C511
C511
0.1U/10V_4
0.1U/10V_4
PEG_TX#6
XDP_TRST#
R163
R163
51_4
51_4
C_PEG_TX7
C512
C512
0.1U/10V_4
0.1U/10V_4
PEG_TX7
C_PEG_TX#7
C517
C517
0.1U/10V_4
0.1U/10V_4
PEG_TX#7
DEL
R85
R85
24.9/F_4
24.9/F_4
PEG_COMP
+1.05V_VTT
Ra
Rb
Rc
FDI_FSYNC can gang all these 4
signals together and tie them
with only one 1K resistor to GND
(DG V0.5 Ch2.2.9).
DIS
NC
Stuff
Stuff
SG/UMA
Stuff
NC
NC
PEG_ICOMPI and RCOMPO signals
should be routed within 500 mils typical
impedance = 43 mohms PEG_ICOMPO
signals should be routed within 500 mils
typical impedance = 14.5 mohms
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
0.22uF AC coupling Caps for PCIE GEN1/2/3
0.22uF AC coupling Caps for PCIE GEN1/2/3
Custom
Custom
Custom
SNB 1/4 (PCIE&DMI&FDI)
SNB 1/4 (PCIE&DMI&FDI)
SNB 1/4 (PCIE&DMI&FDI)
3A
3A
3A
Date:
Date:
Date:
Saturday, September 18, 2010
Saturday, September 18, 2010
Saturday, September 18, 2010
Sheet
Sheet
Sheet
2
2
2
of
of
of
39
39
39
5
4
3
2
1
FDIeDP
FDIeDP
DMIIntel(R)
DMIIntel(R)
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
1
3
MISCTHERMALPWR
MISCTHERMALPWR
MANAGEMENT
MANAGEMENT
JTAG & BPM
JTAG & BPM
DDR3
DDR3
CLOCKS
CLOCKS
MISC
MISC
2

www.vinafix.vn

http://laptop-motherboard-schematic.blogspot.com/

5 4 3 2 1 Sandy Bridge Processor (DDR3) U15C U15C U15D U15D D D
5
4
3
2
1
Sandy Bridge Processor (DDR3)
U15C
U15C
U15D
U15D
D
D
AB6
AE2
SA_CLK[0]
M_A_CLKP0 12
13
M_B_DQ[63:0]
SB_CLK[0]
M_B_CLKP0 13
AA6
AD2
12
M_A_DQ[63:0]
SA_CLK#[0]
M_A_CLKN0
12
SB_CLK#[0]
M_B_CLKN0
13
M_A_DQ0
C5
V9
M_B_DQ0
C9
R9
SA_DQ[0]
SA_CKE[0]
M_A_CKE0 12
SB_DQ[0]
SB_CKE[0]
M_B_CKE0 13
M_A_DQ1
D5
M_B_DQ1
A7
SA_DQ[1]
SB_DQ[1]
M_A_DQ2
D3
M_B_DQ2
D10
SA_DQ[2]
SB_DQ[2]
M_A_DQ3
D2
M_B_DQ3
C8
SA_DQ[3]
SB_DQ[3]
M_A_DQ4
D6
AA5
M_B_DQ4
A9
AE1
SA_DQ[4]
SA_CLK[1]
M_A_CLKP1 12
SB_DQ[4]
SB_CLK[1]
M_B_CLKP1 13
M_A_DQ5
C6
AB5
M_B_DQ5
A8
AD1
SA_DQ[5]
SA_CLK#[1]
M_A_CLKN1
12
SB_DQ[5]
SB_CLK#[1]
M_B_CLKN1
13
M_A_DQ6
C2
V10
M_B_DQ6
D9
R10
SA_DQ[6]
SA_CKE[1]
M_A_CKE1 12
SB_DQ[6]
SB_CKE[1]
M_B_CKE1 13
M_A_DQ7
C3
M_B_DQ7
D8
SA_DQ[7]
SB_DQ[7]
M_A_DQ8
F10
M_B_DQ8
G4
SA_DQ[8]
SB_DQ[8]
M_A_DQ9
F8
M_B_DQ9
F4
SA_DQ[9]
SB_DQ[9]
M_A_DQ10
G10
AB4
M_B_DQ10
F1
AB2
SA_DQ[10]
SA_CLK[2]
SB_DQ[10]
SB_CLK[2]
M_A_DQ11
G9
AA4
M_B_DQ11
G1
AA2
SA_DQ[11]
SA_CLK#[2]
SB_DQ[11]
SB_CLK#[2]
M_A_DQ12
F9
W9
M_B_DQ12
G5
T9
SA_DQ[12]
SA_CKE[2]
SB_DQ[12]
SB_CKE[2]
M_A_DQ13
F7
M_B_DQ13
F5
SA_DQ[13]
SB_DQ[13]
M_A_DQ14
G8
M_B_DQ14
F2
SA_DQ[14]
SB_DQ[14]
M_A_DQ15
G7
M_B_DQ15
G2
SA_DQ[15]
SB_DQ[15]
M_A_DQ16
K4
AB3
M_B_DQ16
J7
AA1
SA_DQ[16]
SA_CLK[3]
SB_DQ[16]
SB_CLK[3]
M_A_DQ17
K5
AA3
M_B_DQ17
J8
AB1
SA_DQ[17]
SA_CLK#[3]
SB_DQ[17]
SB_CLK#[3]
M_A_DQ18
K1
W10
M_B_DQ18
K10
T10
SA_DQ[18]
SA_CKE[3]
SB_DQ[18]
SB_CKE[3]
M_A_DQ19
J1
M_B_DQ19
K9
SA_DQ[19]
SB_DQ[19]
M_A_DQ20
J5
M_B_DQ20
J9
SA_DQ[20]
SB_DQ[20]
M_A_DQ21
J4
M_B_DQ21
J10
SA_DQ[21]
SB_DQ[21]
M_A_DQ22
J2
AK3
M_B_DQ22
K8
AD3
SA_DQ[22]
SA_CS#[0]
M_A_CS#0 12
SB_DQ[22]
SB_CS#[0]
M_B_CS#0 13
M_A_DQ23
K2
AL3
M_B_DQ23
K7
AE3
SA_DQ[23]
SA_CS#[1]
M_A_CS#1 12
SB_DQ[23]
SB_CS#[1]
M_B_CS#1 13
M_A_DQ24
M8
AG1
M_B_DQ24
M5
AD6
SA_DQ[24]
SA_CS#[2]
SB_DQ[24]
SB_CS#[2]
M_A_DQ25
N10
AH1
M_B_DQ25
N4
AE6
SA_DQ[25]
SA_CS#[3]
SB_DQ[25]
SB_CS#[3]
M_A_DQ26
N8
M_B_DQ26
N2
SA_DQ[26]
SB_DQ[26]
C
M_A_DQ27
C
N7
M_B_DQ27
N1
SA_DQ[27]
SB_DQ[27]
M_A_DQ28
M10
M_B_DQ28
M4
SA_DQ[28]
SB_DQ[28]
M_A_DQ29
M9
AH3
M_B_DQ29
N5
AE4
SA_DQ[29]
SA_ODT[0]
M_A_ODT0 12
SB_DQ[29]
SB_ODT[0]
M_B_ODT0 13
M_A_DQ30
N9
AG3
M_B_DQ30
M2
AD4
SA_DQ[30]
SA_ODT[1]
M_A_ODT1 12
SB_DQ[30]
SB_ODT[1]
M_B_ODT1 13
M_A_DQ31
M7
AG2
M_B_DQ31
M1
AD5
SA_DQ[31]
SA_ODT[2]
SB_DQ[31]
SB_ODT[2]
M_A_DQ32
AG6
AH2
M_B_DQ32
AM5
AE5
SA_DQ[32]
SA_ODT[3]
SB_DQ[32]
SB_ODT[3]
M_A_DQ33
AG5
M_B_DQ33
AM6
SA_DQ[33]
SB_DQ[33]
M_A_DQ34
AK6
M_B_DQ34
AR3
SA_DQ[34]
SB_DQ[34]
M_A_DQ35
AK5
M_B_DQ35
AP3
SA_DQ[35]
SB_DQ[35]
M_A_DQ36
AH5
M_B_DQ36
AN3
SA_DQ[36]
12
SB_DQ[36]
13
M_A_DQ37
AH6
C4
M_A_DQSN0
M_B_DQ37
AN2
D7
M_B_DQSN0
SA_DQ[37]
SA_DQS#[0]
SB_DQ[37]
SB_DQS#[0]
M_A_DQ38
AJ5
G6
M_A_DQSN1
M_B_DQ38
AN1
F3
M_B_DQSN1
SA_DQ[38]
SA_DQS#[1]
SB_DQ[38]
SB_DQS#[1]
M_A_DQ39
AJ6
J3
M_A_DQSN2
M_B_DQ39
AP2
K6
M_B_DQSN2
SA_DQ[39]
SA_DQS#[2]
SB_DQ[39]
SB_DQS#[2]
M_A_DQ40
AJ8
M6
M_A_DQSN3
M_A_DQSN[7:0]
M_B_DQ40
AP5
N3
M_B_DQSN3
SA_DQ[40]
SA_DQS#[3]
SB_DQ[40]
SB_DQS#[3]
M_A_DQ41
AK8
AL6
M_A_DQSN4
M_B_DQ41
AN9
AN5
M_B_DQSN4
SA_DQ[41]
SA_DQS#[4]
SB_DQ[41]
SB_DQS#[4]
M_A_DQ42
AJ9
AM8
M_A_DQSN5
M_B_DQ42
AT5
AP9
M_B_DQSN5
SA_DQ[42]
SA_DQS#[5]
SB_DQ[42]
SB_DQS#[5]
M_A_DQ43
AK9
AR12
M_A_DQSN6
M_B_DQ43
AT6
AK12
M_B_DQSN6
SA_DQ[43]
SA_DQS#[6]
SB_DQ[43]
SB_DQS#[6]
M_A_DQ44
AH8
AM15
M_A_DQSN7
M_B_DQ44
AP6
AP15
M_B_DQSN7
M_B_DQSN[7:0]
SA_DQ[44]
SA_DQS#[7]
SB_DQ[44]
SB_DQS#[7]
M_A_DQ45
AH9
M_B_DQ45
AN8
SA_DQ[45]
SB_DQ[45]
M_A_DQ46
AL9
M_B_DQ46
AR6
SA_DQ[46]
SB_DQ[46]
M_A_DQ47
AL8
M_B_DQ47
AR5
SA_DQ[47]
SB_DQ[47]
M_A_DQ48
AP11
M_B_DQ48
AR9
SA_DQ[48]
M_A_DQSP[7:0]
12
SB_DQ[48]
13
M_A_DQ49
AN11
D4
M_A_DQSP0
M_B_DQ49
AJ11
C7
M_B_DQSP0
SA_DQ[49]
SA_DQS[0]
SB_DQ[49]
SB_DQS[0]
M_A_DQ50
AL12
F6
M_A_DQSP1
M_B_DQ50
AT8
G3
M_B_DQSP1
SA_DQ[50]
SA_DQS[1]
SB_DQ[50]
SB_DQS[1]
M_A_DQ51
AM12
K3
M_A_DQSP2
M_B_DQ51
AT9
J6
M_B_DQSP2
SA_DQ[51]
SA_DQS[2]
SB_DQ[51]
SB_DQS[2]
M_A_DQ52
AM11
N6
M_A_DQSP3
M_B_DQ52
AH11
M3
M_B_DQSP3
SA_DQ[52]
SA_DQS[3]
SB_DQ[52]
SB_DQS[3]
M_A_DQ53
AL11
AL5
M_A_DQSP4
M_B_DQ53
AR8
AN6
M_B_DQSP4
SA_DQ[53]
SA_DQS[4]
SB_DQ[53]
SB_DQS[4]
M_A_DQ54
AP12
AM9
M_A_DQSP5
M_B_DQ54
AJ12
AP8
M_B_DQSP5
SA_DQ[54]
SA_DQS[5]
SB_DQ[54]
SB_DQS[5]
M_A_DQ55
AN12
AR11
M_A_DQSP6
M_B_DQ55
AH12
AK11
M_B_DQSP6
SA_DQ[55]
SA_DQS[6]
SB_DQ[55]
SB_DQS[6]
M_A_DQ56
AJ14
AM14
M_A_DQSP7
M_B_DQ56
AT11
AP14
M_B_DQSP7
M_B_DQSP[7:0]
SA_DQ[56]
SA_DQS[7]
SB_DQ[56]
SB_DQS[7]
B
M_A_DQ57
M_B_DQ57
B
AH14
AN14
SA_DQ[57]
SB_DQ[57]
M_A_DQ58
AL15
M_B_DQ58
AR14
SA_DQ[58]
SB_DQ[58]
M_A_DQ59
AK15
M_B_DQ59
AT14
SA_DQ[59]
SB_DQ[59]
M_A_DQ60
AL14
M_B_DQ60
AT12
SA_DQ[60]
M_A_A[15:0]
12
SB_DQ[60]
M_B_A[15:0]
13
M_A_DQ61
AK14
AD10
M_A_A0
M_B_DQ61
AN15
AA8
M_B_A0
SA_DQ[61]
SA_MA[0]
SB_DQ[61]
SB_MA[0]
M_A_DQ62
AJ15
W1
M_A_A1
M_B_DQ62
AR15
T7
M_B_A1
SA_DQ[62]
SA_MA[1]
SB_DQ[62]
SB_MA[1]
M_A_DQ63
AH15
W2
M_A_A2
M_B_DQ63
AT15
R7
M_B_A2
SA_DQ[63]
SA_MA[2]
SB_DQ[63]
SB_MA[2]
W7
M_A_A3
T6
M_B_A3
SA_MA[3]
SB_MA[3]
V3
M_A_A4
T2
M_B_A4
SA_MA[4]
SB_MA[4]
V2
M_A_A5
T4
M_B_A5
SA_MA[5]
SB_MA[5]
W3
M_A_A6
T3
M_B_A6
SA_MA[6]
SB_MA[6]
AE10
W6
M_A_A7
AA9
R2
M_B_A7
12
M_A_BS#0
SA_BS[0]
SA_MA[7]
13
M_B_BS#0
SB_BS[0]
SB_MA[7]
AF10
V1
M_A_A8
AA7
T5
M_B_A8
12
M_A_BS#1
SA_BS[1]
SA_MA[8]
13
M_B_BS#1
SB_BS[1]
SB_MA[8]
V6
W5
M_A_A9
R6
R3
M_B_A9
12
M_A_BS#2
SA_BS[2]
SA_MA[9]
13
M_B_BS#2
SB_BS[2]
SB_MA[9]
AD8
M_A_A10
AB7
M_B_A10
SA_MA[10]
SB_MA[10]
V4
M_A_A11
R1
M_B_A11
SA_MA[11]
SB_MA[11]
W4
M_A_A12
T1
M_B_A12
SA_MA[12]
SB_MA[12]
AE8
AF8
M_A_A13
AA10
AB10
M_B_A13
12
M_A_CAS#
SA_CAS#
SA_MA[13]
13
M_B_CAS#
SB_CAS#
SB_MA[13]
AD9
V5
M_A_A14
AB8
R5
M_B_A14
12
M_A_RAS#
SA_RAS#
SA_MA[14]
13
M_B_RAS#
SB_RAS#
SB_MA[14]
AF9
V7
M_A_A15
AB9
R4
M_B_A15
12
M_A_WE#
SA_WE#
SA_MA[15]
13
M_B_WE#
SB_WE#
SB_MA[15]
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
rpga989-47989-socket
rpga989-47989-socket
rpga989-47989-socket
rpga989-47989-socket
DGG^9000005
DGG^9000005
DGG^9000005
DGG^9000005
IC SOCKET RPGA 989P(P1.0,M/H3.0)
IC SOCKET RPGA 989P(P1.0,M/H3.0)
IC SOCKET RPGA 989P(P1.0,M/H3.0)
IC SOCKET RPGA 989P(P1.0,M/H3.0)
A
A
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
SNB 2/4 (DDR3 I/F)
SNB 2/4 (DDR3 I/F)
SNB 2/4 (DDR3 I/F)
3A
3A
3A
1A
1A
1A
Date:
Date:
Date:
Saturday, September 18, 2010
Saturday, September 18, 2010
Saturday, September 18, 2010
Sheet
Sheet
Sheet
3
3
3
of
of
of
39
39
39
5
4
3
2
1
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B

www.vinafix.vn

http://laptop-motherboard-schematic.blogspot.com/

5 4 3 2 1 Sandy Bridge Processor (POWER) Sandy Bridge Processor (GRAPHIC POWER) U15F
5
4
3
2
1
Sandy Bridge Processor (POWER)
Sandy Bridge Processor (GRAPHIC POWER)
U15F
U15F
U15G
+VCC_CORE
SNB: 55A
22uF_8 x2 Socket TOP cavity
22uF_8 x2 Socket BOT cavity
U15G
R140
R140
100_4
100_4
+VCC_GFX
+1.05V_VTT
SNB: 8.5A
22uF_8 x4 Socket TOP edge
AG35
AT24
AK35
VCC1
VAXG1
VAXG_SENSE
VCC_AXG_SENSE
33
AG34
AH13
22uF_8 x4 Socket BOT edge
AT23
AK34
VCC2
VCCIO1
VAXG2
VSSAXG_SENSE
VSS_AXG_SENSE 33
AG33
AH10
470uF_7343 x2
AT21
VCC3
VCCIO2
VAXG3
AG32
AG10
AT20
R142
R142
100_4
100_4
VCC4
VCCIO3
VAXG4
C493
C493
C521
C521
C516
C516
AG31
AC10
C145
C145
C147
C147
C482
C482
AT18
VCC5
VCCIO4
VAXG5
D
22U/6.3VS_8
22U/6.3VS_8
10U/6.3VS_6
10U/6.3VS_6
22U/6.3VS_8
22U/6.3VS_8
D
AG30
Y10
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
AT17
VCC6
VCCIO5
VAXG6
+VCC_GFX
AG29
U10
SNB: 21.5A
AR24
VCC7
VCCIO6
VAXG7
AG28
P10
AR23
VCC8
VCCIO7
VAXG8
AG27
L10
AR21
VCC9
VCCIO8
VAXG9
AG26
J14
AR20
VCC10
VCCIO9
VAXG10
+VDDR_REF_CPU
AF35
J13
AR18
VCC11
VCCIO10
VAXG11
CAD Note: +VDDR_REF_CPU should
have 10 mil trace width
AF34
J12
C260
C260
C180
C180
C166
C166
C529
C529
C264
C264
AR17
VCC12
VCCIO11
VAXG12
C42
C42
C36
C36
C174
C174
AF33
J11
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
AP24
AL1
R28
R28
*0_8
*0_8
VCC13
VCCIO12
VAXG13
SM_VREF
DDR_VTTREF
12,13,35
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
AF32
H14
AP23
VCC14
VCCIO13
VAXG14
AF31
H12
AP21
VCC15
VCCIO14
VAXG15
AF30
H11
AP20
1
3
VCC16
VCCIO15
VAXG16
AF29
G14
AP18
VCC17
VCCIO16
VAXG17
AF28
G13
AP17
R31
R31
Q2
Q2
VCC18
VCCIO17
VAXG18
AF27
G12
C146
C146
C215
C215
C526
C526
C285
C285
C299
C299
AN24
100K_4
100K_4
2N7002
2N7002
VCC19
VCCIO18
VAXG19
AF26
F14
*22U/6.3VS_8
*22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
AN23
VCC20
VCCIO19
VAXG20
C509
C509
C172
C172
C263
C263
AD35
F13
AN21
MAIND
VCC21
VCCIO20
VAXG21
MAIND
38
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
AD34
F12
AN20
VCC22
VCCIO21
VAXG22
AD33
F11
AN18
VCC23
VCCIO22
VAXG23
AD32
E14
AN17
VCC24
VCCIO23
VAXG24
AD31
E12
AM24
AF7
VCC25
VCCIO24
VAXG25
VDDQ1
+1.5V_CPU
AD30
C532
C532
C200
C200
C61
C61
C284
C284
C530
C530
AM23
AF4
SNB: 5A
VCC26
VAXG26
VDDQ2
AD29
E11
*22U/6.3VS_8
*22U/6.3VS_8
*22U/6.3VS_8
*22U/6.3VS_8
*22U/6.3VS_8
*22U/6.3VS_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
AM21
AF1
VCC27
VCCIO25
VAXG27
VDDQ3
AD28
D14
AM20
AC7
VCC28
VCCIO26
VAXG28
VDDQ4
C300
C300
C39
C39
C502
C502
AD27
D13
AM18
AC4
VCC29
VCCIO27
VAXG29
VDDQ5
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
AD26
D12
AM17
AC1
VCC30
VCCIO28
VAXG30
VDDQ6
AC35
D11
AL24
Y7
C297
C297
C214
C214
C289
C289
C268
C268
VCC31
VCCIO29
VAXG31
VDDQ7
AC34
C14
5/14 modify
AL23
Y4
10U/6.3V_6
10U/6.3V_6
10U/6.3V_8
10U/6.3V_8
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
VCC32
VCCIO30
VAXG32
VDDQ8
AC33
C13
C491
C491
C66
C66
C282
C282
C301
C301
C238
C238
AL21
Y1
VCC33
VCCIO31
VAXG33
VDDQ9
AC32
C12
22U/6.3VS_8
22U/6.3VS_8
*22U/6.3VS_8
*22U/6.3VS_8
*22U/6.3VS_8
*22U/6.3VS_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
AL20
U7
4/27: layout modify
VCC34
VCCIO32
VAXG34
VDDQ10
AC31
C11
AL18
U4
VCC35
VCCIO33
VAXG35
VDDQ11
C
C527
C527
C
AC30
B14
AL17
U1
9/10 SI for H/W.
VCC36
VCCIO34
VAXG36
VDDQ12
C177
C177
*10U/6.3V_6S
*10U/6.3V_6S
C33
C33
AC29
B12
AK24
P7
VCC37
VCCIO35
VAXG37
VDDQ13
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
+ +
AC28
A14
AK23
P4
VCC38
VCCIO36
VAXG38
VDDQ14
AC27
A13
AK21
P1
C190
C190
C305
C305
C576
C576
VCC39
VCCIO37
VAXG39
VDDQ15
AC26
A12
C167
C167
C506
C506
C236
C236
C528
C528
C239
C239
AK20
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
*330U_2.5V_5.0x5.9_ESR10m
*330U_2.5V_5.0x5.9_ESR10m
VCC40
VCCIO38
VAXG40
AA35
A11
*22U/6.3VS_8
*22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
*22U/6.3VS_8
*22U/6.3VS_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
AK18
VCC41
VCCIO39
VAXG41
AA34
AK17
VCC42
VAXG42
AA33
J23
AJ24
330uF x1, 10uF_8 x6 Socket BOT edge.
VCC43
VCCIO40
VAXG43
AA32
AJ23
VCC44
VAXG44
C151
C151
C286
C286
C283
C283
AA31
AJ21
VCC45
VAXG45
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
AA30
AJ20
VCC46
VAXG46
AA29
C513
C513
C499
C499
C158
C158
C265
C265
C531
C531
AJ18
VCC47
VAXG47
AA28
*22U/6.3VS_8
*22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
AJ17
VCC48
VAXG48
+VCCSA
AA27
AH24
SNB: 6A
VCC49
VAXG49
AA26
AH23
VCC50
VAXG50
Y35
AH21
M27
VCC51
VAXG51
VCCSA1
Y34
AH20
M26
VCC52
VAXG52
VCCSA2
C237
C237
C242
C242
C163
C163
Y33
AH18
L26
VCC53
22uF_8 x7 Socket TOP cavity
22uF_8 x5 Socket BOT cavity
22uF_8 x2 Socket TOP cavity (no stuff)
22uF_8 x5 Socket BOT cavity (no stuff)
330uF_7343 x2
VAXG53
VCCSA3
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
Y32
DEL
AH17
J26
C485
C485
C448
C448
C484
C484
C445
C445
VCC54
VAXG54
VCCSA4
Y31
J25
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
*10U/6.3V_8
*10U/6.3V_8
VCC55
VCCSA5
Y30
J24
VCC56
VCCSA6
Y29
DIS
SG/UMA
H26
VCC57
VCCSA7
Y28
H25
VCC58
VCCSA8
Y27
Ra
Stuff
NC
VCC59
330uF x1, 10uF_8 x1 Socket BOT edge,
10uF_8 x2 Socket BOT cavity.
Y26
VCC60
+1.05V_VTT
C535
C535
C220
C220
C447
C447
V35
VCC61
+1.8V
*22U/6.3VS_8
*22U/6.3VS_8
*22U/6.3VS_8
*22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
V34
SNB: 1.5A
VCC62
V33
+1.05V_VTT_40
R86
R86
*0_4/S
*0_4/S
VCC63
V32
B6
H23
VCCUSA_SENSE_R
R82
R82
0_4
0_4
VCC64
VCCPLL1
VCCSA_SENSE
VCCUSA_SENSE
36
V31
A6
VCC65
VCCPLL2
B
B
V30
A2
VCC66
VCCPLL3
V29
AJ29
H_CPU_SVIDALRT#
C449
C449
C441
C441
C443
C443
+ C440
+
C440
R77
R77
10K_4
10K_4
VCC67
VIDALERT#
V28
AJ30
H_CPU_SVIDCLK
10U/6.3V_8
10U/6.3V_8
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
330U/2V_7343
330U/2V_7343
C22
H_FC_C22
VCC68
VIDSCLK
FC_C22
C173
C173
C515
C515
C270
C270
V27
AJ28
H_CPU_SVIDDAT
C24
VCC69
VIDSOUT
VCCSA_VID1
VCCSA_SEL
36
22U/6.3VS_8
22U/6.3VS_8
10U/6.3VS_6
10U/6.3VS_6
22U/6.3VS_8
22U/6.3VS_8
V26
VCC70
U35
R81
R81
10K_4
10K_4
VCC71
U34
VCC72
330uF x1, 10uF_8 x1, 1uF_4 x2
Socket BOT edge.
U33
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
VCC73
U32
rpga989-47989-socket
rpga989-47989-socket
5/11: Add for intel CRB
VCC74
U31
DGG^9000005
DGG^9000005
R310
R310
*0_8/S
*0_8/S
VCC75
+1.5V_CPU
+1.5V
C542
C542
U30
IC SOCKET RPGA 989P(P1.0,M/H3.0)
IC SOCKET RPGA 989P(P1.0,M/H3.0)
VCC76
C450
C450
C451
C451
*10U/6.3V_6S
*10U/6.3V_6S
U29
40mile routing
VCC77
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
U28
VCC78
U27
VCC79
U26
VCC80
+1.5VSUS
+1.5V_CPU
+1.5VSUS
R35
VCC81
Place PU resistor
close to VR
SVID CLK
R34
VCC82
22uF_8 x8 Socket TOP cavity
22uF_8 x10 Socket BOT cavity
22uF_8 x8 Socket TOP edge
470uF_7343 x4
R33
Layout note: need routing
together and ALERT need
between CLK and DATA.
R309
R309
*54.9/F_4
*54.9/F_4
C455
0.1U/10V_4
0.1U/10V_4
VCC83
+1.05V_VTT
C455
R32
R136
R136
100_4
100_4
VCC84
+VCC_CORE
Q36
Q36
R31
C452
C452
0.1U/10V_4
0.1U/10V_4
VCC85
R30
AJ35
H_CPU_SVIDCLK
AON7410
AON7410
VCC86
VCC_SENSE
VCC_SENSE
33
VR_SVID_CLK
33
R29
AJ34
1
R185
R185
C554
0.1U/10V_4
0.1U/10V_4
VCC87
VSS_SENSE
VSS_SENSE
33
C554
R28
5
2
220_8
220_8
VCC88
3/26 DB change 10U FP to 0805.
R27
R139
R139
100_4
100_4
3
C558
C558
0.1U/10V_4
0.1U/10V_4
VCC89
+1.05V_VTT
+1.05V_VTT
R26
SVID DATA
VCC90
P35
VCC91
P34
3/26 DB add for Intel.
Placement close to CPU.
VCC92
P33
MAIND
VCC93
VCCP_SENSE
32
P32
B10
2
VCC94
VCCIO_SENSE
MAIN_ONG
2,38
P31
A10
VSSP_SENSE
R137
R137
R308
R308
VCC95
VSSIO_SENSE
VSSP_SENSE
32
Place PU resistor
close to CPU
Place PU resistor
close to VR
A
130/F_4
130/F_4
*130/F_4
*130/F_4
C438
C438
Q16
Q16
A
P30
VCC96
P29
*470P/50V_4
*470P/50V_4
2N7002
2N7002
VCC97
P28
Trace Route to Power IC area.
H_CPU_SVIDDAT
VCC98
VR_SVID_DATA
33
CPU VDDQ
P27
VCC99
P26
+VCC_CORE
22,34
VCC100
+VCC_GFX
34
Place PU resistor close to CPU
SVID ALERT
+VCCSA
36
+1.05V_VTT 2,6,7,8,10,29,32,33
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
R26
R26
75/F_4
75/F_4
+1.5V_CPU
2
+1.05V_VTT
rpga989-47989-socket
rpga989-47989-socket
+1.5V_CPU
2
DGG^9000005
DGG^9000005
+1.5VSUS
2,10,12,13,22,35,39
IC SOCKET RPGA 989P(P1.0,M/H3.0)
IC SOCKET RPGA 989P(P1.0,M/H3.0)
H_CPU_SVIDALRT#
R25
R25
43_4
43_4
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
VR_SVID_ALERT#
33
Custom
Custom
Custom
SNB 3/4 (POWER)
SNB 3/4 (POWER)
SNB 3/4 (POWER)
3A
3A
3A
1A
1A
1A
Date:
Date:
Date:
Saturday, September 18, 2010
Saturday, September 18, 2010
Saturday, September 18, 2010
Sheet
Sheet
Sheet
4
4
4
of
of
of
39
39
39
5
4
3
2
1
CORE SUPPLY
CORE SUPPLY
SENSE LINES
SENSE LINES
SVID
SVID
PEG AND DDR
PEG AND DDR
1.8V RAIL
1.8V RAIL
GRAPHICS
GRAPHICS
SENSE
SENSE
VREFMISC
VREFMISC
SA RAIL
SA RAIL
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
LINES
LINES
4
2
1
3
12

www.vinafix.vn

http://laptop-motherboard-schematic.blogspot.com/

5 4 3 2 1 Sandy Bridge Processor (GND) Sandy Bridge Processor (RESERVED, CFG) U15H
5
4
3
2
1
Sandy Bridge Processor (GND)
Sandy Bridge Processor (RESERVED, CFG)
U15H
U15H
U15I
U15I
U15E
U15E
AT35
AJ22
VSS1
VSS81
AT32
AJ19
For CPU debug.
L7
VSS2
VSS82
RSVD28
AT29
AJ16
T35
F22
AG7
VSS3
VSS83
VSS161
VSS234
RSVD29
AT27
AJ13
T34
F19
CFG0
AK28
AE7
VSS4
VSS84
VSS162
VSS235
TP6TP6
CFG[0]
RSVD30
AT25
AJ10
T33
E30
AK29
AK2
VSS5
VSS85
VSS163
VSS236
TP3TP3
CFG[1]
RSVD31
AT22
AJ7
T32
E27
CFG2
AL26
W8
VSS6
VSS86
VSS164
VSS237
CFG[2]
RSVD32
AT19
AJ4
T31
E24
AL27
VSS7
VSS87
VSS165
VSS238
TP9TP9
CFG[3]
D
D
AT16
AJ3
T30
E21
CFG4
AK26
VSS8
VSS88
VSS166
VSS239
CFG[4]
AT13
AJ2
T29
E18
CFG5
AL29
AT26
VSS9
VSS89
VSS167
VSS240
CFG[5]
RSVD33
AT10
AJ1
T28
E15
CFG6
AL30
AM33
VSS10
VSS90
VSS168
VSS241
CFG[6]
RSVD34
AT7
AH35
T27
E13
CFG7CFG7
AM31
AJ27
VSS11
VSS91
VSS169
VSS242
CFG[7]
RSVD35
AT4
AH34
T26
E10
AM32
VSS12
VSS92
VSS170
VSS243
CFG[8]
AT3
AH32
P9
E9
AM30
VSS13
VSS93
VSS171
VSS244
CFG[9]
AR25
AH30
P8
E8
AM28
VSS14
VSS94
VSS172
VSS245
CFG[10]
AR22
AH29
P6
E7
AM26
VSS15
VSS95
VSS173
VSS246
CFG[11]
AR19
AH28
P5
E6
AN28
VSS16
VSS96
VSS174
VSS247
CFG[12]
AR16
AH26
P3
E5
AN31
T8
VSS17
VSS97
VSS175
VSS248
CFG[13]
RSVD37
AR13
AH25
P2
E4
AN26
J16
VSS18
VSS98
VSS176
VSS249
CFG[14]
RSVD38
AR10
AH22
N35
E3
AM27
H16
VSS19
VSS99
VSS177
VSS250
CFG[15]
RSVD39
AR7
AH19
N34
E2
AK31
G16
VSS20
VSS100
VSS178
VSS251
TP1TP1
CFG[16]
RSVD40
AR4
AH16
N33
E1
AN29
VSS21
VSS101
VSS179
VSS252
CFG[17]
AR2
AH7
N32
D35
VSS22
VSS102
VSS180
VSS253
AP34
AH4
N31
D32
VSS23
VSS103
VSS181
VSS254
AP31
AG9
N30
D29
VSS24
VSS104
VSS182
VSS255
AP28
AG8
N29
D26
AR35
VSS25
VSS105
VSS183
VSS256
RSVD41
AP25
AG4
N28
D20
AJ31
AT34
VSS26
VSS106
VSS184
VSS257
RSVD1
RSVD42
AP22
AF6
N27
D17
AH31
AT33
VSS27
VSS107
VSS185
VSS258
RSVD2
RSVD43
AP19
AF5
N26
C34
AJ33
AP35
VSS28
VSS108
VSS186
VSS259
RSVD3
RSVD44
AP16
AF3
M34
C31
AH33
AR34
VSS29
VSS109
VSS187
VSS260
RSVD4
RSVD45
AP13
AF2
L33
C28
VSS30
VSS110
VSS188
VSS261
AP10
AE35
L30
C27
VSS31
VSS111
VSS189
VSS262
AP7
AE34
L27
C25
AJ26
VSS32
VSS112
VSS190
VSS263
RSVD5
AP4
AE33
L9
C23
VSS33
VSS113
VSS191
VSS264
AP1
AE32
L8
C10
VSS34
VSS114
VSS192
VSS265
AN30
AE31
L6
C1
B34
VSS35
VSS115
VSS193
VSS266
RSVD46
AN27
AE30
L5
B22
B4
A33
VSS36
VSS116
VSS194
VSS267
12 SMDDR_VREF_DQ0_M3
RSVD47
AN25
AE29
L4
B19
D1
A34
VSS37
VSS
VSS
VSS117
VSS195
VSS
VSS
VSS268
13 SMDDR_VREF_DQ1_M3
RSVD6
RSVD7
RSVD48
C
C
AN22
AE28
L3
B17
B35
VSS38
VSS118
VSS196
VSS269
RSVD49
AN19
AE27
L2
B15
C35
VSS39
VSS119
VSS197
VSS270
RSVD50
AN16
AE26
L1
B13
VSS40
VSS120
VSS198
VSS271
AN13
AE9
K35
B11
R321
R321
R317
R317
F25
VSS41
VSS121
VSS199
VSS272
RSVD8
AN10
AD7
K32
B9
*1K_4
*1K_4
*1K_4
*1K_4
F24
VSS42
VSS122
VSS200
VSS273
RSVD9
AN7
AC9
K29
B8
F23
VSS43
VSS123
VSS201
VSS274
RSVD10
AN4
AC8
K26
B7
D24
AJ32
VSS44
VSS124
VSS202
VSS275
RSVD11
RSVD51
AM29
AC6
J34
B5
G25
AK32
VSS45
VSS125
VSS203
VSS276
RSVD12
RSVD52
AM25
AC5
J31
B3
G24
VSS46
VSS126
VSS204
VSS277
RSVD13
AM22
AC3
H33
B2
E23
VSS47
VSS127
VSS205
VSS278
RSVD14
AM19
AC2
H30
A35
D23
VSS48
VSS128
VSS206
VSS279
RSVD15
AM16
AB35
H27
A32
C30
AH27
VSS49
VSS129
VSS207
VSS280
RSVD16
RSVD53
AM13
AB34
H24
A29
A31
VSS50
VSS130
VSS208
VSS281
RSVD17
AM10
AB33
H21
A26
B30
VSS51
VSS131
VSS209
VSS282
RSVD18
AM7
AB32
H18
A23
B29
VSS52
VSS132
VSS210
VSS283
RSVD19
AM4
AB31
H15
A20
D30
AN35
VSS53
VSS133
VSS211
VSS284
RSVD20
RSVD54
TP38TP38
AM3
AB30
H13
A3
B31
AM35
VSS54
VSS134
VSS212
VSS285
RSVD21
RSVD55
TP37TP37
AM2
AB29
H10
A30
VSS55
VSS135
VSS213
RSVD22
AM1
AB28
H9
C29
#27636 SNB EDS0.7v1 no function.
VSS56
VSS136
VSS214
RSVD23
AL34
AB27
H8
VSS57
VSS137
VSS215
AL31
AB26
H7
VSS58
VSS138
VSS216
AL28
Y9
H6
J20
VSS59
VSS139
VSS217
RSVD24
AL25
Y8
H5
B18
AT2
VSS60
VSS140
VSS218
RSVD25
RSVD56
AL22
Y6
H4
R320
R320
0_4
0_4
A19
AT1
VSS61
VSS141
VSS219
32
H_VTTVID1
RSVD26
RSVD57
AL19
Y5
H3
AR1
VSS62
VSS142
VSS220
RSVD58
AL16
Y3
H2
VSS63
VSS143
VSS221
AL13
Y2
H1
J15
For rPGA socket, RSVD59 pin should be left NC.
VSS64
VSS144
VSS222
RSVD27
AL10
W35
G35
VSS65
VSS145
VSS223
AL7
W34
G32
VSS66
VSS146
VSS224
AL4
W33
G29
B1
VSS67
VSS147
VSS225
KEY
B
B
AL2
W32
G26
VSS68
VSS148
VSS226
AK33
W31
G23
VSS69
VSS149
VSS227
AK30
W30
G20
VSS70
VSS150
VSS228
AK27
W29
G17
VSS71
VSS151
VSS229
AK25
W28
G11
VSS72
VSS152
VSS230
AK22
W27
F34
VSS73
VSS153
VSS231
AK19
W26
F31
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
VSS74
VSS154
VSS232
AK16
U9
F29
rpga989-47989-socket
rpga989-47989-socket
VSS75
VSS155
VSS233
AK13
U8
DGG^9000005
DGG^9000005
VSS76
VSS156
AK10
U6
IC SOCKET RPGA 989P(P1.0,M/H3.0)
IC SOCKET RPGA 989P(P1.0,M/H3.0)
VSS77
VSS157
AK7
U5
VSS78
VSS158
AK4
U3
VSS79
VSS159
AJ25
U2
VSS80
VSS160
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
rpga989-47989-socket
rpga989-47989-socket
rpga989-47989-socket
rpga989-47989-socket
DGG^9000005
DGG^9000005
DGG^9000005
DGG^9000005
IC SOCKET RPGA 989P(P1.0,M/H3.0)
IC SOCKET RPGA 989P(P1.0,M/H3.0)
IC SOCKET RPGA 989P(P1.0,M/H3.0)
IC SOCKET RPGA 989P(P1.0,M/H3.0)
CFG[6:5] (PCIE Port Bifurcation Straps)
Processor Strapping
The CFG signals have a default value of '1' if not terminated on the board.
1
0
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG2
A
A
Normal Operation
Lane Reversed
(PEG Static Lane Reversal)
CFG2
R153
R153
*1K_4
*1K_4
CFG4
CFG4
R154
R154
*1K_4
*1K_4
Disable; No physical DP attached to eDP
Enable; An ext DP device is connected to eDP
(DP Presence Strap)
CFG7
R149
R149
*1K_4
*1K_4
CFG7
PEG train immediately following
xxRESETB de assertion
PEG wait for BIOS training
CFG5
R152
R152
1K_4
1K_4
(PEG Defer Training)
CFG6
R147
R147
1K_4
1K_4
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
SNB 4/4 (GND)
SNB 4/4 (GND)
SNB 4/4 (GND)
3A
3A
3A
1A
1A
1A
Date:
Date:
Date:
Saturday, September 18, 2010
Saturday, September 18, 2010
Saturday, September 18, 2010
Sheet
Sheet
Sheet
5
5
5
of
of
of
39
39
39
5
4
3
2
1
RESERVED
RESERVED

www.vinafix.vn

http://laptop-motherboard-schematic.blogspot.com/

INT. HDMI 5 4 3 2 1 Cougar Point (DMI,FDI,PM) Cougar Point (LVDS,DDI) U24C U24C
INT. HDMI
5
4
3
2
1
Cougar Point (DMI,FDI,PM)
Cougar Point (LVDS,DDI)
U24C
U24C
U24D
U24D
J47
AP43
20
LVDS_BLON
L_BKLTEN
SDVO_TVCLKINN
BC24
BJ14
M45
AP45
2
DMI_RXN0
DMI0RXN
FDI_RXN0
FDI_TXN0
2
20
DISP_ON
L_VDD_EN
SDVO_TVCLKINP
BE20
AY14
2
DMI_RXN1
DMI1RXN
FDI_RXN1
FDI_TXN1
2
BG18
BE14
P45
AM42
2
DMI_RXN2
DMI2RXN
FDI_RXN2
FDI_TXN2
2
20
DPST_PWM
L_BKLTCTL
SDVO_STALLN
BG20
BH13
AM40
2
DMI_RXN3
DMI3RXN
FDI_RXN3
FDI_TXN3
2
SDVO_STALLP
BC12
T40
FDI_RXN4
FDI_TXN4
2
20
EDIDCLK
L_DDC_CLK
BE24
BJ12
K47
AP39
2
DMI_RXP0
DMI0RXP
FDI_RXN5
FDI_TXN5
2
20
EDIDDATA
L_DDC_DATA
SDVO_INTN
BC20
BG10
AP40
2
DMI_RXP1
DMI1RXP
FDI_RXN6
FDI_TXN6
2
SDVO_INTP
D
R276
R276
2.2K_4
2.2K_4
L_CTRL_CLK
D
BJ18
BG9
T45
2
DMI_RXP2
DMI2RXP
FDI_RXN7
FDI_TXN7
2
L_CTRL_CLK
BJ20
R275
R275
2.2K_4
2.2K_4
L_CTRL_DATA
P39
2
DMI_RXP3
DMI3RXP
+3V
L_CTRL_DATA
BG14
FDI_RXP0
FDI_TXP0 2
AW24
BB14
R273
R273
2.37K/F_4
2.37K/F_4
LVDS_IBG
AF37
P38
2
DMI_TXN0
DMI0TXN
FDI_RXP1
FDI_TXP1 2
LVD_IBG
SDVO_CTRLCLK
SDVO_CLK
21
AW20
BF14
LVDS_VBG
AF36
M39
2
DMI_TXN1
DMI1TXN
FDI_RXP2
FDI_TXP2 2
LVD_VBG
SDVO_CTRLDATA
SDVO_DATA
21
BB18
BG13
TP30TP30
2
DMI_TXN2
DMI2TXN
FDI_RXP3
FDI_TXP3 2
AV18
BE12
AE48
2
DMI_TXN3
DMI3TXN
FDI_RXP4
FDI_TXP4 2
LVD_VREFH
BG12
AE47
AT49
FDI_RXP5
FDI_TXP5 2
LVD_VREFL
DDPB_AUXN
AY24
BJ10
AT47
2
DMI_TXP0
DMI0TXP
FDI_RXP6
FDI_TXP6 2
DDPB_AUXP
AY20
BH9
AT40
DPB_HPD_Q
2
DMI_TXP1
DMI1TXP
FDI_RXP7
FDI_TXP7 2
DDPB_HPD
AY18
AK39
2
DMI_TXP2
DMI2TXP
20
TXLCLKOUT-
LVDSA_CLK#
AU18
AK40
AV42
DPB_LANE0_N
2
DMI_TXP3
DMI3TXP
20
TXLCLKOUT+
LVDSA_CLK
DDPB_0N
AW16
AV40
DPB_LANE0_P
FDI_INT
FDI_INT
2
DDPB_0P
AN48
AV45
DPB_LANE1_N
20
TXLOUT0-
LVDSA_DATA#0
DDPB_1N
BJ24
AV12
AM47
AV46
DPB_LANE1_P
DMI_ZCOMP
FDI_FSYNC0
FDI_FSYNC0
2
20
TXLOUT1-
LVDSA_DATA#1
DDPB_1P
AK47
AU48
DPB_LANE2_N
20
TXLOUT2-
LVDSA_DATA#2
DDPB_2N
R500
R500
49.9/F_4
49.9/F_4
DMI_COMP
BG25
BC10
AJ48
AU47
DPB_LANE2_P
+1.05V_VTT
DMI_IRCOMP
FDI_FSYNC1
FDI_FSYNC1
2
LVDSA_DATA#3
DDPB_2P
AV47
DPB_LANE3_N
DDPB_3N
R498
R498
750/F_4
750/F_4
DMI_RBIAS
BH21
AV14
AN47
AV49
DPB_LANE3_P
DMI2RBIAS
FDI_LSYNC0
FDI_LSYNC0
2
20
TXLOUT0+
LVDSA_DATA0
DDPB_3P
AM49
20
TXLOUT1+
LVDSA_DATA1
BB10
AK49
FDI_LSYNC1
FDI_LSYNC1
2
20
TXLOUT2+
LVDSA_DATA2
AJ47
P46
TP54TP54
LVDSA_DATA3
DDPC_CTRLCLK
P42
TP53TP53
DDPC_CTRLDATA
SUS_PWR_ACK_R
R489
R489
0_4
0_4
A18
DSWVREN
AF40
DSWVRMEN
20
TXUCLKOUT-
LVDSB_CLK#
AF39
AP47
20
TXUCLKOUT+
LVDSB_CLK
DDPC_AUXN
9/10 SI for H/W.
AP49
DDPC_AUXP
SUSACK#_R
C12
E22
R501
R501
0_4
0_4
RSMRST#
AH45
AT38
SUSACK#
DPWROK
20
TXUOUT0-
LVDSB_DATA#0
DDPC_HPD
AH47
20
TXUOUT1-
LVDSB_DATA#1
AF49
AY47
20
TXUOUT2-
LVDSB_DATA#2
DDPC_0N
C
XDP_DBRST#
C
K3
B9
PCIE_WAKE#
AF45
AY49
2
XDP_DBRST#
SYS_RESET#
WAKE#
PCIE_WAKE#
27,30
20
TXUOUT0+
LVDSB_DATA#3
DDPC_0P
AY43
20
TXUOUT1+
DDPC_1N
(+3V)
AH43
AY45
20
TXUOUT2+
LVDSB_DATA0
DDPC_1P
SYS_PWROK
R433
R433
0_4
0_4
SYS_PWROK_R
P12
N3
CLKRUN#
PD Res place close to PCH
AH49
BA47
SYS_PWROK
CLKRUN# / GPIO32
CLKRUN#
29
LVDSB_DATA1
DDPC_2N
AF47
BA48
LVDSB_DATA2
DDPC_2P
9/10 SI for H/W.
(+3VS5)
PCH to Res routeing 50 ohm Impedance.
Res to connector filter routeing 37.5ohm Impedance.
AF43
BB47
LVDSB_DATA3
DDPC_3N
R423
R423
0_4
0_4
EC_PWROK_R
L22
G8
BB49
17,29
EC_PWROK
PWROK
SUS_STAT# / GPIO61
TP21TP21
DDPC_3P
(+3VS5)
22
CRT_B
EC_PWROK_R
R233
R233
0_4
0_4
APWROK_R
L10
N14
PCH_SUSCLK_L
R249
R249
0_4
0_4
R282
R282
150/F_4
150/F_4
N48
M43
APWROK
SUSCLK / GPIO62
PCH_SUSCLK
29
CRT_BLUE
DDPD_CTRLCLK
P49
M36
22
CRT_G
CRT_GREEN
DDPD_CTRLDATA
(+3VS5)
R284
R284
150/F_4
150/F_4
T49
TP26TP26
CRT_RED
PM_DRAM_PWRGD
B13
D10
2 PM_DRAM_PWRGD
DRAMPWROK
SLP_S5# / GPIO63
SLP_S5
29
22
CRT_R
R283
R283
150/F_4
150/F_4
AT45
DDPD_AUXN
T39
AT43
22 DDCCLK
CRT_DDC_CLK
DDPD_AUXP
RSMRST#
C21
H4
R211
R211
0_4
0_4
M40
BH41
29
RSMRST#
RSMRST#
SLP_S4#
SUSC#
29
22 DDCDATA
CRT_DDC_DATA
DDPD_HPD
(+3VS5)
BB43
DDPD_0N
R477
R477
0_4
0_4
SUS_PWR_ACK_R
K16
F4
R467
R467
0_4
0_4
R296
R296
33_4
33_4
PCH_HSYNC_R
M47
BB45
29 SUS_PWR_ACK
SUSWARN#/SUSPWRDNACK/GPIO30
SLP_S3#
SUSB#
29
22
HSYNC_COM
CRT_HSYNC
DDPD_0P
R297
R297
33_4
33_4
PCH_VSYNC_R
M49
BF44
22
VSYNC_COM
CRT_VSYNC
DDPD_1N
BE44
DDPD_1P
R495
R495
0_4
0_4
DNBSWON#_R
5/11: add TP9048
E20
G10
BF42
29
DNBSWON#
PWRBTN#
SLP_A#
TP22TP22
DDPD_2N
R279
R279
1K/F_4
1K/F_4
DAC_IREF
T43
BE42
DAC_IREF
DDPD_2P
(DSW)
T42
BJ42
CRT_IRTN
DDPD_3N
R494
R494
0_4
0_4
AC_PRESENT_R
5/7: DEL R8304 , Add
TP9041
H20
G16
BG42
29
AC_PRESENT
ACPRESENT / GPIO31
SLP_SUS#
TP55TP55
DDPD_3P
(+3VS5)
CougarPoint_Rev_0p7
CougarPoint_Rev_0p7
PM_BATLOW#
E10
AP14
fcbga989-intel-cougarpoint
fcbga989-intel-cougarpoint
BATLOW# / GPIO72
PMSYNCH
PM_SYNC
2
AJ0QMZQ0T00
AJ0QMZQ0T00
(+3VS5)
IC CTRL(989P)COUGARPOINT QMVY TOP B/S
IC CTRL(989P)COUGARPOINT QMVY TOP B/S
B
SYS_PWROK_R
PM_RI#
A10
K14
SLP_LAN#
B
RI#
SLP_LAN# / GPIO29
+1.05V_VTT 2,4,7,8,10,29,32,33
C698
C698
+3V_RTC
7,10
CougarPoint_Rev_0p7
CougarPoint_Rev_0p7
*0.1U/10V_4
*0.1U/10V_4
+3V_DSW
fcbga989-intel-cougarpoint
fcbga989-intel-cougarpoint
+3VPCU
7,20,28,29,31,37
AJ0QMZQ0T00
AJ0QMZQ0T00
+3VS5
2,7,8,9,10,22,26,31,32,38,39
9/3 SI for H/W.
IC CTRL(989P)COUGARPOINT QMVY TOP B/S
IC CTRL(989P)COUGARPOINT QMVY TOP B/S
+3V
2,7,8,9,10,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,38,39
+5V
7,10,17,21,22,23,25,28,30,38
Reserve for R13 power on sequence
PCH Pull-high/low(CLG)
INT HDMI disable (DIS only remove)
System PWR_OK(CLG)
DPWROK FOR DSW
9/10 SI for EE
+3VS5
+3VS5
DPB_LANE0_N
IN_D2#
21
PM_RI#
R485
R485
10K_4
10K_4
DPB_LANE0_P
SYS_PWROK R420 R420
0_4 0_4 IMVP_PWRGD
C596
C596
*0.1U/10V_4
*0.1U/10V_4
IN_D2
21
DPB_LANE1_N
IN_D1#
21
PM_BATLOW#
R473
R473
*8.2K_4
*8.2K_4
DPB_LANE1_P
IN_D1
21
DPB_LANE2_N
IN_D0#
21
PCIE_WAKE#
R476
R476
10K_4
10K_4
DPB_LANE2_P
IN_D0
21
2 IMVP_PWRGD
33
DPB_LANE3_N
SYS_PWROK
4
Remove DSW power rail
IN_CLK#
21
SLP_LAN#
R260
R260
*10K_4
*10K_4
DPB_LANE3_P
1 EC_PWROK
IN_CLK
21
SUS_PWR_ACK
R474
R474
10K_4
10K_4
U21
U21
*TC7SH08FU
*TC7SH08FU
AC_PRESENT_R
R496
R496
10K_4
10K_4
R427
R427
INT HDMI Detect Function
*100K_4
*100K_4
A
+3V
R537
R537
0_4
0_4
A
CLKRUN#
R439
R439
8.2K_4
8.2K_4
R430
R430
*0_4
*0_4
XDP_DBRST#
R443
R443
10K_4
10K_4
DPB_HPD_Q
1
3
HDMI_HPD_CON
21
R459
R459
*1K_4
*1K_4
R493
R493
330K_4
330K_4
DSWVREN
R491
R491
*330K_4
*330K_4
+3V_RTC
Q40
Q40
RSMRST#
R503
R503
10K_4
10K_4
R535
R535
*2N7002K
*2N7002K
R546
R546
*100K_4
*100K_4
*100K_4
*100K_4
On Die DSW VR Enable
SYS_PWROK
R434
R434
*10K_4
*10K_4
+5V
High = Enable (Default)
Low = Disable
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
9/3 SI for H/W.
Custom
Custom
Custom
PCH 1/6 (DMI/FDI/VIDEO)
PCH 1/6 (DMI/FDI/VIDEO)
PCH 1/6 (DMI/FDI/VIDEO)
3A
3A
3A
1A
1A
1A
Date:
Date:
Date:
Saturday, September 18, 2010
Saturday, September 18, 2010
Saturday, September 18, 2010
Sheet
Sheet
Sheet
6
6 6
of
of
of
39
39
39
5
4
3
2
1
System Power Management
System Power Management
DMI
DMI
FDI
FDI
2
3
5
CRT
CRT
LVDS
LVDS
Digital Display Interface
Digital Display Interface

www.vinafix.vn

http://laptop-motherboard-schematic.blogspot.com/

5 4 3 2 1 Cougar Point (HDA,JTAG,SATA) TP58TP58 U24A U24A TP57TP57 +1.05V_VTT 2,4,6,8,10,29,32,33 RTC
5
4
3
2
1
Cougar Point (HDA,JTAG,SATA)
TP58TP58
U24A
U24A
TP57TP57
+1.05V_VTT 2,4,6,8,10,29,32,33
RTC Clock 32.768KHz
+1.8V
4,10,32,39
RTC_X1
A20
C38
RTCX1
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LAD0
29,30
+3V_RTC
6,10
A38
LAD1
29,30
+3V_DSW
RTC_X2
C20
B37
RTCX2
LAD2
29,30
+3VPCU
20,28,29,31,37
C37
C608
C608
18P/50V_4
18P/50V_4
LAD3
29,30
+3V
2,6,8,9,10,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,38,39
RTC_X1
RTC_RST#
D20
RTCRST#
+V3.3A_1.5A_HDA_IO
10
TP27TP27
D36
FWH4 / LFRAME#
LFRAME#
29,30
SRTC_RST#
G22
SRTCRST#
E36
PCH_DRQ#0
Y4
Y4
R499
R499
LDRQ0#
TP32TP32
R258
R258
1M_4
1M_4
SM_INTRUDER#
K22
K36
PCH_DRQ#1
32.768KHZ
32.768KHZ
10M_4
10M_4
+3V_RTC
INTRUDER#
LDRQ1# / GPIO23
TP31TP31
D
D
(+3V)
PCH_INVRMEN
C17
V5
SERIRQ
R234
R234
8.2K_4
8.2K_4
C609
C609
18P/50V_4
18P/50V_4
INTVRMEN
SERIRQ
+3V
RTC_X2
TP56TP56
SERIRQ
29
AM3
SATA0RXN
SATA_RXN0 23
ACZ_BCLK
N34
AM1
HDA_BCLK
SATA0RXP
SATA_RXP0 23
AP7
HDD0 (SATA3 6.0Gb/s)
SATA0TXN
SATA_TXN0 23
RF
ACZ_SYNC
L34
AP5
HDA_SYNC
SATA0TXP
SATA_TXP0 23
C408
C408
*10P/50V_4
*10P/50V_4
ACZ_SPKR
T10
AM10
25
ACZ_SPKR
SPKR
SATA1RXN
RTC Circuitry(RTC)
AM8
30mils
SATA1RXP
ACZ_RST#
K34
AP11
HDA_RST#
SATA1TXN
+3V_RTC
AP10
SATA1TXP
R567
R567
E34
AD7
RTC_RST#
25
ACZ_SDIN0
HDA_SDIN0
SATA2RXN
AD5
SATA2RXP
G34
AH5
20K/F_4
20K/F_4
TP29TP29
HDA_SDIN1
SATA2TXN
AH4
9/10 SI for H/W.
FOR DSW
SATA2TXP
C34
DG recommended that AC coupling capacitors should be
C683
C683
J1
J1
HDA_SDIN2
AB8
1U/6.3V_4
1U/6.3V_4
*SOLDERJUMPER-2
*SOLDERJUMPER-2
SATA3RXN
close to the connector (<100 mils) for optimal signal quality.
A34
AB10
R568
R568
HDA_SDIN3
SATA3RXP
AF3
R558
R558
0_6
0_6
+3V_RTC_2
20K/F_4
20K/F_4
SATA3TXN
+3VPCU
AF1
SRTC_RST#
SATA3TXP
ACZ_SDOUT
A36
+3V_RTC_0
R573
R573
1K_4
1K_4
+3V_RTC_1
HDA_SDO
Y7
SATA4RXN
SATA_RXN4 23
(+3V)
Y5
SATA4RXP
SATA_RXP4 23
GPIO33
C36
AD3
CN24
CN24
D14
D14
C687
C687
C692
C692
J2
J2
HDA_DOCK_EN# / GPIO33
SATA4TXN
SATA_TXN4 23
ODD (SATA1 1.5Gb/s)
AD1
BAT54C
BAT54C
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
*SOLDERJUMPER-2
*SOLDERJUMPER-2
BAT_CONN
BAT_CONN
(+3VS5)
SATA4TXP
SATA_TXP4 23
TP28TP28
N32
HDA_DOCK_RST# / GPIO13
DFWF02MS032
DFWF02MS032
Y3
8/25 SI for M/E.
SATA5RXN
50273-0027N-001-2P-L
50273-0027N-001-2P-L
C
Y1
RTC Power trace width 20mils.
4/20 DB add.
C
SATA5RXP
AB3
SATA5TXN
PCH_JTAG_TCK_R
J3
AB1
RTC_RST#
R253
R253
*0_6
*0_6
SRTC_RST#
TP49TP49
JTAG_TCK
SATA5TXP
TP15TP15
PCH_JTAG_TMS
H7
Y11
3/26 DB modify for placement.
JTAG_TMS
SATAICOMPO
PCH_JTAG_TDI_R
TP14TP14
K5
Y10
JTAG_TDI
SATAICOMPI
R244
SATA_COMP
R244
37.4/F_4
37.4/F_4
+1.05V_VTT
PCH JTAG Debug(CLG)
HDA Bus(CLG)
PCH_JTAG_TDO_R
H1
BIT_CLK_AUDIO
TP50TP50
JTAG_TDO
AB12
SATA3RCOMPO
+3VS5
EMI
AB13
49.9/F_4
49.9/F_4
SATA3COMPI
R246
SATA3_COMP
R246
C411
C411
R280
R280
33_4
33_4
ACZ_BCLK
25
BIT_CLK_AUDIO
PCH_SPI_CLK
T3
AH1
SATA3_RBIAS
R465
R465
750/F_4
750/F_4
*33P/50V_4
*33P/50V_4
SPI_CLK
SATA3RBIAS
PCH_SPI_CS0#
Y14
SPI_CS0#
R277
R277
33_4
33_4
ACZ_RST#
R225
R225
R202
R202
R463
R463
SATA_LED# 28
25
ACZ_RST#_AUDIO
R454
R454
*10K_4
*10K_4
PCH_SPI_CS1#
T1
210/F_4
210/F_4
210/F_4
210/F_4
210/F_4
210/F_4
+3VPCU
SPI_CS1#
P3
SATALED#
R438
R438
10K_4
10K_4
R514
R514
33_4
33_4
ACZ_SDOUT
+3V
25 ACZ_SDOUT_AUDIO
PCH_JTAG_TMS
(+3V)
PCH_SPI_SI
V4
V14
DGT_STOP#
PCH_JTAG_TDI_R
SPI_MOSI
SATA0GP / GPIO21
R529
R529
10K_4
10K_4
PCH_JTAG_TDO_R
(+3V)
+5V
PCH_SPI_SO
U3
P1
BBS_BIT0
PCH_JTAG_TCK_R
SPI_MISO
SATA1GP / GPIO19
R531
R531
33_4
33_4
1
3
ACZ_SYNC
25 ACZ_SYNC_AUDIO
CougarPoint_Rev_0p7
CougarPoint_Rev_0p7
DGT_STOP#
R217
R217
*10K_4
*10K_4
R224
R224
R219
R219
R462
R462
R446
R446
+3V
fcbga989-intel-cougarpoint
fcbga989-intel-cougarpoint
Q39
Q39
100/F_4
100/F_4
100/F_4
100/F_4
100/F_4
100/F_4
51_4
51_4
AJ0QMZQ0T00
AJ0QMZQ0T00
2N7002K
2N7002K
PCH Strap Table
IC CTRL(989P)COUGARPOINT QMVY TOP B/S
IC CTRL(989P)COUGARPOINT QMVY TOP B/S
B
B
Pin Name
Strap description
Sampled
Configuration
Circuit
Different from
0
= Default (weak pull-down 20K)
SPKR
No reboot mode setting
PWROK
1
= Setting to No-Reboot mode
ACZ_SPKR
R435
R435
*1K_4
*1K_4
+3V
Calpella
PCH SPI ROM(CLG)
TP47TP47
TP52TP52
0
= "top-block swap" mode
R522
R522
*1K_4
*1K_4
PCI_GNT3#
8
GNT3# / GPIO55
Top-Block Swap Override
PWROK
1
= Default (weak pull-up 20K)
R521
R521
10K_4
10K_4
+3V
TP48TP48
TP51TP51
+3V
U22
U22
INTVRMEN
Integrated 1.05V VRM enable
ALWAYS
Should be always pull-up
PCH_INVRMEN
R497
R497
330K_4
330K_4
PCH_SPI_CS0#
1
8
+3V_RTC
CE#
VDD
PCH_SPI_CLK
R479
R479
0_4
0_4
PCH_SPI1_CLK_R
6
SCK
Flash Descriptor Security
Only for Interposer
0 = Override
PCH_SPI_SI
R216
R216
0_4
0_4
PCH_SPI1_SI_R
5
SI
HDA_DOCK_EN#/GPIO33
PWROK
1 = Default (weak pull-up 20K)
GPIO33
R509
R509
1K_4
1K_4
PCH_SPI_SO
R437
R437
0_4
0_4
PCH_SPI1_SO_R
PCH_SPI1_SO_R
2
7
R480
R480
3.3K_4
3.3K_4
GPIO33_E
29
SO
HOLD#
RF
3
4
WP#
VSS
GNT1# / GPIO51
Boot BIOS Selection 1 [bit-1]
PWROK
GNT1#
GNT0#
Boot Location
[Need external pull-down for LPC BIOS]
Default weak pull-up on GNT0/1#
C598
C598
C597
C597
C599
C599
1
1
SPI
BBS_BIT0
*22P/50V_4
*22P/50V_4
*22P/50V_4
*22P/50V_4
W25Q32BVSSIG
W25Q32BVSSIG
0.1U/10V_4
0.1U/10V_4
Different from
0
0
LPC
R455
R455
*1K_4
*1K_4
GPIO19
Boot BIOS Selection 0 [bit-0]
PWROK
R523
R523
*1K_4
*1K_4
BBS_BIT1
8
Calpella
R432
R432
3.3K_4
3.3K_4
+3V
GNT2# / GPIO53
ESI strap (Server only)
PWROK
Should not be pull-down
(weak pull-up 20K)
USE GPIO PIN
NV_ALE
Intel Anti-Theft HDD protection
Only for Interposer
Vender
Size
P/N
PWROK
0
= Disable (Internal pull-down 20kohm)
R468
R468
*1K_4
*1K_4
+1.8V
NV_ALE
8
EON
4MB
AKE39FN0Q00 (EN25F32-100HIP)
NV_CLE
DMI Termination voltage
PWROK
weak pull-down 20kohm
R470
R470
2.2K_4
2.2K_4
R469
R469
4.7K_4
4.7K_4
N.A at CPT EDS 0.7
+1.8V
NV_CLE
8
Winbond
4MB
AKE391P0N00 (W25Q32BVSSIG)
H_SNB_IVB#
2
A
HDA_SYNC
On-Die PLL VR Voltage Select
RSMRST
0
= Support by 1.8V (weak pull-down)
R278
R278
1K_4
1K_4
ACZ_SYNC
A
Socket
DG008000031
+3VS5
1
= Support by 1.5V
0
= Override
HDA_SDO
Flash Descriptor Security
PWROK
1
= Default (weak pull-up 20K)
ACZ_SDOUT
R510
R510
*1K_4
*1K_4
+V3.3A_1.5A_HDA_IO
GPIO8
Integrated Clock Chip Enable
RSMRST#
Should be pull-down (weak pull-up 20K)
R483
R483
*1K_4
*1K_4
ICC_EN#
9
Different from
0
= Disable
GPIO28
On-die PLL Voltage Regulator
RSMRST#
1
= Enable (Default)
R447
R447
*1K_4
*1K_4
Calpella
PLL_ODVR_EN
9
0
= Default (weak pull-down 20K)
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
SPI_MOSI
iTPM function Disable
APWROK
1
= Enable
PCH_SPI_SI
R198
R198
1K_4
1K_4
Custom
Custom
Custom
PCH 2/6 (SATA/HDA/SPI)
PCH 2/6 (SATA/HDA/SPI)
PCH 2/6 (SATA/HDA/SPI)
3A
3A
3A
1A
1A
1A
+3V
Date:
Date:
Date:
Saturday, September 18, 2010
Saturday, September 18, 2010
Saturday, September 18, 2010
Sheet
Sheet
Sheet
7
7
7
of
of
of
39
39
39
5
4
3
2
1
SPI
SPI
JTAG
JTAG
RTCIHDA
RTCIHDA
SATA
SATA
LPC
LPC
SATA 6G
SATA 6G
12
2
23
4
1
12
12

www.vinafix.vn

http://laptop-motherboard-schematic.blogspot.com/

5

4

3

2

1

Cougar Point-M (PCI,USB,NVRAM)

Cougar Point-M (PCI-E,SMBUS,CLK)

PCI/USBOC# Pull-up(CLG) U24E U24E U24B U24B AY7 NV_CE#0 +3V AV7 BG34 (+3VS5) 30 PCIE_RXN1 NV_CE#1
PCI/USBOC# Pull-up(CLG)
U24E
U24E
U24B
U24B
AY7
NV_CE#0
+3V
AV7
BG34
(+3VS5)
30
PCIE_RXN1
NV_CE#1
PERN1
BG26
AU3
BJ34
E12
SMBALERT#
30
PCIE_RXP1
TP1
NV_CE#2
PERP1
SMBALERT# / GPIO11
PCI_PIRQA#
R294
R294
8.2K_4
8.2K_4
BJ26
BG4
WLAN
C399
C399
0.1U/10V_4
0.1U/10V_4
PCIE_TXN1_C
AV32
30
PCIE_TXN1
TP2
NV_CE#3
PETN1
PCI_PIRQB#
R286
R286
8.2K_4
8.2K_4
BH25
C396
C396
0.1U/10V_4
0.1U/10V_4
PCIE_TXP1_C
AU32
H14
SMB_PCH_CLK
30
PCIE_TXP1
TP3
PETP1
SMBCLK
PCI_PIRQC#
R287
R287
8.2K_4
8.2K_4
BJ16
AT10
TP4
NV_DQS0
PCI_PIRQD#
R295
R295
8.2K_4
8.2K_4
BG16
BC8
BE34
C9
SMB_PCH_DAT
27
PCIE_RXN2_LAN
TP5
NV_DQS1
PERN2
SMBDATA
AH38
BF34
27
PCIE_RXP2_LAN
TP6
PERP2
AH37
AU2
LAN
C398
C398
0.1U/10V_4
0.1U/10V_4
PCIE_TXN2_LAN_C
BB32
27
PCIE_TXN2_LAN
TP7
NV_DQ0 / NV_IO0
PETN2
+3V
AK43
AT4
C397
C397
0.1U/10V_4
0.1U/10V_4
PCIE_TXP2_LAN_C
AY32
(+3VS5)
27
PCIE_TXP2_LAN
TP8
NV_DQ1 / NV_IO1
PETP2
RP8
RP8
AK45
AT3
A12
DRAMRST_CNTRL_PCH
D
D
DRAMRST_CNTRL_PCH
2
TP9
NV_DQ2 / NV_IO2
SML0ALERT# / GPIO60
10
1 DGPU_HOLD_RST#
C18
AT1
BG36
24
PCIE_RXN3_CARD
TP10
NV_DQ3 / NV_IO3
PERN3
MPC_PWR_CTRL#
9
2 INTH#
N30
AY3
Cardreader
BJ36
C8
SMB_ME0_CLK
24
PCIE_RXP3_CARD
TP11
NV_DQ4 / NV_IO4
PERP3
SML0CLK
8
3 BT_COMBO_EN#
H3
AT5
C405
C405
0.1U/10V_4
0.1U/10V_4
PCIE_TXN3_CARD_C
AV34
24
PCIE_TXN3_CARD
TP12
NV_DQ5 / NV_IO5
PETN3
EDID_SELECT#
7
4 AH12
DGPU_SELECT#
AV3
C404
C404
0.1U/10V_4
0.1U/10V_4
PCIE_TXP3_CARD_C
AU34
G12
SMB_ME0_DAT
24
PCIE_TXP3_CARD
TP13
NV_DQ6 / NV_IO6
PETP3
SML0DATA
LCD_BK
6
5 AM4
AV1
TP14
NV_DQ7 / NV_IO7
AM5
BB1
BF36
TP15
NV_DQ8 / NV_IO8
PERN4
10K_10P8R_6
10K_10P8R_6
Y13
BA3
BE36
(+3VS5)
TP16
NV_DQ9 / NV_IO9
PERP4
K24
BB5
AY34
C13
SML1ALERT#_R
TP18TP18
TP17
NV_DQ10 / NV_IO10
PETN4
SML1ALERT# / PCHHOT# / GPIO74
L24
BB3
BB34
TP18
NV_DQ11 / NV_IO11
PETP4
(+3VS5)
+3VS5
AB46
BB7
E14
SMB_ME1_CLK
TP19
NV_DQ12 / NV_IO12
SML1CLK / GPIO58
RP6
RP6
AB45
BE8
BG37
TP20
NV_DQ13 / NV_IO13
PERN5
(+3VS5)
10
1 USB_OC6#
BD4
BH37
M16
SMB_ME1_DAT
NV_DQ14 / NV_IO14
PERP5
SML1DATA / GPIO75
USB_OC4#
9
2 USB_OC0#
BF6
AY36
NV_DQ15 / NV_IO15
PETN5
USB_OC1#
8
3 USB_OC7#
BB36
PETP5
USB_OC2#
7
4 USB_OC5#
B21
AV5
NV_ALE
TP21
NV_ALE
USB_OC3#
6
5 M20
AY1
NV_CLE
TP22
NV_CLE
NV_ALE
7
BJ38
NV_CLE
7
PERN6
AY16
BG38
TP23
PERP6
10K_10P8R_6
10K_10P8R_6
BG46
AV10
AU36
M7
CL_CLK_R
TP20TP20
TP24
NV_RCOMP
PETN6
CL_CLK1
+3V
AV36
PETP6
AT8
NV_RB#
C646
C646
*0.1U/10V_4
*0.1U/10V_4
BG40
T11
CL_DAT_R
DGPU_PWROK
9,17,29,35,39
TP16TP16
PERN7
CL_DATA1
MPC Switch Control
BE28
AY5
BJ40
TP25
NV_RE#_WRB0
PERP7
BC30
BA2
U25
U25
AY40
TP26
NV_RE#_WRB1
PETN7
BE32
P10
CL_RST#_R
TP24TP24
TP27
CL_RST1#
MPC_PWR_CTRL#
Low = MPC ON
High = MPC OFF (Default)
BB40
PETP7
BJ32
AT12
PCH_CLK_27M_1
2
4
TP28
NV_WE#_CK0
PCH_CLK_27M
15
BC28
BF3
BE38
TP29
NV_WE#_CK1
PERN8
BE30
9/3 SI for H/W.
*74LVC1G126
*74LVC1G126
BC38
TP30
PERP8
MPC_PWR_CTRL#
R519
R519
*1K_4
*1K_4
BF32
AW38
TP31
PETN8
BG32
C24
AY38
(+3VS5)
TP32
USBP0N
USBP0-
26
PETP8
AV26
A24
Left_USB
M10
CLK_PEGA_REQ#
TP33
USBP0P
USBP0+
26
PEG_A_CLKRQ# / GPIO47
BB26
C25
TP34
USBP1N
USBP1-
26
AU28
B25
Left_USB 2
CLK_PCH_SRC0N
Y40
C
TP35
USBP1P
USBP1+
26
CLKOUT_PCIE0N
C
DGPU_HOLD_RST#
AY30
C26
CLK_PCH_SRC0P
Y39
AB37
CLK_PCH_PEGAN
9,14
DGPU_HOLD_RST#
TP36
USBP2N
CLKOUT_PCIE0P
CLKOUT_PEG_A_N
AU26
A26
AB38
CLK_PCH_PEGAP
TP37
USBP2P
CLKOUT_PEG_A_P
AY26
K28
CLK_PCIE_REQ0#
9/3 SI for H/W.
J2
TP38
USBP3N
PCIECLKRQ0# / GPIO73
AV28
H28
TP39
USBP3P
AW30
E28
(+3VS5)
AV22
USBP4-
CLK_CPU_BCLKN
2
TP40
USBP4N
20
CLKOUT_DMI_N
D28
Webcam
CLK_PCH_SRC2N
AB49
AU22
CLK_CPU_BCLKP
2
USBP4P
USBP4+
20
CLKOUT_PCIE1N
CLKOUT_DMI_P
C28
CLK_PCH_SRC2P
AB47
USBP5N
CLKOUT_PCIE1P
A28
CLOCKS
CLOCKS
24
CLK_PCIE_CARDN
USBP5P
C29
CLK_PCIE_REQ1#
M1
AM12
24
CLK_PCIE_CARDP
CLK_DPLL_SSCLKN
2
USBP6N
PCIECLKRQ1# / GPIO18
CLKOUT_DP_N
B29
AM13
CLK_DPLL_SSCLKP
2
USBP6P
CLKOUT_DP_P
PCI_PIRQA#
K40
N28
(+3V)
PIRQA#
USBP7N
PCI_PIRQB#
K38
M28
RP7
RP7
1
2
CLK_PCH_CARD2N
AA48
PIRQB#
USBP7P
PCI_PIRQC#
H38
L30
0_4P2R_4
0_4P2R_4
3
4
CLK_PCH_CARD2P
AA47
BF18
CLK_BUF_PCIE_3GPLL#
PIRQC#
USBP8N
USBP8-
26
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
PCI_PIRQD#
G38
K30
Right_USB
BE18
CLK_BUF_PCIE_3GPLL
PIRQD#
USBP8P
USBP8+
26
CLKIN_DMI_P
G30
CLK_PCIE_REQ2#
V10
24 CLK_PCIE_REQ2#
USBP9N
PCIECLKRQ2# / GPIO20
BT_COMBO_EN#
C46
E30
30 BT_COMBO_EN#
(+3V)
USBP9P
DGPU_SELECT#
C44
C30
(+3V)
BJ30
CLK_BUF_BCLK_N
(+3V)
USBP10N
USBP10-
30
CLKIN_GND1_N
EDID_SELECT#
E40
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
A30
(+3V)
WLAN
Y37
BG30
CLK_BUF_BCLK_P
USBP10P
USBP10+
30
CLKOUT_PCIE3N
CLKIN_GND1_P
L32
Y36
USBP11N
CLKOUT_PCIE3P
BBS_BIT1
D47
K32
7
BBS_BIT1
(+3V)
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
USBP11P
PWM_SELECT#
E42
G32
CLK_PCIE_REQ3#
A8
G24
CLK_BUF_DREFCLK#
TP33TP33
(+3V)
USBP12N
PCIECLKRQ3# / GPIO25
CLKIN_DOT_96N
PCI_GNT3#
F46
E32
E24
CLK_BUF_DREFCLK
7
PCI_GNT3#
(+3V)
USBP12P
CLKIN_DOT_96P
C32
(+3VS5)
USBP13N
USBP2-
26
A32
Blue tooth
Y43
USBP13P
USBP2+
26
CLKOUT_PCIE4N
MPC_PWR_CTRL#
G42
Y45
AK7
CLK_BUF_DREFSSCLK#
(+3V)
PIRQE# / GPIO2
CLKOUT_PCIE4P
CLKIN_SATA_N
LCD_BK
G40
AK5
CLK_BUF_DREFSSCLK
20
LCD_BK
(+3V)
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
CLKIN_SATA_P
BOARD_ID4
C42
C33
USB_BIAS
CLK_PCIE_REQ4#
L12
9
BOARD_ID4
(+3V)
USBRBIAS#
PCIECLKRQ4# / GPIO26
INTH#
D44
(+3V)
change 25M to small size
R508
R508
9/3 SI for H/W.
(+3VS5)
CLK_PCH_14M
K45
REFCLK14IN
B33
22.6/F_4
22.6/F_4
V45
RF
USBRBIAS
PCI_PME#
K10
V46
TP19TP19
PME#
CLKOUT_PCIE5N
9/8 SI for TXC
TP59TP59
CLKOUT_PCIE5P
H45
CLK_PCI_FB
CLK_PCH_14M
CLKIN_PCILOOPBACK
PCI_PLTRST#
C6
A14
USB_OC0#
L14
33P/50V_4
C621
C621
33P/50V_4
B
B
9
BOARD_ID0
PLTRST#