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http://laptop-motherboard-schematic.blogspot.com/
5 4 3 2 1

Sandy Bridge Processor (DMI,PEG,FDI)


U15A
PEG_ICOMPI J22
J21
PEG_COMP PEG_COMP connect to PIN H22&J22 W:4mils/S:15mils/L: 500mils.
Sandy Bridge Processor (CLK,MISC,JTAG)
U15B

PEG_ICOMPO PEG_COMP connect to PIN J21 W:12mils/S:15mils/L: 500mils.
6 DMI_TXN0 B27 DMI_RX#[0] PEG_RCOMPO H22
6 DMI_TXN1 B25 DMI_RX#[1] PEG_RX#[0..7] 14 BCLK A28 CLK_CPU_BCLKP 8
A25 C26 A27

MISC

CLOCKS
6 DMI_TXN2 DMI_RX#[2] 7 H_SNB_IVB# SNB_IVB# BCLK# CLK_CPU_BCLKN 8
B24 K33 PEG_RX#0
6 DMI_TXN3 DMI_RX#[3] PEG_RX#[0]
M35 PEG_RX#1
PEG_RX#[1] PEG_RX#2 SKTOCC#
6 DMI_TXP0 B28 DMI_RX[0] PEG_RX#[2] L34 SNB_IVB# N.A at SNB EDS #27637 0.7v1 TP4 AN34 SKTOCC#
D B26 J35 PEG_RX#3 A16 CLK_DPLL_SSCLKP D
6 DMI_TXP1 DMI_RX[1] PEG_RX#[3] DPLL_REF_SSCLK
A24 J32 PEG_RX#4 A15 CLK_DPLL_SSCLKN
6 DMI_TXP2 DMI_RX[2] PEG_RX#[4] PEG_RX#5 DPLL_REF_SSCLK#

DMI
6 DMI_TXP3 B23 DMI_RX[3] PEG_RX#[5] H34
H31 PEG_RX#6
PEG_RX#[6] PEG_RX#7 TP_CATERR#
6 DMI_RXN0 G21 DMI_TX#[0] PEG_RX#[7] G33 TP2 AL33 CATERR#
6 DMI_RXN1 E22 DMI_TX#[1] PEG_RX#[8] G30
6 DMI_RXN2 F21 DMI_TX#[2] PEG_RX#[9] F35 Placement close to EC.
D21 E34

THERMAL
6 DMI_RXN3 DMI_TX#[3] PEG_RX#[10]
E32 R386 43_4 H_PECI AN33 R8 CPU_DRAMRST#
PEG_RX#[11] 29 EC_PECI PECI SM_DRAMRST#
6 DMI_RXP0 G22 DMI_TX[0] PEG_RX#[12] D33
D22 D31

DDR3
MISC
6 DMI_RXP1 DMI_TX[1] PEG_RX#[13]
6 DMI_RXP2 F20 DMI_TX[2] PEG_RX#[14] B33
C21 C32 PEG_RX[0..7] 14 29,33 H_PROCHOT# R146 56.2/F_4 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R143 140/F_4
6 DMI_RXP3 DMI_TX[3] PEG_RX#[15] PROCHOT# SM_RCOMP[0]

PCI EXPRESS* - GRAPHICS


A5 SM_RCOMP_1 R318 26.1/F_4
PEG_RX0 SM_RCOMP[1] SM_RCOMP_2 R316 200/F_4
PEG_RX[0] J33 SM_RCOMP[2] A4
L35 PEG_RX1
PEG_RX[1] PEG_RX2 R148 0_4 PM_THRMTRIP#_R AN32
PEG_RX[2] K34 9,29 PM_THRMTRIP# THERMTRIP# SM_RCOMP[0] W:20mils/S:20mils/L: 500mils,
A21 H35 PEG_RX3
6 FDI_TXN0 FDI0_TX#[0] PEG_RX[3] PEG_RX4
SM_RCOMP[1] W:20mils/S:20mils/L: 500mils,
6 FDI_TXN1 H19 FDI0_TX#[1] PEG_RX[4] H32
E19 G34 PEG_RX5 SM_RCOMP[2] W:15mils/S:20mils/L: 500mils,
6 FDI_TXN2 FDI0_TX#[2] PEG_RX[5]
F18 G31 PEG_RX6
6 FDI_TXN3 FDI0_TX#[3] PEG_RX[6]
B21 F33 PEG_RX7 AP29 XDP_PRDY# TP12
6 FDI_TXN4
Intel(R) FDI

FDI1_TX#[0] PEG_RX[7] PRDY# XDP_PREQ#


6 FDI_TXN5 C20 FDI1_TX#[1] PEG_RX[8] F30 PREQ# AP27 TP11 CPU XDP
6 FDI_TXN6 D18 FDI1_TX#[2] PEG_RX[9] E35
E17 E33 AR26 XDP_TCLK TP8
6 FDI_TXN7 FDI1_TX#[3] PEG_RX[10] TCK XDP_TMS
F32 AR27 TP10

PWR MANAGEMENT
PEG_RX[11] TMS

JTAG & BPM


D34 R377 0_4 PM_SYNC_R AM34 AP30 XDP_TRST#
PEG_RX[12] 6 PM_SYNC PM_SYNC TRST# TP13
6 FDI_TXP0 A22 FDI0_TX[0] PEG_RX[13] E31
G19 C33 AR28 XDP_TDI_R
6 FDI_TXP1 FDI0_TX[1] PEG_RX[14] TDI TP39
E20 B32 AP26 XDP_TDO TP7
C 6 FDI_TXP2 FDI0_TX[2] PEG_RX[15] H_PWRGOOD_R TDO C
G18 9 H_PWRGOOD R378 0_4 AP33
6 FDI_TXP3 FDI0_TX[3] UNCOREPW RGOOD
B20 M29 C_PEG_TX#0 R375 *1K_4
6 FDI_TXP4 FDI1_TX[0] PEG_TX#[0] +3V
C19 M32 C_PEG_TX#1 R384 10K_4
6 FDI_TXP5 FDI1_TX[1] PEG_TX#[1]
D19 M31 C_PEG_TX#2 AL35 XDP_DBRST# XDP_DBRST# 6
6 FDI_TXP6 FDI1_TX[2] PEG_TX#[2] DBR#
F17 L32 C_PEG_TX#3 9/15 SI for H/W. PM_DRAM_PWRGD_R V8
6 FDI_TXP7 FDI1_TX[3] PEG_TX#[3] C_PEG_TX#4 SM_DRAMPW ROK
PEG_TX#[4] L29
J18 K31 C_PEG_TX#5 AT28 XDP_BPM0 TP40
6 FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5] C_PEG_TX#6 BPM#[0] XDP_BPM1
J17 K28 +1.05V_VTT R404 *75/F_4 AR29 TP41
6 FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] BPM#[1]
J30 C_PEG_TX#7 U18 AR30 XDP_BPM2
H20
PEG_TX#[7]
J28
CPU RESET# 3 4 CPU_PLTRST# R400 *43_4 CPU_PLTRST#_R AR33
BPM#[2]
AT30 XDP_BPM3
TP43
TP42
6 FDI_INT FDI_INT PEG_TX#[8] GND OUT RESET# BPM#[3] XDP_BPM4
PEG_TX#[9] H29 BPM#[4] AP32 TP5
J19 G27 2 +3VS5 AR31 XDP_BPM5
6 FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10] 8,14,24,27,29,30 PLTRST# IN C560 BPM#[5] TP45
H17 E29 AT31 XDP_BPM6 TP44
6 FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] BPM#[6]
F27 1 5 R401 AR32 XDP_BPM7
PEG_TX#[12] NC VCC BPM#[7] TP46
PEG_TX#[13] D28
F26 *74LVC1G07GW 750/F_4
PEG_TX#[14] 0.1U/10V_4 Sandy Bridge_rPGA_Rev0p61
PEG_TX#[15] E25
eDP_COMP A18 rpga989-47989-socket
eDP_COMPIO C_PEG_TX0 R402 1.5K/F_4 DGG^9000005
A17 eDP_ICOMPO PEG_TX[0] M28
INT_eDP_HPD_Q B16 M33 C_PEG_TX1 IC SOCKET RPGA 989P(P1.0,M/H3.0)
eDP_HPD PEG_TX[1]
PEG_TX[2] M30
L31
C_PEG_TX2
C_PEG_TX3
SM_DRAMPWROK Processor Input. DDR3 DRAM RESET
PEG_TX[3] C_PEG_TX4 +3VS5 +3VS5
C15 eDP_AUX PEG_TX[4] L28
D15 K30 C_PEG_TX5 R311 1K_4 R313 *0_4
eDP_AUX# PEG_TX[5] +1.5V_CPU +1.5VSUS
K27 C_PEG_TX6
PEG_TX[6] C_PEG_TX7
eDP

PEG_TX[7] J29
C17 J27 R312 1K_4 3 1 CPU_DRAMRST#
eDP_TX[0] PEG_TX[8] 12,13 DDR3_DRAMRST#
F16 H28 R49 U2 C27
eDP_TX[1] PEG_TX[9] 10K_4 0.1U/10V_4
C16 eDP_TX[2] PEG_TX[10] G28 1 NC VCC 5
G15 E28 R40 CPU_DRAMRST#_R Q24

2
B eDP_TX[3] PEG_TX[11] PM_DRAM_PWRGD_PU 200/F_4 2N7002 B
PEG_TX[12] F28 2 IN
C18 D27 8 DRAMRST_CNTRL_PCH R315 0_4
eDP_TX#[0] PEG_TX[13] PM_DRAM_PWRGD_C R42 130/F_4 PM_DRAM_PWRGD_R R314
E16 eDP_TX#[1] PEG_TX[14] E26 3 GND OUT 4
D16 D25 R37 C442 4.99K/F_4
eDP_TX#[2] PEG_TX[15] R48 *74LVC1G07GW 0.047U/10V_4
F15 eDP_TX#[3] *0_4

3
*39_4
Sandy Bridge_rPGA_Rev0p61 PM_DRAM_PWRGD 6
rpga989-47989-socket
DGG^9000005 2 MAIN_ONG 4,38
IC SOCKET RPGA 989P(P1.0,M/H3.0) R47 0_4 PM_DRAM_PWRGD_R
+1.05V_VTT 4,6,7,8,10,29,32,33
eDP_COMP connect to PIN A18 W:4mils/S:15mils/L: 500mils. R43 Q3
+1.5V_CPU 4
*3K/F_4 *2N7002
eDP_COMP connect to PIN A17 W:12mils/S:15mils/L: 500mils. +3VS5 6,7,8,9,10,22,26,31,32,38,39

1
+3V 6,7,8,9,10,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,38,39

FDI disable PEG x16 disable (UMA only remove) Embedded Display PLL Clock DP & PEG Compensation Processor pull-up (CPU)
(DIS only stuff) 14 PEG_TX[0..7] 14 PEG_TX#[0..7]
Ra
3/26 DB change
Part reference. +1.05V_VTT R67 10K_4 INT_eDP_HPD_Q +1.05V_VTT

C_PEG_TX0 C483 0.1U/10V_4 PEG_TX0 C_PEG_TX#0 C488 0.1U/10V_4 PEG_TX#0 CLK_DPLL_SSCLKP H_PROCHOT# R145 62_4
CLK_DPLL_SSCLKP 8
C_PEG_TX1 C489 0.1U/10V_4 PEG_TX1 C_PEG_TX#1 C490 0.1U/10V_4 PEG_TX#1 CLK_DPLL_SSCLKN CLK_DPLL_SSCLKN 8 +1.05V_VTT R319 24.9/F_4 eDP_COMP XDP_TDO R155 51_4
C_PEG_TX2 C492 0.1U/10V_4 PEG_TX2 C_PEG_TX#2 C496 0.1U/10V_4 PEG_TX#2 XDP_TMS R159 51_4
C_PEG_TX3 C498 0.1U/10V_4 PEG_TX3 C_PEG_TX#3 C500 0.1U/10V_4 PEG_TX#3 XDP_TDI_R R403 51_4
C_PEG_TX4 C501 0.1U/10V_4 PEG_TX4 C_PEG_TX#4 C503 0.1U/10V_4 PEG_TX#4 eDP_COMPIO and ICOMPO signals should be shorted XDP_PREQ# R158 *51_4
A DEL C_PEG_TX5 C504 0.1U/10V_4 PEG_TX5 C_PEG_TX#5 C507 0.1U/10V_4 PEG_TX#5
near balls and routed with typical impedance <25 mohms
XDP_TCLK R156 51_4 A
C_PEG_TX6 C508 0.1U/10V_4 PEG_TX6 C_PEG_TX#6 C511 0.1U/10V_4 PEG_TX#6 XDP_TRST# R163 51_4
C_PEG_TX7 C512 0.1U/10V_4 PEG_TX7 C_PEG_TX#7 C517 0.1U/10V_4 PEG_TX#7
DEL +1.05V_VTT R85 24.9/F_4 PEG_COMP

FDI_FSYNC can gang all these 4


Ra Rb Rc PEG_ICOMPI and RCOMPO signals 352-(&75
signals together and tie them DIS NC Stuff Stuff
should be routed within 500 mils typical
impedance = 43 mohms PEG_ICOMPO
4XDQWD&RPSXWHU,QF
with only one 1K resistor to GND
SG/UMA Stuff NC NC signals should be routed within 500 mils
(DG V0.5 Ch2.2.9). Size Document Number Rev
typical impedance = 14.5 mohms
1%
0.22uF AC coupling Caps for PCIE GEN1/2/3 0.22uF AC coupling Caps for PCIE GEN1/2/3 Custom SNB 1/4 (PCIE&DMI&FDI) 3A

Date: Saturday, September 18, 2010 Sheet 2 of 39


5 4 3 2 1

www.vinafix.vn
http://laptop-motherboard-schematic.blogspot.com/
5 4 3 2 1

Sandy Bridge Processor (DDR3) 


U15C U15D

D D

SA_CLK[0] AB6 M_A_CLKP0 12 13 M_B_DQ[63:0] SB_CLK[0] AE2 M_B_CLKP0 13


12 M_A_DQ[63:0] SA_CLK#[0] AA6 M_A_CLKN0 12 SB_CLK#[0] AD2 M_B_CLKN0 13
M_A_DQ0 C5 V9 M_A_CKE0 12 M_B_DQ0 C9 R9 M_B_CKE0 13
M_A_DQ1 SA_DQ[0] SA_CKE[0] M_B_DQ1 SB_DQ[0] SB_CKE[0]
D5 SA_DQ[1] A7 SB_DQ[1]
M_A_DQ2 D3 M_B_DQ2 D10
M_A_DQ3 SA_DQ[2] M_B_DQ3 SB_DQ[2]
D2 SA_DQ[3] C8 SB_DQ[3]
M_A_DQ4 D6 AA5 M_B_DQ4 A9 AE1
SA_DQ[4] SA_CLK[1] M_A_CLKP1 12 SB_DQ[4] SB_CLK[1] M_B_CLKP1 13
M_A_DQ5 C6 AB5 M_B_DQ5 A8 AD1
SA_DQ[5] SA_CLK#[1] M_A_CLKN1 12 SB_DQ[5] SB_CLK#[1] M_B_CLKN1 13
M_A_DQ6 C2 V10 M_A_CKE1 12 M_B_DQ6 D9 R10 M_B_CKE1 13
M_A_DQ7 SA_DQ[6] SA_CKE[1] M_B_DQ7 SB_DQ[6] SB_CKE[1]
C3 SA_DQ[7] D8 SB_DQ[7]
M_A_DQ8 F10 M_B_DQ8 G4
M_A_DQ9 SA_DQ[8] M_B_DQ9 SB_DQ[8]
F8 SA_DQ[9] F4 SB_DQ[9]
M_A_DQ10 G10 AB4 M_B_DQ10 F1 AB2
M_A_DQ11 SA_DQ[10] SA_CLK[2] M_B_DQ11 SB_DQ[10] SB_CLK[2]
G9 SA_DQ[11] SA_CLK#[2] AA4 G1 SB_DQ[11] SB_CLK#[2] AA2
M_A_DQ12 F9 W9 M_B_DQ12 G5 T9
M_A_DQ13 SA_DQ[12] SA_CKE[2] M_B_DQ13 SB_DQ[12] SB_CKE[2]
F7 SA_DQ[13] F5 SB_DQ[13]
M_A_DQ14 G8 M_B_DQ14 F2
M_A_DQ15 SA_DQ[14] M_B_DQ15 SB_DQ[14]
G7 SA_DQ[15] G2 SB_DQ[15]
M_A_DQ16 K4 AB3 M_B_DQ16 J7 AA1
M_A_DQ17 SA_DQ[16] SA_CLK[3] M_B_DQ17 SB_DQ[16] SB_CLK[3]
K5 SA_DQ[17] SA_CLK#[3] AA3 J8 SB_DQ[17] SB_CLK#[3] AB1
M_A_DQ18 K1 W 10 M_B_DQ18 K10 T10
M_A_DQ19 SA_DQ[18] SA_CKE[3] M_B_DQ19 SB_DQ[18] SB_CKE[3]
J1 SA_DQ[19] K9 SB_DQ[19]
M_A_DQ20 J5 M_B_DQ20 J9
M_A_DQ21 SA_DQ[20] M_B_DQ21 SB_DQ[20]
J4 SA_DQ[21] J10 SB_DQ[21]
M_A_DQ22 J2 AK3 M_A_CS#0 12 M_B_DQ22 K8 AD3 M_B_CS#0 13
M_A_DQ23 SA_DQ[22] SA_CS#[0] M_B_DQ23 SB_DQ[22] SB_CS#[0]
K2 SA_DQ[23] SA_CS#[1] AL3 M_A_CS#1 12 K7 SB_DQ[23] SB_CS#[1] AE3 M_B_CS#1 13
M_A_DQ24 M8 AG1 M_B_DQ24 M5 AD6
M_A_DQ25 SA_DQ[24] SA_CS#[2] M_B_DQ25 SB_DQ[24] SB_CS#[2]
N10 SA_DQ[25] SA_CS#[3] AH1 N4 SB_DQ[25] SB_CS#[3] AE6
M_A_DQ26 N8 M_B_DQ26 N2
C M_A_DQ27 SA_DQ[26] M_B_DQ27 SB_DQ[26] C
N7 SA_DQ[27] N1 SB_DQ[27]
M_A_DQ28 M10 M_B_DQ28 M4
M_A_DQ29 SA_DQ[28] M_B_DQ29 SB_DQ[28]
M9 SA_DQ[29] SA_ODT[0] AH3 M_A_ODT0 12 N5 SB_DQ[29] SB_ODT[0] AE4 M_B_ODT0 13

DDR SYSTEM MEMORY B


M_A_DQ30 N9 AG3 M_B_DQ30 M2 AD4
DDR SYSTEM MEMORY A
SA_DQ[30] SA_ODT[1] M_A_ODT1 12 SB_DQ[30] SB_ODT[1] M_B_ODT1 13
M_A_DQ31 M7 AG2 M_B_DQ31 M1 AD5
M_A_DQ32 SA_DQ[31] SA_ODT[2] M_B_DQ32 SB_DQ[31] SB_ODT[2]
AG6 SA_DQ[32] SA_ODT[3] AH2 AM5 SB_DQ[32] SB_ODT[3] AE5
M_A_DQ33 AG5 M_B_DQ33 AM6
M_A_DQ34 SA_DQ[33] M_B_DQ34 SB_DQ[33]
AK6 SA_DQ[34] AR3 SB_DQ[34]
M_A_DQ35 AK5 M_B_DQ35 AP3
M_A_DQ36 SA_DQ[35] M_B_DQ36 SB_DQ[35]
AH5 SA_DQ[36] M_A_DQSN[7:0] 12 AN3 SB_DQ[36] M_B_DQSN[7:0] 13
M_A_DQ37 AH6 C4 M_A_DQSN0 M_B_DQ37 AN2 D7 M_B_DQSN0
M_A_DQ38 SA_DQ[37] SA_DQS#[0] M_A_DQSN1 M_B_DQ38 SB_DQ[37] SB_DQS#[0] M_B_DQSN1
AJ5 SA_DQ[38] SA_DQS#[1] G6 AN1 SB_DQ[38] SB_DQS#[1] F3
M_A_DQ39 AJ6 J3 M_A_DQSN2 M_B_DQ39 AP2 K6 M_B_DQSN2
M_A_DQ40 SA_DQ[39] SA_DQS#[2] M_A_DQSN3 M_B_DQ40 SB_DQ[39] SB_DQS#[2] M_B_DQSN3
AJ8 SA_DQ[40] SA_DQS#[3] M6 AP5 SB_DQ[40] SB_DQS#[3] N3
M_A_DQ41 AK8 AL6 M_A_DQSN4 M_B_DQ41 AN9 AN5 M_B_DQSN4
M_A_DQ42 SA_DQ[41] SA_DQS#[4] M_A_DQSN5 M_B_DQ42 SB_DQ[41] SB_DQS#[4] M_B_DQSN5
AJ9 SA_DQ[42] SA_DQS#[5] AM8 AT5 SB_DQ[42] SB_DQS#[5] AP9
M_A_DQ43 AK9 AR12 M_A_DQSN6 M_B_DQ43 AT6 AK12 M_B_DQSN6
M_A_DQ44 SA_DQ[43] SA_DQS#[6] M_A_DQSN7 M_B_DQ44 SB_DQ[43] SB_DQS#[6] M_B_DQSN7
AH8 SA_DQ[44] SA_DQS#[7] AM15 AP6 SB_DQ[44] SB_DQS#[7] AP15
M_A_DQ45 AH9 M_B_DQ45 AN8
M_A_DQ46 SA_DQ[45] M_B_DQ46 SB_DQ[45]
AL9 SA_DQ[46] AR6 SB_DQ[46]
M_A_DQ47 AL8 M_B_DQ47 AR5
M_A_DQ48 SA_DQ[47] M_B_DQ48 SB_DQ[47]
AP11 SA_DQ[48] M_A_DQSP[7:0] 12 AR9 SB_DQ[48] M_B_DQSP[7:0] 13
M_A_DQ49 AN11 D4 M_A_DQSP0 M_B_DQ49 AJ11 C7 M_B_DQSP0
M_A_DQ50 SA_DQ[49] SA_DQS[0] M_A_DQSP1 M_B_DQ50 SB_DQ[49] SB_DQS[0] M_B_DQSP1
AL12 SA_DQ[50] SA_DQS[1] F6 AT8 SB_DQ[50] SB_DQS[1] G3
M_A_DQ51 AM12 K3 M_A_DQSP2 M_B_DQ51 AT9 J6 M_B_DQSP2
M_A_DQ52 SA_DQ[51] SA_DQS[2] M_A_DQSP3 M_B_DQ52 SB_DQ[51] SB_DQS[2] M_B_DQSP3
AM11 SA_DQ[52] SA_DQS[3] N6 AH11 SB_DQ[52] SB_DQS[3] M3
M_A_DQ53 AL11 AL5 M_A_DQSP4 M_B_DQ53 AR8 AN6 M_B_DQSP4
M_A_DQ54 SA_DQ[53] SA_DQS[4] M_A_DQSP5 M_B_DQ54 SB_DQ[53] SB_DQS[4] M_B_DQSP5
AP12 SA_DQ[54] SA_DQS[5] AM9 AJ12 SB_DQ[54] SB_DQS[5] AP8
M_A_DQ55 AN12 AR11 M_A_DQSP6 M_B_DQ55 AH12 AK11 M_B_DQSP6
M_A_DQ56 SA_DQ[55] SA_DQS[6] M_A_DQSP7 M_B_DQ56 SB_DQ[55] SB_DQS[6] M_B_DQSP7
AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
B M_A_DQ57 AH14 M_B_DQ57 AN14 B
M_A_DQ58 SA_DQ[57] M_B_DQ58 SB_DQ[57]
AL15 SA_DQ[58] AR14 SB_DQ[58]
M_A_DQ59 AK15 M_B_DQ59 AT14
M_A_DQ60 SA_DQ[59] M_B_DQ60 SB_DQ[59]
AL14 SA_DQ[60] M_A_A[15:0] 12 AT12 SB_DQ[60] M_B_A[15:0] 13
M_A_DQ61 AK14 AD10 M_A_A0 M_B_DQ61 AN15 AA8 M_B_A0
M_A_DQ62 SA_DQ[61] SA_MA[0] M_A_A1 M_B_DQ62 SB_DQ[61] SB_MA[0] M_B_A1
AJ15 SA_DQ[62] SA_MA[1] W1 AR15 SB_DQ[62] SB_MA[1] T7
M_A_DQ63 AH15 W2 M_A_A2 M_B_DQ63 AT15 R7 M_B_A2
SA_DQ[63] SA_MA[2] M_A_A3 SB_DQ[63] SB_MA[2] M_B_A3
SA_MA[3] W7 SB_MA[3] T6
V3 M_A_A4 T2 M_B_A4
SA_MA[4] M_A_A5 SB_MA[4] M_B_A5
SA_MA[5] V2 SB_MA[5] T4
W3 M_A_A6 T3 M_B_A6
SA_MA[6] M_A_A7 SB_MA[6] M_B_A7
12 M_A_BS#0 AE10 SA_BS[0] SA_MA[7] W6 13 M_B_BS#0 AA9 SB_BS[0] SB_MA[7] R2
12 M_A_BS#1 AF10 V1 M_A_A8 13 M_B_BS#1 AA7 T5 M_B_A8
SA_BS[1] SA_MA[8] M_A_A9 SB_BS[1] SB_MA[8] M_B_A9
12 M_A_BS#2 V6 SA_BS[2] SA_MA[9] W5 13 M_B_BS#2 R6 SB_BS[2] SB_MA[9] R3
AD8 M_A_A10 AB7 M_B_A10
SA_MA[10] M_A_A11 SB_MA[10] M_B_A11
SA_MA[11] V4 SB_MA[11] R1
W4 M_A_A12 T1 M_B_A12
SA_MA[12] M_A_A13 SB_MA[12] M_B_A13
12 M_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 13 M_B_CAS# AA10 SB_CAS# SB_MA[13] AB10
AD9 V5 M_A_A14 AB8 R5 M_B_A14
12 M_A_RAS# SA_RAS# SA_MA[14] 13 M_B_RAS# SB_RAS# SB_MA[14]
AF9 V7 M_A_A15 AB9 R4 M_B_A15
12 M_A_WE# SA_W E# SA_MA[15] 13 M_B_WE# SB_W E# SB_MA[15]

Sandy Bridge_rPGA_Rev0p61 Sandy Bridge_rPGA_Rev0p61


rpga989-47989-socket rpga989-47989-socket
DGG^9000005 DGG^9000005
IC SOCKET RPGA 989P(P1.0,M/H3.0) IC SOCKET RPGA 989P(P1.0,M/H3.0)

A A

352-(&75
4XDQWD&RPSXWHU,QF
Size Document Number Rev

1%
Custom SNB 2/4 (DDR3 I/F) 3A
1A

Date: Saturday, September 18, 2010 Sheet 3 of 39


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http://laptop-motherboard-schematic.blogspot.com/
5 4 3 2 1

SNB: 55A
Sandy Bridge Processor (POWER)
+VCC_CORE
U15F
Sandy Bridge Processor (GRAPHIC POWER)
22uF_8 x2 Socket TOP cavity U15G
R140 100_4

+1.05V_VTT 22uF_8 x2 Socket BOT cavity +VCC_GFX
SNB: 8.5A 22uF_8 x4 Socket TOP edge
AG35 AT24 AK35

SENSE
LINES
VCC1 VAXG1 VAXG_SENSE VCC_AXG_SENSE 33
AG34 VCC2 VCCIO1 AH13 22uF_8 x4 Socket BOT edge AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE 33
AG33 VCC3 VCCIO2 AH10 470uF_7343 x2 AT21 VAXG3
AG32 AG10 AT20 R142 100_4
C493 C521 C516 VCC4 VCCIO3 C145 C147 C482 VAXG4
AG31 VCC5 VCCIO4 AC10 AT18 VAXG5
D 22U/6.3VS_8 10U/6.3VS_6 22U/6.3VS_8 AG30 Y10 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 AT17 D
VCC6 VCCIO5 +VCC_GFX VAXG6
AG29 VCC7 VCCIO6 U10 SNB: 21.5A AR24 VAXG7
AG28 VCC8 VCCIO7 P10 AR23 VAXG8
AG27 VCC9 VCCIO8 L10 AR21 VAXG9
AG26 VCC10 VCCIO9 J14 AR20 VAXG10 CAD Note: +VDDR_REF_CPU should
AF35 J13 AR18 +VDDR_REF_CPU

VREF
VCC11 VCCIO10 C260 C180 C166 C529 C264 VAXG11 have 10 mil trace width
AF34 VCC12 VCCIO11 J12 AR17 VAXG12
C42 C36 C174 AF33 J11 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 AP24 AL1 R28 *0_8 DDR_VTTREF 12,13,35
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC13 VCCIO12 VAXG13 SM_VREF
AF32 VCC14 VCCIO13 H14 AP23 VAXG14
AF31 VCC15 VCCIO14 H12 AP21 VAXG15
AF30 VCC16 VCCIO15 H11 AP20 VAXG16 1 3
AF29 VCC17 VCCIO16 G14 AP18 VAXG17
AF28 G13 AP17 R31 Q2
VCC18 VCCIO17 C146 C215 C526 C285 C299 VAXG18 100K_4 2N7002
AF27 G12 AN24

2
VCC19 VCCIO18 *22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 VAXG19
AF26 VCC20 VCCIO19 F14 AN23 VAXG20

PEG AND DDR


C509 C172 C263 AD35 F13 AN21 MAIND
VCC21 VCCIO20 VAXG21 MAIND 38
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 AD34 F12 AN20
VCC22 VCCIO21 VAXG22
AD33 F11 AN18

DDR3 -1.5V RAILS


VCC23 VCCIO22 VAXG23
AD32 VCC24 VCCIO23 E14 AN17 VAXG24
AD31 E12 AM24 AF7

GRAPHICS
VCC25 VCCIO24 C532 C200 C61 C284 C530 VAXG25 VDDQ1 +1.5V_CPU
AD30 VCC26 AM23 VAXG26 VDDQ2 AF4 SNB: 5A
AD29 E11 *22U/6.3VS_8 *22U/6.3VS_8 *22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 AM21 AF1
VCC27 VCCIO25 VAXG27 VDDQ3
AD28 VCC28 VCCIO26 D14 AM20 VAXG28 VDDQ4 AC7
C300 C39 C502 AD27 D13 AM18 AC4
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC29 VCCIO27 VAXG29 VDDQ5
AD26 VCC30 VCCIO28 D12 AM17 VAXG30 VDDQ6 AC1
AC35 D11 AL24 Y7 C297 C214 C289 C268
VCC31 VCCIO29 VAXG31 VDDQ7 10U/6.3V_6 10U/6.3V_8 10U/6.3V_6 10U/6.3V_6
AC34 VCC32 VCCIO30 C14 5/14 modify AL23 VAXG32 VDDQ8 Y4
AC33 C13 C491 C66 C282 C301 C238 AL21 Y1
VCC33 VCCIO31 VAXG33 VDDQ9
AC32 VCC34 VCCIO32 C12 22U/6.3VS_8 *22U/6.3VS_8 *22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 AL20 VAXG34 VDDQ10 U7 4/27: layout modify
AC31 VCC35 VCCIO33 C11 AL18 VAXG35 VDDQ11 U4
C C527 C
AC30 VCC36 VCCIO34 B14 AL17 VAXG36 VDDQ12 U1 9/10 SI for H/W.

1
C177 *10U/6.3V_6S C33 AC29 B12 AK24 P7
22U/6.3VS_8 22U/6.3VS_8 VCC37 VCCIO35 VAXG37 VDDQ13 +
AC28 VCC38 VCCIO36 A14 AK23 VAXG38 VDDQ14 P4
AC27 A13 AK21 P1 C190 C305 C576
VCC39 VCCIO37 C167 C506 C236 C528 C239 VAXG39 VDDQ15 10U/6.3V_6 10U/6.3V_6 *330U_2.5V_5.0x5.9_ESR10m
AC26 A12 AK20

2
VCC40 VCCIO38 *22U/6.3VS_8 22U/6.3VS_8 *22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 VAXG40
AA35 VCC41 VCCIO39 A11 AK18 VAXG41
AA34 VCC42 AK17 VAXG42
AA33 VCC43 VCCIO40 J23 AJ24 VAXG43 330uF x1, 10uF_8 x6 Socket BOT edge.
AA32 VCC44 AJ23 VAXG44
C151 C286 C283 AA31 AJ21
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC45 VAXG45
AA30 VCC46 AJ20 VAXG46
AA29 C513 C499 C158 C265 C531 AJ18
VCC47 *22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 VAXG47
AA28 VCC48 AJ17 VAXG48 +VCCSA
AA27 VCC49 AH24 VAXG49 SNB: 6A

SA RAIL
AA26 VCC50 AH23 VAXG50
Y35 VCC51 AH21 VAXG51 VCCSA1 M27
Y34 VCC52 22uF_8 x7 Socket TOP cavity AH20 VAXG52 VCCSA2 M26
CORE SUPPLY

C237 C242 C163 Y33 AH18 L26


22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC53 22uF_8 x5 Socket BOT cavity VAXG53 VCCSA3 C485 C448 C484 C445
Y32
Y31
VCC54
VCC55
22uF_8 x2 Socket TOP cavity (no stuff) DEL AH17 VAXG54 VCCSA4
VCCSA5
J26
J25 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8
Y30 VCC56
22uF_8 x5 Socket BOT cavity (no stuff) VCCSA6 J24
Y29 VCC57 330uF_7343 x2 DIS SG/UMA VCCSA7 H26
Y28 VCC58 VCCSA8 H25 330uF x1, 10uF_8 x1 Socket BOT edge,
Y27 VCC59 Ra Stuff NC 10uF_8 x2 Socket BOT cavity.
Y26

1.8V RAIL
C535 C220 C447 VCC60 +1.05V_VTT
V35 VCC61
*22U/6.3VS_8 *22U/6.3VS_8 22U/6.3VS_8 +1.8V
V34 VCC62 +1.05V_VTT_40
SNB: 1.5A
V33 R86 *0_4/S
VCC63
V32 VCC64 B6 VCCPLL1 VCCSA_SENSE H23 VCCUSA_SENSE_R R82 0_4 VCCUSA_SENSE 36
V31 A6

MISC
B VCC65 VCCPLL2 B
V30 VCC66 A2 VCCPLL3
V29 AJ29 H_CPU_SVIDALRT# C449 C441 C443 + C440 R77 10K_4
SVID

VCC67 VIDALERT# H_CPU_SVIDCLK


V28 VCC68 VIDSCLK AJ30 10U/6.3V_8 1U/6.3V_4 1U/6.3V_4 330U/2V_7343
FC_C22 C22 H_FC_C22
C173 C515 C270 V27 AJ28 H_CPU_SVIDDAT C24
VCC69 VIDSOUT VCCSA_VID1 VCCSA_SEL 36
22U/6.3VS_8 10U/6.3VS_6 22U/6.3VS_8 V26 VCC70 R81 10K_4
U35 VCC71 330uF x1, 10uF_8 x1, 1uF_4 x2
U34 VCC72 Socket BOT edge.
U33 Sandy Bridge_rPGA_Rev0p61
VCC73
U32 VCC74
rpga989-47989-socket 5/11: Add for intel CRB
U31 DGG^9000005 +1.5V_CPU R310 *0_8/S +1.5V
C542 VCC75 IC SOCKET RPGA 989P(P1.0,M/H3.0)
U30 VCC76
C450 C451 *10U/6.3V_6S U29 40mile routing
22U/6.3VS_8 22U/6.3VS_8 VCC77
U28 VCC78
U27 VCC79
U26 VCC80 Layout note: need routing Place PU resistor SVID CLK
R35 +1.5VSUS +1.5V_CPU +1.5VSUS
VCC81 together and ALERT need close to VR
R34 VCC82
22uF_8 x8 Socket TOP cavity R33 between CLK and DATA. R309 *54.9/F_4 +1.05V_VTT C455 0.1U/10V_4
VCC83 R136 100_4
22uF_8 x10 Socket BOT cavity R32 VCC84 +VCC_CORE Q36
SENSE LINES

R31 C452 0.1U/10V_4


22uF_8 x8 Socket TOP edge VCC85 H_CPU_SVIDCLK AON7410
R30 VCC86 VCC_SENSE AJ35 VCC_SENSE 33 VR_SVID_CLK 33
470uF_7343 x4 R29 VCC87 VSS_SENSE AJ34 VSS_SENSE 33 1 R185 C554 0.1U/10V_4
R28 5 2 220_8
VCC88 R139 100_4 C558 0.1U/10V_4
3/26 DB change 10U FP to 0805. R27 VCC89 3
R26 +1.05V_VTT +1.05V_VTT
VCC90 SVID DATA

3
P35 VCC91 3/26 DB add for Intel.
P34 Placement close to CPU.

4
VCC92 MAIND
P33 VCC93 VCCP_SENSE 32
P32 VCC94 VCCIO_SENSE B10 Place PU resistor Place PU resistor 2 MAIN_ONG 2,38
P31 A10 VSSP_SENSE R137 R308
A VCC95 VSSIO_SENSE VSSP_SENSE 32 close to CPU 130/F_4 *130/F_4
close to VR C438 Q16 A
P30 VCC96
P29 *470P/50V_4 2N7002
VCC97 H_CPU_SVIDDAT
P28 Trace Route to Power IC area. VR_SVID_DATA 33
CPU VDDQ

1
VCC98
P27 VCC99
+VCC_CORE 22,34 P26 VCC100

352-(&75
+VCC_GFX 34
+VCCSA 36 Place PU resistor close to CPU SVID ALERT
+1.05V_VTT 2,6,7,8,10,29,32,33
+1.5V_CPU 2
Sandy Bridge_rPGA_Rev0p61
rpga989-47989-socket
+1.05V_VTT R26 75/F_4 4XDQWD&RPSXWHU,QF
+1.5V_CPU 2
DGG^9000005
+1.5VSUS 2,10,12,13,22,35,39
IC SOCKET RPGA 989P(P1.0,M/H3.0) H_CPU_SVIDALRT# R25 43_4 VR_SVID_ALERT# 33 Size Document Number Rev

1%
Custom SNB 3/4 (POWER) 3A
1A

Date: Saturday, September 18, 2010 Sheet 4 of 39


5 4 3 2 1

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http://laptop-motherboard-schematic.blogspot.com/
5 4 3 2 1

AT35
U15H
Sandy Bridge Processor (GND)

AJ22
U15I
Sandy Bridge Processor (RESERVED, CFG)
U15E

VSS1 VSS81
AT32 VSS2 VSS82 AJ19 For CPU debug. RSVD28 L7
AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22 RSVD29 AG7
AT27 AJ13 T34 F19 CFG0 AK28 AE7
VSS4 VSS84 VSS162 VSS235 TP6 CFG[0] RSVD30
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30 TP3 AK29 CFG[1] RSVD31 AK2
AT22 AJ7 T32 E27 CFG2 AL26 W8
VSS6 VSS86 VSS164 VSS237 CFG[2] RSVD32
AT19 VSS7 VSS87 AJ4 T31 VSS165 VSS238 E24 TP9 AL27 CFG[3]
D AT16 AJ3 T30 E21 CFG4 AK26 D
VSS8 VSS88 VSS166 VSS239 CFG5 CFG[4]
AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18 AL29 CFG[5] RSVD33 AT26
AT10 AJ1 T28 E15 CFG6 AL30 AM33
VSS10 VSS90 VSS168 VSS241 CFG7 CFG[6] RSVD34
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13 AM31 CFG[7] RSVD35 AJ27
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10 AM32 CFG[8]
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9 AM30 CFG[9]
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8 AM28 CFG[10]
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7 AM26 CFG[11]
AR19 VSS16 VSS96 AH28 P5 VSS174 VSS247 E6 AN28 CFG[12]
AR16 VSS17 VSS97 AH26 P3 VSS175 VSS248 E5 AN31 CFG[13] RSVD37 T8
AR13 VSS18 VSS98 AH25 P2 VSS176 VSS249 E4 AN26 CFG[14] RSVD38 J16
AR10 VSS19 VSS99 AH22 N35 VSS177 VSS250 E3 AM27 CFG[15] RSVD39 H16
AR7 VSS20 VSS100 AH19 N34 VSS178 VSS251 E2 TP1 AK31 CFG[16] RSVD40 G16
AR4 VSS21 VSS101 AH16 N33 VSS179 VSS252 E1 AN29 CFG[17]
AR2 VSS22 VSS102 AH7 N32 VSS180 VSS253 D35
AP34 VSS23 VSS103 AH4 N31 VSS181 VSS254 D32
AP31 VSS24 VSS104 AG9 N30 VSS182 VSS255 D29
AP28 VSS25 VSS105 AG8 N29 VSS183 VSS256 D26 RSVD41 AR35
AP25 VSS26 VSS106 AG4 N28 VSS184 VSS257 D20 AJ31 RSVD1 RSVD42 AT34
AP22 VSS27 VSS107 AF6 N27 VSS185 VSS258 D17 AH31 RSVD2 RSVD43 AT33
AP19 VSS28 VSS108 AF5 N26 VSS186 VSS259 C34 AJ33 RSVD3 RSVD44 AP35
AP16 VSS29 VSS109 AF3 M34 VSS187 VSS260 C31 AH33 RSVD4 RSVD45 AR34
AP13 VSS30 VSS110 AF2 L33 VSS188 VSS261 C28
AP10 VSS31 VSS111 AE35 L30 VSS189 VSS262 C27
AP7 VSS32 VSS112 AE34 L27 VSS190 VSS263 C25 AJ26 RSVD5

RESERVED
AP4 VSS33 VSS113 AE33 L9 VSS191 VSS264 C23
AP1 VSS34 VSS114 AE32 L8 VSS192 VSS265 C10
AN30 VSS35 VSS115 AE31 L6 VSS193 VSS266 C1 RSVD46 B34
AN27 VSS36 VSS116 AE30 L5 VSS194 VSS267 B22 12 SMDDR_VREF_DQ0_M3 B4 RSVD6 RSVD47 A33
AN25 AE29 L4 B19 D1 A34
C AN22
AN19
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
AE28
AE27
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
13 SMDDR_VREF_DQ1_M3 RSVD7 RSVD48
RSVD49
RSVD50
B35
C35
C

AN16 VSS40 VSS120 AE26 L1 VSS198 VSS271 B13


AN13 AE9 K35 B11 R321 R317 F25
VSS41 VSS121 VSS199 VSS272 *1K_4 *1K_4 RSVD8
AN10 VSS42 VSS122 AD7 K32 VSS200 VSS273 B9 F24 RSVD9
AN7 VSS43 VSS123 AC9 K29 VSS201 VSS274 B8 F23 RSVD10
AN4 VSS44 VSS124 AC8 K26 VSS202 VSS275 B7 D24 RSVD11 RSVD51 AJ32
AM29 VSS45 VSS125 AC6 J34 VSS203 VSS276 B5 G25 RSVD12 RSVD52 AK32
AM25 VSS46 VSS126 AC5 J31 VSS204 VSS277 B3 G24 RSVD13
AM22 VSS47 VSS127 AC3 H33 VSS205 VSS278 B2 E23 RSVD14
AM19 VSS48 VSS128 AC2 H30 VSS206 VSS279 A35 D23 RSVD15
AM16 VSS49 VSS129 AB35 H27 VSS207 VSS280 A32 C30 RSVD16 RSVD53 AH27
AM13 VSS50 VSS130 AB34 H24 VSS208 VSS281 A29 A31 RSVD17
AM10 VSS51 VSS131 AB33 H21 VSS209 VSS282 A26 B30 RSVD18
AM7 VSS52 VSS132 AB32 H18 VSS210 VSS283 A23 B29 RSVD19
AM4 VSS53 VSS133 AB31 H15 VSS211 VSS284 A20 D30 RSVD20 RSVD54 AN35 TP38
AM3 VSS54 VSS134 AB30 H13 VSS212 VSS285 A3 B31 RSVD21 RSVD55 AM35 TP37
AM2 VSS55 VSS135 AB29 H10 VSS213 A30 RSVD22
AM1 VSS56 VSS136 AB28 H9 VSS214 C29 RSVD23 #27636 SNB EDS0.7v1 no function.
AL34 VSS57 VSS137 AB27 H8 VSS215
AL31 VSS58 VSS138 AB26 H7 VSS216
AL28 VSS59 VSS139 Y9 H6 VSS217 J20 RSVD24
AL25 VSS60 VSS140 Y8 H5 VSS218 B18 RSVD25 RSVD56 AT2
AL22 Y6 H4 R320 0_4 A19 AT1
VSS61 VSS141 VSS219 32 H_VTTVID1 RSVD26 RSVD57
AL19 VSS62 VSS142 Y5 H3 VSS220 RSVD58 AR1
AL16 VSS63 VSS143 Y3 H2 VSS221
AL13 VSS64 VSS144 Y2 H1 VSS222 J15 RSVD27 For rPGA socket, RSVD59 pin should be left NC.
AL10 VSS65 VSS145 W 35 G35 VSS223
AL7 VSS66 VSS146 W 34 G32 VSS224
AL4 VSS67 VSS147 W 33 G29 VSS225 KEY B1
B AL2 W 32 G26 B
VSS68 VSS148 VSS226
AK33 VSS69 VSS149 W 31 G23 VSS227
AK30 VSS70 VSS150 W 30 G20 VSS228
AK27 VSS71 VSS151 W 29 G17 VSS229
AK25 VSS72 VSS152 W 28 G11 VSS230
AK22 VSS73 VSS153 W 27 F34 VSS231
AK19 W 26 F31 Sandy Bridge_rPGA_Rev0p61
VSS74 VSS154 VSS232 rpga989-47989-socket
AK16 VSS75 VSS155 U9 F29 VSS233
AK13 U8 DGG^9000005
VSS76 VSS156 IC SOCKET RPGA 989P(P1.0,M/H3.0)
AK10 VSS77 VSS157 U6
AK7 VSS78 VSS158 U5
AK4 VSS79 VSS159 U3
AJ25 VSS80 VSS160 U2

Sandy Bridge_rPGA_Rev0p61 Sandy Bridge_rPGA_Rev0p61


rpga989-47989-socket rpga989-47989-socket
DGG^9000005 DGG^9000005
IC SOCKET RPGA 989P(P1.0,M/H3.0) IC SOCKET RPGA 989P(P1.0,M/H3.0)

CFG[6:5] (PCIE Port Bifurcation Straps)


The CFG signals have a default value of '1' if not terminated on the board.
Processor Strapping 11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
1 0 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
CFG2 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
A A
(PEG Static Lane Reversal) Normal Operation Lane Reversed CFG2 R153 *1K_4

CFG4 CFG4 R154 *1K_4

(DP Presence Strap) Disable; No physical DP attached to eDP Enable; An ext DP device is connected to eDP CFG7 R149 *1K_4
352-(&75
CFG7 PEG train immediately following PEG wait for BIOS training CFG5 R152 1K_4 4XDQWD&RPSXWHU,QF
(PEG Defer Training) xxRESETB de assertion CFG6 R147 1K_4
Size Document Number Rev

1%
Custom SNB 4/4 (GND) 3A
1A

Date: Saturday, September 18, 2010 Sheet 5 of 39


5 4 3 2 1

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http://laptop-motherboard-schematic.blogspot.com/
5 4 3 2 1

2 DMI_RXN0
Cougar Point (DMI,FDI,PM)

BC24
BE20
U24C

DMI0RXN FDI_RXN0 BJ14


AY14
FDI_TXN0 2
20 LVDS_BLON
20 DISP_ON
Cougar Point (LVDS,DDI)
J47
M45
U24D
L_BKLTEN
L_VDD_EN
SDVO_TVCLKINN
SDVO_TVCLKINP
AP43
AP45

2 DMI_RXN1 DMI1RXN FDI_RXN1 FDI_TXN1 2
2 DMI_RXN2 BG18 DMI2RXN FDI_RXN2 BE14 FDI_TXN2 2 20 DPST_PWM P45 L_BKLTCTL SDVO_STALLN AM42
2 DMI_RXN3 BG20 DMI3RXN FDI_RXN3 BH13 FDI_TXN3 2 SDVO_STALLP AM40
FDI_RXN4 BC12 FDI_TXN4 2 20 EDIDCLK T40 L_DDC_CLK
2 DMI_RXP0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_TXN5 2 20 EDIDDATA K47 L_DDC_DATA SDVO_INTN AP39
2 DMI_RXP1 BC20 DMI1RXP FDI_RXN6 BG10 FDI_TXN6 2 SDVO_INTP AP40
D BJ18 BG9 R276 2.2K_4 L_CTRL_CLK T45 D
2 DMI_RXP2 DMI2RXP FDI_RXN7 FDI_TXN7 2 L_CTRL_CLK
BJ20 R275 2.2K_4 L_CTRL_DATA P39
2 DMI_RXP3 DMI3RXP +3V L_CTRL_DATA
FDI_RXP0 BG14 FDI_TXP0 2
2 DMI_TXN0 AW 24 BB14 R273 2.37K/F_4 LVDS_IBG AF37 P38 SDVO_CLK 21
DMI0TXN FDI_RXP1 FDI_TXP1 2 LVD_IBG SDVO_CTRLCLK
AW 20 BF14 LVDS_VBG AF36 M39
2 DMI_TXN1 DMI1TXN FDI_RXP2 FDI_TXP2 2 LVD_VBG SDVO_CTRLDATA SDVO_DATA 21
2 DMI_TXN2 BB18 BG13 TP30
DMI2TXN FDI_RXP3 FDI_TXP3 2
2 DMI_TXN3 AV18 DMI3TXN FDI_RXP4 BE12 FDI_TXP4 2 AE48 LVD_VREFH

INT. HDMI
FDI_RXP5 BG12 FDI_TXP5 2 AE47 LVD_VREFL DDPB_AUXN AT49

DMI
FDI
2 DMI_TXP0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_TXP6 2 DDPB_AUXP AT47
2 DMI_TXP1 AY20 BH9 AT40 DPB_HPD_Q
DMI1TXP FDI_RXP7 FDI_TXP7 2 DDPB_HPD
2 DMI_TXP2 AY18 DMI2TXP 20 TXLCLKOUT- AK39 LVDSA_CLK#
AU18 AK40 AV42 DPB_LANE0_N

LVDS
2 DMI_TXP3 DMI3TXP 20 TXLCLKOUT+ LVDSA_CLK DDPB_0N
AW 16 AV40 DPB_LANE0_P
FDI_INT FDI_INT 2 DDPB_0P
20 TXLOUT0- AN48 AV45 DPB_LANE1_N
LVDSA_DATA#0 DDPB_1N DPB_LANE1_P
BJ24 DMI_ZCOMP FDI_FSYNC0 AV12 FDI_FSYNC0 2 20 TXLOUT1- AM47 LVDSA_DATA#1 DDPB_1P AV46
DPB_LANE2_N

Digital Display Interface


20 TXLOUT2- AK47 LVDSA_DATA#2 DDPB_2N AU48
+1.05V_VTT R500 49.9/F_4 DMI_COMP BG25 BC10 AJ48 AU47 DPB_LANE2_P
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 2 LVDSA_DATA#3 DDPB_2P
AV47 DPB_LANE3_N
R498 750/F_4 DMI_RBIAS DDPB_3N DPB_LANE3_P
BH21 DMI2RBIAS FDI_LSYNC0 AV14 FDI_LSYNC0 2 20 TXLOUT0+ AN47 LVDSA_DATA0 DDPB_3P AV49
20 TXLOUT1+ AM49 LVDSA_DATA1
FDI_LSYNC1 BB10 FDI_LSYNC1 2 20 TXLOUT2+ AK49 LVDSA_DATA2
TP54 AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
TP53 DDPC_CTRLDATA P42

SUS_PWR_ACK_R R489 0_4 A18 DSWVREN 20 TXUCLKOUT- AF40


DSW VRMEN LVDSB_CLK#
20 TXUCLKOUT+ AF39 AP47

System Power Management


LVDSB_CLK DDPC_AUXN
9/10 SI for H/W. DDPC_AUXP AP49
SUSACK#_R C12 E22 R501 0_4 RSMRST# 20 TXUOUT0- AH45 AT38
SUSACK# DPW ROK LVDSB_DATA#0 DDPC_HPD
20 TXUOUT1- AH47 LVDSB_DATA#1
20 TXUOUT2- AF49 LVDSB_DATA#2 DDPC_0N AY47
C XDP_DBRST# K3 B9 PCIE_WAKE# AF45 AY49 C
2 XDP_DBRST# SYS_RESET# W AKE# PCIE_WAKE# 27,30 20 TXUOUT0+ LVDSB_DATA#3 DDPC_0P
20 TXUOUT1+ DDPC_1N AY43
(+3V) 20 TXUOUT2+ AH43 LVDSB_DATA0 DDPC_1P AY45
SYS_PWROK R433 0_4 SYS_PWROK_R P12 N3 CLKRUN# CLKRUN# 29 PD Res place close to PCH AH49 BA47
SYS_PW ROK CLKRUN# / GPIO32 LVDSB_DATA1 DDPC_2N
AF47 LVDSB_DATA2 DDPC_2P BA48
9/10 SI for H/W. (+3VS5) PCH to Res routeing 50 ohm Impedance. AF43 LVDSB_DATA3 DDPC_3N BB47
R423 0_4 EC_PWROK_R L22 G8 BB49
17,29 EC_PWROK PW ROK SUS_STAT# / GPIO61 TP21 Res to connector filter routeing 37.5ohm Impedance. DDPC_3P
(+3VS5) 22 CRT_B
EC_PWROK_R R233 0_4 APWROK_R L10 N14 PCH_SUSCLK_L R249 0_4 R282 150/F_4 N48 M43
APW ROK SUSCLK / GPIO62 PCH_SUSCLK 29 CRT_BLUE DDPD_CTRLCLK
22 CRT_G P49 CRT_GREEN DDPD_CTRLDATA M36
(+3VS5) TP26 R284 150/F_4 T49
PM_DRAM_PWRGD CRT_RED
2 PM_DRAM_PWRGD B13 DRAMPW ROK SLP_S5# / GPIO63 D10 SLP_S5 29 22 CRT_R
R283 150/F_4 AT45
DDPD_AUXN
T39 AT43

CRT
22 DDCCLK CRT_DDC_CLK DDPD_AUXP
29 RSMRST# RSMRST# C21 H4 R211 0_4 SUSC# 29 22 DDCDATA M40 BH41
RSMRST# SLP_S4# CRT_DDC_DATA DDPD_HPD
(+3VS5) DDPD_0N BB43
29 SUS_PWR_ACK R477 0_4 SUS_PWR_ACK_R K16 F4 R467 0_4 SUSB# 29 22 HSYNC_COM R296 33_4 PCH_HSYNC_R M47 BB45
SUSW ARN#/SUSPW RDNACK/GPIO30 SLP_S3# R297 33_4 PCH_VSYNC_R M49 CRT_HSYNC DDPD_0P
22 VSYNC_COM CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
R495 0_4 DNBSWON#_R E20 G10 5/11: add TP9048 BF42
29 DNBSWON# PW RBTN# SLP_A# TP22 DDPD_2N
R279 1K/F_4 DAC_IREF T43 BE42
DAC_IREF DDPD_2P
(DSW) T42 CRT_IRTN DDPD_3N BJ42
R494 0_4 AC_PRESENT_R H20 G16 5/7: DEL R8304 , Add TP9041 BG42
29 AC_PRESENT ACPRESENT / GPIO31 SLP_SUS# TP55 DDPD_3P
(+3VS5) CougarPoint_Rev_0p7
PM_BATLOW# E10 AP14 fcbga989-intel-cougarpoint
BATLOW # / GPIO72 PMSYNCH PM_SYNC 2
AJ0QMZQ0T00
(+3VS5) IC CTRL(989P)COUGARPOINT QMVY TOP B/S
B SYS_PWROK_R PM_RI# A10 K14 SLP_LAN# B
RI# SLP_LAN# / GPIO29
+1.05V_VTT 2,4,7,8,10,29,32,33
C698
+3V_RTC 7,10
*0.1U/10V_4 CougarPoint_Rev_0p7
+3V_DSW
fcbga989-intel-cougarpoint
+3VPCU 7,20,28,29,31,37
AJ0QMZQ0T00
+3VS5 2,7,8,9,10,22,26,31,32,38,39
9/3 SI for H/W. IC CTRL(989P)COUGARPOINT QMVY TOP B/S
+3V 2,7,8,9,10,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,38,39
+5V 7,10,17,21,22,23,25,28,30,38
Reserve for R13 power on sequence

PCH Pull-high/low(CLG) INT HDMI disable (DIS only remove) System PWR_OK(CLG) DPWROK FOR DSW
9/10 SI for EE
+3VS5 +3VS5
DPB_LANE0_N
PM_RI# DPB_LANE0_P IN_D2# 21 SYS_PWROK R420
R485 10K_4 0_4 IMVP_PWRGD C596 *0.1U/10V_4
IN_D2 21
DPB_LANE1_N
IN_D1# 21
PM_BATLOW# R473 *8.2K_4 DPB_LANE1_P
IN_D1 21

5
DPB_LANE2_N
IN_D0# 21
PCIE_WAKE# R476 10K_4 DPB_LANE2_P 2
IN_D0 21 IMVP_PWRGD 33
DPB_LANE3_N SYS_PWROK 4 Remove DSW power rail
IN_CLK# 21
SLP_LAN# R260 *10K_4 DPB_LANE3_P 1 EC_PWROK
IN_CLK 21
SUS_PWR_ACK R474 10K_4 U21

3
*TC7SH08FU
AC_PRESENT_R R496 10K_4 R427
INT HDMI Detect Function *100K_4

A +3V R537 0_4 A

CLKRUN# R439 8.2K_4 R430 *0_4

XDP_DBRST# R443 10K_4 DPB_HPD_Q 1 3 HDMI_HPD_CON 21


R459 *1K_4
Q40
+3V_RTC R493 330K_4 DSWVREN R491 *330K_4
352-(&75
4XDQWD&RPSXWHU,QF
2

RSMRST# R503 10K_4 R535 *2N7002K R546


*100K_4 *100K_4 On Die DSW VR Enable
SYS_PWROK R434 *10K_4 +5V
High = Enable (Default) Size Document Number Rev

1%
9/3 SI for H/W. Low = Disable Custom PCH 1/6 (DMI/FDI/VIDEO) 3A
1A

Date: Saturday, September 18, 2010 Sheet 6 of 39


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TP58

TP57
RTC_X1
Cougar Point (HDA,JTAG,SATA)
A20
U24A

RTCX1 FW H0 / LAD0 C38


A38
LAD0 29,30
+1.05V_VTT 2,4,6,8,10,29,32,33
+1.8V 4,10,32,39
+3V_RTC 6,10
RTC Clock 32.768KHz 

LPC
FW H1 / LAD1 LAD1 29,30 +3V_DSW
RTC_X2 C20 B37 LAD2 29,30
RTCX2 FW H2 / LAD2 +3VPCU 20,28,29,31,37
C37 LAD3 29,30 C608 18P/50V_4 RTC_X1
RTC_RST# FW H3 / LAD3 +3V 2,6,8,9,10,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,38,39
D20 RTCRST# +V3.3A_1.5A_HDA_IO 10

2
1
TP27 FW H4 / LFRAME# D36 LFRAME# 29,30

RTC
SRTC_RST# G22 SRTCRST# PCH_DRQ#0 Y4 R499
LDRQ0# E36 TP32
+3V_RTC R258 1M_4 SM_INTRUDER# K22 K36 PCH_DRQ#1 TP31 32.768KHZ 10M_4
D INTRUDER# LDRQ1# / GPIO23 D
(+3V)

3
4
PCH_INVRMEN C17 V5 SERIRQ R234 8.2K_4 C609 18P/50V_4 RTC_X2
INTVRMEN SERIRQ +3V
TP56 SERIRQ 29

SATA0RXN AM3 SATA_RXN0 23


ACZ_BCLK N34 AM1
HDA_BCLK SATA0RXP SATA_RXP0 23
AP7
SATA0TXN SATA_TXN0 23 HDD0 (SATA3 6.0Gb/s)

SATA 6G
ACZ_SYNC L34 AP5
C408 RF HDA_SYNC SATA0TXP SATA_TXP0 23
*10P/50V_4 ACZ_SPKR T10 AM10
25 ACZ_SPKR
ACZ_RST#
SPKR SATA1RXN
SATA1RXP AM8 RTC Circuitry(RTC) 30mils
K34 HDA_RST# SATA1TXN AP11
AP10 +3V_RTC
SATA1TXP R567

IHDA
25 ACZ_SDIN0 E34 AD7 RTC_RST#
HDA_SDIN0 SATA2RXN
SATA2RXP AD5

1
TP29 G34 AH5 20K/F_4
HDA_SDIN1 SATA2TXN
SATA2TXP AH4 9/10 SI for H/W. FOR DSW
C34 DG recommended that AC coupling capacitors should be C683 J1
HDA_SDIN2 1U/6.3V_4 *SOLDERJUMPER-2
AB8 close to the connector (<100 mils) for optimal signal quality.

2
SATA3RXN R568
A34 HDA_SDIN3 SATA3RXP AB10

SATA
AF3 +3VPCU R558 0_6 +3V_RTC_2 20K/F_4
SATA3TXN SRTC_RST#
SATA3TXP AF1
ACZ_SDOUT A36 +3V_RTC_0 R573 1K_4 +3V_RTC_1
HDA_SDO

1
SATA4RXN Y7 SATA_RXN4 23

1
(+3V) SATA4RXP Y5 SATA_RXP4 23
GPIO33 C36 AD3 CN24 D14 C687 C692 J2
HDA_DOCK_EN# / GPIO33 SATA4TXN
AD1
SATA_TXN4 23 ODD (SATA1 1.5Gb/s) BAT_CONN BAT54C 1U/6.3V_4 1U/6.3V_4 *SOLDERJUMPER-2
(+3VS5) SATA_TXP4 23

2
SATA4TXP
TP28 N32 DFWF02MS032

2
HDA_DOCK_RST# / GPIO13
SATA5RXN Y3
50273-0027N-001-2P-L 8/25 SI for M/E.
C C
SATA5RXP Y1 RTC Power trace width 20mils. 4/20 DB add.
SATA5TXN AB3
TP49 PCH_JTAG_TCK_R J3 AB1 RTC_RST# R253 *0_6 SRTC_RST#
JTAG_TCK SATA5TXP
TP15 PCH_JTAG_TMS H7 Y11 3/26 DB modify for placement.
JTAG_TMS SATAICOMPO
JTAG

PCH_JTAG_TDI_R K5 Y10 SATA_COMP R244 37.4/F_4


TP14 JTAG_TDI SATAICOMPI +1.05V_VTT
PCH JTAG Debug(CLG)
TP50 PCH_JTAG_TDO_R H1 JTAG_TDO
BIT_CLK_AUDIO HDA Bus(CLG)
SATA3RCOMPO AB12
+3VS5

SATA3COMPI AB13 SATA3_COMP R246 49.9/F_4 EMI


C411 R280 33_4 ACZ_BCLK
25 BIT_CLK_AUDIO
PCH_SPI_CLK T3 AH1 SATA3_RBIAS R465 750/F_4 *33P/50V_4
SPI_CLK SATA3RBIAS
PCH_SPI_CS0# Y14 SPI_CS0# R277 33_4 ACZ_RST# R225 R202 R463
SATA_LED# 28 25 ACZ_RST#_AUDIO
+3VPCU R454 *10K_4 PCH_SPI_CS1# T1 210/F_4 210/F_4 210/F_4
SPI_CS1#
SPI

P3 R438 10K_4 R514 33_4 ACZ_SDOUT


SATALED# +3V 25 ACZ_SDOUT_AUDIO
PCH_JTAG_TMS
PCH_SPI_SI (+3V) DGT_STOP# PCH_JTAG_TDI_R
V4 SPI_MOSI SATA0GP / GPIO21 V14
R529 10K_4 PCH_JTAG_TDO_R
(+3V) +5V

2
PCH_SPI_SO U3 P1 BBS_BIT0 PCH_JTAG_TCK_R
SPI_MISO SATA1GP / GPIO19
25 ACZ_SYNC_AUDIO R531 33_4 1 3 ACZ_SYNC
CougarPoint_Rev_0p7 DGT_STOP# R217 *10K_4 R224 R219 R462 R446
+3V
fcbga989-intel-cougarpoint Q39 100/F_4 100/F_4 100/F_4 51_4
AJ0QMZQ0T00 2N7002K

B
PCH Strap Table IC CTRL(989P)COUGARPOINT QMVY TOP B/S
B

Pin Name Strap description Sampled Configuration Circuit


Different from 0 = Default (weak pull-down 20K) ACZ_SPKR
SPKR No reboot mode setting PWROK 1 = Setting to No-Reboot mode R435 *1K_4
Calpella
R522 *1K_4
+3V
TP47 TP52 PCH SPI ROM(CLG)
0 = "top-block swap" mode PCI_GNT3# 8
GNT3# / GPIO55 Top-Block Swap Override PWROK 1 = Default (weak pull-up 20K) +3V R521 10K_4 TP48 TP51
+3V
U22
INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up PCH_INVRMEN R497 330K_4 +3V_RTC PCH_SPI_CS0# 1 8
PCH_SPI_CLK R479 0_4 PCH_SPI1_CLK_R CE# VDD
6 SCK
Flash Descriptor Security 0 = Override PCH_SPI_SI R216 0_4 PCH_SPI1_SI_R 5
GPIO33 R509 1K_4 PCH_SPI_SO R437 0_4 PCH_SPI1_SO_R SI R480 3.3K_4
HDA_DOCK_EN#/GPIO33 Only for Interposer PWROK 1 = Default (weak pull-up 20K) GPIO33_E 29 2 SO HOLD# 7

[Need external pull-down for LPC BIOS] RF 3 W P# VSS 4


GNT1# / GPIO51 Boot BIOS Selection 1 [bit-1] PWROK GNT1# GNT0# Boot Location Default weak pull-up on GNT0/1# C598 C597 C599
1 1 SPI BBS_BIT0 *22P/50V_4 *22P/50V_4 W25Q32BVSSIG 0.1U/10V_4
Different from 0 0 LPC R455 *1K_4
GPIO19 Boot BIOS Selection 0 [bit-0] PWROK R523 *1K_4 BBS_BIT1 8
Calpella
Should not be pull-down +3V R432 3.3K_4
GNT2# / GPIO53 ESI strap (Server only) PWROK (weak pull-up 20K) USE GPIO PIN
Intel Anti-Theft HDD protection Vender Size P/N
NV_ALE Only for Interposer PWROK 0 = Disable (Internal pull-down 20kohm) +1.8V R468 *1K_4
NV_ALE 8
EON 4MB AKE39FN0Q00 (EN25F32-100HIP)
R470 2.2K_4 R469 4.7K_4
NV_CLE DMI Termination voltage PWROK weak pull-down 20kohm +1.8V NV_CLE 8 N.A at CPT EDS 0.7
H_SNB_IVB# 2 Winbond 4MB AKE391P0N00 (W25Q32BVSSIG)
A 0 = Support by 1.8V (weak pull-down) R278 1K_4 ACZ_SYNC A
HDA_SYNC On-Die PLL VR Voltage Select RSMRST 1 = Support by 1.5V
+3VS5 Socket DG008000031
0 = Override ACZ_SDOUT
HDA_SDO Flash Descriptor Security PWROK 1 = Default (weak pull-up 20K) R510 *1K_4 +V3.3A_1.5A_HDA_IO

GPIO8 Integrated Clock Chip Enable RSMRST# Should be pull-down (weak pull-up 20K) R483 *1K_4
ICC_EN# 9 352-(&75
Different from 0 = Disable
R447 *1K_4
4XDQWD&RPSXWHU,QF
GPIO28 Calpella On-die PLL Voltage Regulator RSMRST# 1 = Enable (Default) PLL_ODVR_EN 9

0 = Default (weak pull-down 20K) Size Document Number Rev

1%
SPI_MOSI iTPM function Disable APWROK 1 = Enable PCH_SPI_SI R198 1K_4 Custom PCH 2/6 (SATA/HDA/SPI) 3A
1A
+3V
Date: Saturday, September 18, 2010 Sheet 7 of 39
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PCI/USBOC# Pull-up(CLG)
+3V
Cougar Point-M (PCI,USB,NVRAM)

BG26
U24E
NV_CE#0
NV_CE#1
AY7
AV7
AU3
30
30
PCIE_RXN1
PCIE_RXP1
Cougar Point-M (PCI-E,SMBUS,CLK)

BG34
BJ34
U24B

PERN1 (+3VS5)
E12 SMBALERT#

PCI_PIRQA# R294 8.2K_4 TP1 NV_CE#2 C399 0.1U/10V_4 PCIE_TXN1_C PERP1 SMBALERT# / GPIO11
PCI_PIRQB# R286 8.2K_4
BJ26
TP2 NV_CE#3
BG4 WLAN 30 PCIE_TXN1
C396 0.1U/10V_4 PCIE_TXP1_C
AV32
PETN1 SMB_PCH_CLK
BH25 30 PCIE_TXP1 AU32 H14
PCI_PIRQC# R287 8.2K_4 TP3 PETP1 SMBCLK
BJ16 AT10
PCI_PIRQD# R295 8.2K_4 TP4 NV_DQS0 SMB_PCH_DAT
BG16 BC8 27 PCIE_RXN2_LAN BE34 C9
TP5 NV_DQS1 PERN2 SMBDATA
AH38 27 PCIE_RXP2_LAN BF34
TP6 C398 0.1U/10V_4 PCIE_TXN2_LAN_C PERP2
AH37 AU2 LAN 27 PCIE_TXN2_LAN BB32

SMBUS
+3V TP7 NV_DQ0 / NV_IO0 C397 0.1U/10V_4 PCIE_TXP2_LAN_C PETN2
AK43
TP8 NV_DQ1 / NV_IO1
AT4 27 PCIE_TXP2_LAN AY32
PETP2 (+3VS5)
D RP8 AK45 AT3 A12 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH 2 D
DGPU_HOLD_RST# TP9 NV_DQ2 / NV_IO2 SML0ALERT# / GPIO60
10 1 C18 AT1 24 PCIE_RXN3_CARD BG36
MPC_PWR_CTRL# INTH# TP10 NV_DQ3 / NV_IO3 PERN3 SMB_ME0_CLK
9 2
BT_COMBO_EN#
N30
TP11 NV_DQ4 / NV_IO4
AY3 Cardreader 24 PCIE_RXP3_CARD
C405 0.1U/10V_4 PCIE_TXN3_CARD_C
BJ36
PERP3 SML0CLK
C8
8 3 H3
TP12 NV_DQ5 / NV_IO5
AT5 24 PCIE_TXN3_CARD AV34
PETN3
EDID_SELECT# 7 4 DGPU_SELECT# AH12 AV3 24 PCIE_TXP3_CARD C404 0.1U/10V_4 PCIE_TXP3_CARD_C AU34 G12 SMB_ME0_DAT
LCD_BK TP13 NV_DQ6 / NV_IO6 PETP3 SML0DATA
6 5 AM4 AV1

NVRAM
TP14 NV_DQ7 / NV_IO7
AM5 BB1 BF36
10K_10P8R_6 TP15 NV_DQ8 / NV_IO8 PERN4
Y13
TP16 NV_DQ9 / NV_IO9
BA3 BE36
PERP4 (+3VS5)
K24 BB5 AY34 C13 SML1ALERT#_R TP18
TP17 NV_DQ10 / NV_IO10 PETN4 SML1ALERT# / PCHHOT# / GPIO74
L24 BB3 BB34 (+3VS5)
+3VS5 TP18 NV_DQ11 / NV_IO11 PETP4 SMB_ME1_CLK
AB46 BB7 E14
RP6 TP19 NV_DQ12 / NV_IO12 SML1CLK / GPIO58
AB45 BE8 BG37 (+3VS5)
USB_OC6# TP20 NV_DQ13 / NV_IO13 PERN5 SMB_ME1_DAT
10 1 BD4 BH37 M16

RSVD

PCI-E*
USB_OC4# USB_OC0# NV_DQ14 / NV_IO14 PERP5 SML1DATA / GPIO75
9 2 BF6 AY36
USB_OC1# USB_OC7# NV_DQ15 / NV_IO15 PETN5
8 3 BB36
USB_OC2# USB_OC5# NV_ALE PETP5
7 4 B21 TP21 NV_ALE AV5 NV_ALE 7
USB_OC3# 6 5 M20 AY1 NV_CLE BJ38
TP22 NV_CLE NV_CLE 7 PERN6
AY16 TP23 BG38 PERP6
10K_10P8R_6 CL_CLK_R

Controller
BG46 TP24 NV_RCOMP AV10 AU36 PETN6 CL_CLK1 M7 TP20
+3V AV36 PETP6
NV_RB# AT8

Link
C646 *0.1U/10V_4 BG40 T11 CL_DAT_R TP16
DGPU_PWROK 9,17,29,35,39 PERN7 CL_DATA1

1
MPC Switch Control BE28 TP25 NV_RE#_WRB0 AY5 BJ40 PERP7
BC30 BA2 U25 AY40
TP26 NV_RE#_WRB1 PETN7 CL_RST#_R
Low = MPC ON BE32 TP27 BB40 PETP7 CL_RST1# P10 TP24
MPC_PWR_CTRL# High = MPC OFF (Default) BJ32 AT12 PCH_CLK_27M_1 2 4
TP28 NV_WE#_CK0 PCH_CLK_27M 15
BC28 TP29 NV_WE#_CK1 BF3 BE38 PERN8
BE30 9/3 SI for H/W. *74LVC1G126 BC38
MPC_PWR_CTRL# R519 *1K_4 TP30 PERP8
BF32 TP31 AW38 PETN8
BG32 TP32 USBP0N C24 USBP0- 26 AY38 PETP8 (+3VS5)
AV26 A24 Left_USB M10 CLK_PEGA_REQ#
TP33 USBP0P USBP0+ 26 PEG_A_CLKRQ# / GPIO47
BB26 TP34 USBP1N C25 USBP1- 26
AU28 B25 Left_USB 2 CLK_PCH_SRC0N Y40
C TP35 USBP1P USBP1+ 26 CLKOUT_PCIE0N C
9,14 DGPU_HOLD_RST# DGPU_HOLD_RST# AY30 C26 CLK_PCH_SRC0P Y39 AB37 CLK_PCH_PEGAN
TP36 USBP2N CLKOUT_PCIE0P CLKOUT_PEG_A_N CLK_PCH_PEGAP
AU26 TP37 USBP2P A26 CLKOUT_PEG_A_P AB38
9/3 SI for H/W. AY26 K28 CLK_PCIE_REQ0# J2
TP38 USBP3N PCIECLKRQ0# / GPIO73
AV28 TP39 USBP3P H28
AW30 TP40 USBP4N E28 USBP4- 20 (+3VS5) CLKOUT_DMI_N AV22 CLK_CPU_BCLKN 2
D28 Webcam CLK_PCH_SRC2N AB49 AU22 CLK_CPU_BCLKP 2
USBP4P USBP4+ 20 CLKOUT_PCIE1N CLKOUT_DMI_P
C28 CLK_PCH_SRC2P AB47
USBP5N CLKOUT_PCIE1P
USBP5P A28
C29
24 CLK_PCIE_CARDN
CLK_PCIE_REQ1# M1
CLOCKS AM12
USBP6N 24 CLK_PCIE_CARDP PCIECLKRQ1# / GPIO18 CLKOUT_DP_N CLK_DPLL_SSCLKN 2
B29 AM13 CLK_DPLL_SSCLKP 2
PCI_PIRQA# USBP6P CLKOUT_DP_P
K40
PIRQA# USBP7N
N28 (+3V)
PCI_PIRQB# K38 M28 RP7 1 2CLK_PCH_CARD2N AA48
PCI_PIRQC# PIRQB# USBP7P 0_4P2R_4 3 CLKOUT_PCIE2N
H38 L30 4CLK_PCH_CARD2P AA47 BF18 CLK_BUF_PCIE_3GPLL#
PCI

PIRQC# USBP8N USBP8- 26 CLKOUT_PCIE2P CLKIN_DMI_N


PCI_PIRQD# G38 K30 Right_USB BE18 CLK_BUF_PCIE_3GPLL
PIRQD# USBP8P USBP8+ 26 CLKIN_DMI_P
G30 24 CLK_PCIE_REQ2# CLK_PCIE_REQ2# V10
BT_COMBO_EN# USBP9N PCIECLKRQ2# / GPIO20
30 BT_COMBO_EN# C46 (+3V) E30
DGPU_SELECT# REQ1# / GPIO50 USBP9P CLK_BUF_BCLK_N
C44 (+3V) C30 (+3V) BJ30
USB

REQ2# / GPIO52 USBP10N USBP10- 30 CLKIN_GND1_N


EDID_SELECT# E40 A30 WLAN Y37 BG30 CLK_BUF_BCLK_P
REQ3# / GPIO54 (+3V) USBP10P USBP10+ 30 CLKOUT_PCIE3N CLKIN_GND1_P
L32 Y36
BBS_BIT1 USBP11N CLKOUT_PCIE3P
D47 K32
7 BBS_BIT1
PWM_SELECT# GNT1# / GPIO51 (+3V) USBP11P CLK_PCIE_REQ3# CLK_BUF_DREFCLK#
E42 G32 A8 G24
TP33
PCI_GNT3# GNT2# / GPIO53 (+3V) USBP12N PCIECLKRQ3# / GPIO25 CLKIN_DOT_96N CLK_BUF_DREFCLK
F46 E32 E24
7 PCI_GNT3# GNT3# / GPIO55 (+3V) USBP12P CLKIN_DOT_96P
USBP13N
C32 USBP2- 26 (+3VS5)
MPC_PWR_CTRL# USBP13P
A32 USBP2+ 26 Blue tooth Y43
CLKOUT_PCIE4N CLK_BUF_DREFSSCLK#
G42 (+3V) Y45 AK7
LCD_BK PIRQE# / GPIO2 CLKOUT_PCIE4P CLKIN_SATA_N CLK_BUF_DREFSSCLK
20 LCD_BK G40 (+3V) AK5
BOARD_ID4 PIRQF# / GPIO3 USB_BIAS CLK_PCIE_REQ4# CLKIN_SATA_P
9 BOARD_ID4 C42 (+3V) C33 L12
INTH# PIRQG# / GPIO4 USBRBIAS# PCIECLKRQ4# / GPIO26
9/3 SI for H/W.
D44
PIRQH# / GPIO5 (+3V) R508 (+3VS5) REFCLK14IN
K45 CLK_PCH_14M change 25M to small size
22.6/F_4
TP19 PCI_PME# K10
PME#
USBRBIAS
B33 V45
V46
CLKOUT_PCIE5N
CLKOUT_PCIE5P 9/8 SI for TXC TP59
RF
H45 CLK_PCI_FB CLK_PCH_14M
PCI_PLTRST# USB_OC0# CLKIN_PCILOOPBACK C621 33P/50V_4
B C6 A14 9 BOARD_ID0 L14 B
PLTRST# (+3VS5) OC0# / GPIO59
K20 USB_OC1# CLK_33M_DEBUG PCIECLKRQ5# / GPIO44 PCH_CLK_27M_1
(+3VS5) OC1# / GPIO40
B17 USB_OC2# (+3VS5)
CLK_PCI_TPM_R H49
(+3VS5) OC2# / GPIO41
C16 USB_OC3# CLK_33M_KBC AB42 R525 Y5
TP61 CLKOUT_PCI0 (+3VS5) OC3# / GPIO42 CLKOUT_PEG_B_N
TP35 CLK_PCI_CARD_R H43 L16 USB_OC4# AB40 V47 XTAL25_IN 1M_4 25MHZ C410 C628
J48
CLKOUT_PCI1 (+3VS5) OC4# / GPIO43
A16 USB_OC5# CLKOUT_PEG_B_P XTAL25_IN
V49 XTAL25_OUT *22P/50V_4 *22P/50V_4
R293 22_4 K42
CLKOUT_PCI2 (+3VS5) OC5# / GPIO9
D14 USB_OC6# C415 C414 CLK_PEGB_REQ# E6
XTAL25_OUT
30 CLK_33M_DEBUG CLKOUT_PCI3 (+3VS5) OC6# / GPIO10 TP17 PEG_B_CLKRQ# / GPIO56
29 CLK_33M_KBC R292 22_4 H40 C14 USB_OC7# *22P/50V_4 *22P/50V_4 C622 27P/50V_4
CLKOUT_PCI4 (+3VS5) OC7# / GPIO14
(+3VS5) TP60
CLK_PCI_FB R281 22_4 9 BOARD_ID1 V40
CougarPoint_Rev_0p7 CLKOUT_PCIE6N XCLK_RCOMP R520 90.9/F_4
V42 Y47 +1.05V_VTT
CLK_PCI_FB_R fcbga989-intel-cougarpoint CLKOUT_PCIE6P XCLK_RCOMP
9 BOARD_ID2
CLK_PCI_LPC_R AJ0QMZQ0T00 CLK_FLEX0
CLK_PCI_EC_R IC CTRL(989P)COUGARPOINT QMVY TOP B/S EMI T13
PCIECLKRQ6# / GPIO45
(+3VS5) (+3V)
TP34
V38 K43
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
V37

FLEX CLOCKS
CLKOUT_PCIE7P (+3V) CLK_FLEX1
F47 TP36
CLKOUTFLEX1 / GPIO65
PLTRST#(CLG) +3VS5 SMBus/Pull-up(CLG) CLK_REQ/Strap Pin(CLG) +3V
K12
PCIECLKRQ7# / GPIO46 (+3V)
H47 CLK_FLEX2 TP62
(+3VS5) CLKOUTFLEX2 / GPIO66
TP25 AK14
CLKOUT_ITPXDP_N (+3V) Rb
C365 *0.1U/10V_4 CLK_PCIE_REQ1# R441 10K_4 AK13 K49 CLK_FLEX3 R524 22_4 PCH_CLK_27M_1
TP23 CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67
2N7002K CLK_PCIE_REQ2# R229 10K_4
5

13,29 MBCLK2 1 3 SMB_ME1_CLK CLK_PCH_ITPN Remove Ra, Rb for UMA &


2 +3VS5 CLK_PCH_ITPP CougarPoint_Rev_0p7 AJ0QMZQ0T00
PLTRST# Q21 R250 2.2K_4 fcbga989-intel-cougarpoint IC CTRL(989P)COUGARPOINT QMVY TOP B/S
SG. 27MHz support DIS only.
4
PCI_PLTRST# 1 CLK_PCIE_REQ0# R445 10K_4
2

+3V +3VS5 CLK_PCIE_REQ3# R478 10K_4


U11 CLK_PCIE_REQ4# R237 10K_4
PCIE Clock SMBus/Pull-up(CLG)
3

*TC7SH08FU R193 R248 2.2K_4 +3VS5


100K_4 CLK_PEGB_REQ# R222 10K_4 3/26 DB change Part reference.
13,29 MBDATA2 1 3 SMB_ME1_DAT CLK_PEGA_REQ# Ra R212 *10K_4 30 CLK_PCIE_WLANN RP1 1 2 CLK_PCH_SRC0N R490 1K_4 DRAMRST_CNTRL_PCH
R208 CLK_PEGA_REQ# Rb R194 10K_4 WLAN 30 CLK_PCIE_WLANP 0_4P2R_4 3 4 CLK_PCH_SRC0P
0_4 Q20 R240 10K_4 SMBALERT#
A
PLTRST# 2N7002K SG : Rb ; UMA : Ra R461 0_4 CLK_PCIE_REQ0# R188 2.2K_4 SMB_PCH_CLK A
PLTRST# 2,14,24,27,29,30 30 PCIE_CLKREQ_WLAN#
CLK_BUF_BCLK_N R270 10K_4 R482 2.2K_4 SMB_PCH_DAT
CLK_BUF_BCLK_P R269 10K_4 3/26 DB change Part reference. R475 2.2K_4 SMB_ME0_CLK
SMB_PCH_DAT 3 1 SMB_RUN_DAT 12,13 27 CLK_PCIE_LANP RP3 3 4 CLK_PCH_SRC2P R245 2.2K_4 SMB_ME0_DAT
LAN 0_4P2R_4 1 CLK_PCH_SRC2N R238 10K_4 SML1ALERT#_R
PEG Clock detect (SG only) Q18 CLK_BUF_PCIE_3GPLL# R243 10K_4
27 CLK_PCIE_LANN 2

2N7002K R192 4.7K_4 CLK_BUF_PCIE_3GPLL R242 10K_4 R457 0_4 CLK_PCIE_REQ1#


352-(&75
27 PCIE_CLKREQ_LAN#
2

+3V CLK_BUF_DREFCLK# R266 10K_4


DGPU_PWROK_1 35
R191 4.7K_4 CLK_BUF_DREFCLK R262 10K_4 3/26 DB change Part reference.
4XDQWD&RPSXWHU,QF
2

CLK_BUF_DREFSSCLK# R231 10K_4 14 CLK_PCIE_VGA# RP2 2 1 CLK_PCH_PEGAN


CLK_BUF_DREFSSCLK R230 10K_4 GPU 14 CLK_PCIE_VGA 0_4P2R_4 4 3 CLK_PCH_PEGAP
1 3 CLK_PEGA_REQ# SMB_PCH_CLK 3 1 SMB_RUN_CLK 12,13 CLK_PCH_14M R285 10K_4
Remove for UMA only. Size Document Number Rev
+3VS5 2,6,7,9,10,22,26,31,32,38,39
1%
Q19 Q17 CLOCK TERMINATION for FCIM Custom PCH 3/6 (PCIE/USB/CLK) 3A
1A
+3V 2,6,7,9,10,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,38,39
*2N7002 2N7002K
Date: Saturday, September 18, 2010 Sheet 8 of 39

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29 PCI_SERR# R190 *0_4 S_GPIO


ʹΠΦΘΒΣ͑΁ΠΚΟΥ͙͑͸΁ͺ΀͝·΄΄ΐͿʹ΅ͷ͝΃΄·͵͚
T7
U24F

BMBUSY# / GPIO0 TACH4 / GPIO68 C40 GPIO68 R512 10K_4 +3V


Clock Gen Power OK (CLG)

SIO_EXT_SMI# (+3V) (+3V) GPIO69 R515 1.5K/F_4
29 SIO_EXT_SMI# A42 TACH1 / GPIO1 TACH5 / GPIO69 B41
R516 *1.5K/F_4 +3V
SIO_EXT_SCI# (+3V) (+3V) GPIO70
29 SIO_EXT_SCI# H36 TACH2 / GPIO6 TACH6 / GPIO70 C41

BT_OFF# (+3V) (+3V) GPIO71


26,30 BT_OFF# E38 TACH3 / GPIO7 TACH7 / GPIO71 A40
ACCLED_EN
D ICC_EN# (+3V) D
7 ICC_EN# C10 GPIO8 (+3V)
LAN_DISABLE#_R C4
(+3VS5)
LAN_PHY_PW R_CTRL / GPIO12
RF_OFF# (+3VS5)
30 RF_OFF# G2 GPIO15 A20GATE P4 EC_A20GATE 29
(+3VS5) PECI AU16
Reserve R452 *0_4 ODD_PRSNT#_R U2

CPU/MISC
23 ODD_PRSNT# SATA4GP / GPIO16
P5 EC_RCIN#
RCIN# EC_RCIN# 29
(+3V)
DGPU_PWROK D40 AY11

GPIO
8,17,29,35,39 DGPU_PWROK TACH0 / GPIO17 PROCPW RGD H_PWRGOOD 2
BIOS_REC T5
(+3V) AY10 PCH_THRMTRIP# R481 390_4
SCLOCK / GPIO22 THRMTRIP# PM_THRMTRIP# 2,29 MFG-TEST GPIO Pull-up/Pull-down(CLG)
BOARD_ID5 (+3V)
E8 GPIO24 / MEM_LED INIT3_3V# T14
+3V
GPIO27 (+3VS5) +3VS5
E16 GPIO27 MFG_MODE R456 10K_4
R448 0_4 PLL_ODVR_EN_R (DSW) LAN_DISABLE#_R R472 10K_4
7 PLL_ODVR_EN P8 GPIO28
AH8 R440 *0_4 ACCLED_EN R486 *10K_4
BOARD_ID3 K1
(+3VS5) NC_1
9/3 SI for H/W. STP_PCI# / GPIO34 +3V
(+3V) NC_2 AK11
DGPU_HOLD_RST# K4
8,14 DGPU_HOLD_RST# GPIO35
AH10 SIO_EXT_SCI# R288 10K_4
R209 0_4 DGPU_PWR_EN_R V8
(+3V) NC_3 SIO_EXT_SMI# R517 10K_4
35 DGPU_PWR_EN SATA2GP / GPIO36 BT_OFF#
AK10 R289 10K_4
FDI_OVRVLTG (+3V) NC_4 R247 0_4 EC_A20GATE R203 10K_4
M5 SATA3GP / GPIO37
P37 EC_RCIN# R220 10K_4
MFG_MODE (+3V) NC_5 GPIO49 R464 *10K_4
N2 SLOAD / GPIO38 GPIO70 R518 1.5K/F_4
C DGPU_PRSNT# (+3V) DG rev0.9 suggest to TS_VSS connect to GND. +3V GPIO71 R513 1.5K/F_4 C
M3 SDATAOUT0 / GPIO39 ODD_PRSNT#_R R453 10K_4
TEST_SET_UP (+3V) S_GPIO R200 10K_4 DGPU_PWROK R290 10K_4
V13 SDATAOUT1 / GPIO48 VSS_NCTF_15 BG2
R210 *0_4
GPIO49 (+3V)
24 GPIO49 V3 SATA5GP / GPIO49 VSS_NCTF_16 BG48
DGPU_PWROK R291 *10K_4
SV_DET (+3V) GPIO27 R251 10K_4
D6 GPIO57 VSS_NCTF_17 BH3
(+3VS5)
VSS_NCTF_18 BH47

A4 VSS_NCTF_1 VSS_NCTF_19 BJ4

A44 VSS_NCTF_2 VSS_NCTF_20 BJ44

A45 BJ45 +3VS5


VSS_NCTF_3 VSS_NCTF_21 +3V
A46
NCTF BJ46 RF_OFF# R449 1K_4
VSS_NCTF_4 VSS_NCTF_22 R213 *0_4 BIOS_REC R195 10K_4
A5 VSS_NCTF_5 VSS_NCTF_23 BJ5
Intel ME Crypto Transport Layer
A6 VSS_NCTF_6 VSS_NCTF_24 BJ6 Security (TLS) cipher suite
BIOS RECOVERY High = Disable (Default)
B3 VSS_NCTF_7 VSS_NCTF_25 C2 Low = Disable (Default) Low = Enable
High = Enable
B47 VSS_NCTF_8 VSS_NCTF_26 C48

BD1 VSS_NCTF_9 VSS_NCTF_27 D1

BD49 VSS_NCTF_10 VSS_NCTF_28 D49


B BE1 E1 +3V +3V B
VSS_NCTF_11 VSS_NCTF_29
BE49 E49 R214 *0_4 TEST_SET_UP R196 10K_4 R236 100K_4 SV_DET R235 *10K_4
VSS_NCTF_12 VSS_NCTF_30
BF1 VSS_NCTF_13 VSS_NCTF_31 F1
SV_SET_UP TEST DETECT
BF49 VSS_NCTF_14 VSS_NCTF_32 F49
High = Strong (Default) Low = Default
+3VS5 2,6,7,8,10,22,26,31,32,38,39
CougarPoint_Rev_0p7 IC CTRL(989P)COUGARPOINT QMVY TOP B/S
+3V 2,6,7,8,10,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,38,39
fcbga989-intel-cougarpoint
AJ0QMZQ0T00

+3V +3V
BOARD_ID0
BOARD ID SETTING 8
8
8
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID1
BOARD_ID2
9/3 SI for H/W. DGPU_PWR_EN_R R199 *200K/F_4 R201 100K_4 FDI_OVRVLTG R218 *1K_4

BOARD_ID4
8 BOARD_ID4
Low = Tx, Rx terminated to
RD0 9/3 SI for H/W. DMI TERMINATION same voltage (DC Coupling Mode) FDI TERMINATION LOW - Tx, Rx terminated
BOARD_ID5 BOARD_ID4 BOARD_ID3 BOARD_ID2 BOARD_ID1 BOARD_ID0
Model VOLTAGE OVERRIDE (DEFAULT) VOLTAGE OVERRIDE to same voltage

BOARD_ID0
RU0
R13 UMA 0 0 0 0 0 0 R451 *10K_4 R466 10K_4 +3VS5

RD1 BOARD_ID1
RU1
R13 DIS 0 0 0 0 0 1 R215 10K_4 R197 *10K_4

A A
RD2 RU2
0 0 0 0 0 0 R226 10K_4 BOARD_ID2 R232 *10K_4 GFX Present +3V
RD3 RU3 Rb Ra
0 0 0 0 0 0 R460 10K_4 BOARD_ID3 R444 *10K_4 R442 *100K_4 DGPU_PRSNT# R458 10K_4
+3V

0 0 0 0 0 0 R221
RD4
10K_4 BOARD_ID4 R205
RU4
*10K_4 SG UMA
352-(&75
Stuff Ra Rb
4XDQWD&RPSXWHU,QF
RD5 BOARD_ID5
RU5
R241 10K_4 R227 *10K_4 +3VS5
NC Rb Ra Size Document Number Rev

1%
Custom PCH 4/6 (GPIO/MISC) 3A
1A

Date: Saturday, September 18, 2010 Sheet 9 of 39


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1mA (10mils)
+3V
Cougar Point-M (POWER) +VCCA_DAC_1_2
L56

U24J +1.05V_VCCUSBCORE +1.05V_VTT 1.3 A (60mils)


COUGAR POINT (POWER) *HCB1608KF-181T15/1.5A_6
+1.05V_VTT R526 *0_8
+VCCACLK AD49 N26 R506 0_8 +1.05V_VTT +1.05V_PCH_VCC U24G +3V_LDO
R257 0_4 VCCACLK VCCIO[29]
+3VS5
VCCIO[30] P26
+VCCPDSW T16 C615 AA23 U48
VCCDSW3_3 1U/6.3V_4 VCCCORE[1] VCCADAC
3mA (10mils) VCCIO[31] P28 119mA (20mils) AC23 VCCCORE[2] 9/15 SI for EE
C369 C388 C381 AD21

CRT
C377 PCH_VCCDSW +3VS5 1U/6.3V_4 1U/6.3V_4 VCCCORE[3] C632 10U/6.3VS_6
V12 DCPSUSBYP VCCIO[32] T27 AD23 VCCCORE[4] VSSADAC U47
0.1U/10V_4 AF21
*0.1U/10V_4 R263 0_6 VCCCORE[5] C626 0.1U/10V_4
9/10 SI for H/W. T29 AF23

VCC CORE
+3V_SUS_CLKF33 VCCIO[33] VCCCORE[6]
D T38 VCC3_3[5] AG21 VCCCORE[7] D
AG23 C629 0.01U/25V_4
+3V_VCCPUSB C382 VCCCORE[8]
VCCSUS3_3[7] T23 AG24 VCCCORE[9]
BH23 0.1U/10V_4 AG26 R533 *0_6
+1.05V_VTT +VCCAPLL_CPY_PCH VCCAPLLDMI2 C378 C392 VCCCORE[10]
VCCSUS3_3[8] T24 AG27 VCCCORE[11]
L49 +VCCDPLL_CPY AL29 10U/6.3VS_6 1U/6.3V_4 AG29 1mA (10mils)
VCCIO[14] VCCCORE[12]

USB
V23 R261 0_6 AJ23
VCCSUS3_3[9] VCCCORE[13] +VCCALVDS +3V
AJ26 VCCCORE[14]
*10uH/100mA_8 +VCCSUS1 AL24 V24 AJ27 Ra
C607 DCPSUS[3] VCCSUS3_3[10] C383 VCCCORE[15]
AJ29 VCCCORE[16] VCCALVDS AK36
*10U/6.3V_6 P24 +3V_VCCAUBG 0.1U/10V_4 +1.05V_VTT +1.05V_PCH_VCCDPLL_EXP AJ31
C384 VCCSUS3_3[6] R254 VCCCORE[17]
AK37
+1.05V_VTT *1U/6.3V_4 AA19 VCCASW[1]
VSSALVDS DEL
R268 T26 +VCCAUPLL R267 0_6 +1.05V_VTT 60mA (10mils)
VCCIO[34] 0_6
AA21 VCCASW[2] Ra
AM37 +VCC_TX_LVDS L54 +1.8V
0_6 +5V_PCH_VCC5REFSUS +1.05V_VTT +1.05V_VCCAPLL_EXP VCCTX_LVDS[1] 0.1uH/250mA_8
AA24 VCCASW[3] V5REF_SUS M26 AN19 VCCIO[28]
L48 AM38

LVDS
+1.05V_VTT +1.05V_VCCEPW VCCTX_LVDS[2]
1.01A (60mils) AA26 VCCASW[4]
AN23 +VCCA_USBSUS C379 *1U/6.3V_4 AP36
AA27 VCCASW[5]
DCPSUS[4] *1uH/25mA_6 VCCTX_LVDS[3] DEL
AN24 +3V_VCCPSUS C605 AP37 C633 22U/6.3VS_8

Clock and Miscellaneous


VCCSUS3_3[1] *10U/6.3V_6 VCCTX_LVDS[4]
AA29 VCCASW[6] BJ22 VCCAPLLEXP
C387 C394 C393 SG & UMA : Ra C635 0.01U/25V_4
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 AA31 VCCASW[7] DIS : Rb C630 0.01U/25V_4
AC26 P34 +5V_PCH_VCC5REF
VCCASW[8] V5REF +1.05V_VTT AN16 VCCIO[15]
AC27 2.925 A (140mils) +3V_VCC_GIO +3V
VCCASW[9]
VCCSUS3_3[2] N20 AN17 VCCIO[16] R548 0_6

PCI/GPIO/LPC
AC29 V33

HVCMOS
C366 C367 VCCASW[10] VCC3_3[6]
VCCSUS3_3[3] N22 119mA (15mils)
22U/6.3VS_8 22U/6.3VS_8 AC31 C400 C401 AN21 V34
VCCASW[11] +3V_VCCPSUS R265 0_6 1U/6.3V_4 1U/6.3V_4 VCCIO[17] VCC3_3[7] C662
VCCSUS3_3[4] P20 +3VS5
AD29 AN26 0.1U/10V_4
VCCASW[12] VCCIO[18]
C VCCSUS3_3[5] P22 C
AD31 C380 AN27 42mA (10mils)
VCCASW[13] 1U/6.3V_4 VCCIO[19]

VCCIO
W21 AA16 266mA (20mils) AP21 AT16 +VCCAFDI_VRM +1.1V_VCC_DMI +1.05V_VTT
VCCASW[14] VCC3_3[1] C386 C389 C390 VCCIO[20] VCCVRM[3]
W23 W16 +3V_VCCPCORE R189 0_6 10U/6.3VS_6 1U/6.3V_4 1U/6.3V_4 AP23 AT20 R252 0_4

DMI
VCCASW[15] VCC3_3[8] +3V VCCIO[21] VCCDMI[1]
W24 T34 AP24 +1.1V_VCC_DMI_CCI
VCCASW[16] VCC3_3[4] +3V VCCIO[22]
C363 C376
W26 0.1U/10V_4 AP26 AB36 1U/6.3V_4
VCCASW[17] C594 +3V +3V_VCC_EXP VCCIO[23] VCCCLKDMI
W29 0.1U/10V_4 AT24
VCCASW[18] R504 0_8 VCCIO[24] C631 C640
W31 AJ2 +3V 1U/6.3V_4 *10U/6.3V_6
R471 0_6 VCCASW[19] VCC3_3[2]
+1.05V_VTT AN33 VCCIO[25]
W33 C611
VCCASW[20] C403 0.1U/10V_4 AN34 VCCIO[26]
C595 0.1U/10V_4 190 mA (15mils)
1U/6.3V_4 C371 +VCCRTCEXT N16 AF13 160mA (15mils) AG16
0.1U/10V_4 DCPRTC VCCIO[5] VCCPNAND[1] +VCCP_NAND +1.8V
BH29

NAND / SPI
+V1.05S_SATA3 R228 0_8 +VCCAFDI_VRM VCC3_3[3]
VCCIO[12] AH13 +1.05V_VTT (Mobile 1.5V)
+1.05V_VTT R528 0_6 +VCCAFDI_VRM Y49 AG17 R223 0_8
VCCVRM[4] R534 0_6 VCCPNAND[2]
160mA (20mils) VCCIO[13] AH14 +1.5V
C368
C623 +1.05V_VCCA_A_DPL BD47 AF14 1U/6.3V_4 +1.05V_VTT R536 *0_6 +VCCAFDI_VRM AP16 AJ16 C373
VCCADPLLA VCCIO[6] VCCVRM[2] VCCPNAND[3]
SATA

1U/6.3V_4 65mA (10mils) 0.1U/10V_4


+1.05V_VCCAPLL_FDI
+1.05V_VCCA_B_DPL BF47 AK1 +V1.1LAN_VCCAPLL L47 +1.05V_VTT AJ17
R527 0_6 VCCADPLLB VCCAPLLSATA *10uH/100mA_8 R450 *0_8 VCCPNAND[4]
+1.05V_VTT 8mA (10mils) +1.05V_VTT BG6 VccAFDIPLL
AF11 +VCCAFDI_VRM 20mA (10mils)

FDI
+VCCDIFFCLK VCCVRM[1] C593 R492 0_8
AF17 VCCIO[7] AP17 VCCIO[27]
C625 +VCCDIFFCLKN AF33 *10U/6.3V_6 +3V_VCCME_SPI +3V
1U/6.3V_4 VCCDIFFCLKN[1] +1.05V_VCCDPLL_FDI
55mA (10mils) AF34 VCCDIFFCLKN[2] VCCIO[2] AC16
AG34 V1 R436 0_6
VCCDIFFCLKN[3] +1.05V_VCCIO1 R206 0_6 VCCSPI
VCCIO[3] AC17 +1.05V_VTT +1.05V_VTT AU20 VCCDMI[2]
B B
+V1.05V_SSCVCC AG33 AD17 C590
R256 *0_6 VCCSSC VCCIO[4] C374 CougarPoint_Rev_0p7 1U/6.3V_4
+1.05V_VTT 95mA (10mils)
1.01A (60mils) 1U/6.3V_4 fcbga989-intel-cougarpoint
C372 +VCCSST V16 AJ0QMZQ0T00
C375 0.1U/10V_4 DCPSST +1.05V_VCCEPW +1.05V_VTT IC CTRL(989P)COUGARPOINT QMVY TOP B/S
65mA (10mils)
*1U/6.3V_4 +5V_PCH_VCC5REF R271 10_4 +5V
T17 T21 L53 +1.05V_VCCA_A_DPL C620 1U/6.3V_4
+V1.05M_VCCSUS DCPSUS[1] VCCASW[22] 10uH/100MA_8 D7 RB500V-40
V19 DCPSUS[2] V5REF= 1mA +3V
C627 *220U/2.5V_3528 C395

+
MISC

+1.05V_VTT R488 0_4 +VTT_VCCPCPU V21 8mA (10mils) 1U/6.3V_4


VCCASW[23]
10mA (10mils)
CPU

V_PROC_IO=1mA BJ8 L50 +1.05V_VCCA_B_DPL C617 1U/6.3V_4


C603 C601 C602 V_PROC_IO +V3.3A_1.5A_HDA_IO 10uH/100MA_8
(10mils) VCCASW[21] T19
4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 C406 *220U/2.5V_3528 +5V_PCH_VCC5REFSUS R274 10_4

+
+5VS5
R505 *0_4 +1.5VSUS
VCC5REFSUS=1mA D8 RB500V-40 +3VS5
RTC

A22 P32 R507 0_4 +3V 20mA (10mils) C402


+3V_RTC +3VS5
HDA

VCCRTC VCCSUSHDA 0.1U/10V_4


VCCRTC<1mA R539 *0_6 +3V_SUS_CLKF33 C642 1U/6.3V_4
C606 C612 C610 CougarPoint_Rev_0p7 C613 C614
(10mils) 1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 fcbga989-intel-cougarpoint 0.1U/10V_4 *1U/6.3V_4 R543 1/F_4 +3V_SUS_CLKF33_R C639 10U/6.3VS_6
AJ0QMZQ0T00 L58
IC CTRL(989P)COUGARPOINT QMVY TOP B/S 10uH/100mA_8
20mA (10mils)
+3V_RTC 6,7 +1.05V_VTT +VCC_DMI_CCI +1.1V_VCC_DMI_CCI
+3V_DSW
+3VS5 2,6,7,8,9,22,26,31,32,38,39
R540 *1/F_4 UMA Only, If have power noise issue then stuff it.
+1.05V_VTT 2,4,6,7,8,29,32,33 +3V 2,6,7,8,9,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,38,39 +5V +3V_LDO
L55
+1.5VSUS 2,4,12,13,22,35,39 +5VS5 20,26,31,32,33,34,35,36,38,39
R541 0_4 *10uH/100mA_8 U29
+1.8V 4,7,32,39 +5V 6,7,17,21,22,23,25,28,30,38
G910T21U
3 Vin Vout 1

GND
A A
C699

2
1U/6.3V_4 9/15 SI for EE

352-(&75
4XDQWD&RPSXWHU,QF

www.vinafix.vn
http://laptop-motherboard-schematic.blogspot.com/ Size Document Number Rev

1%
Custom PCH 5/6 (POWER) 3A

Date: Saturday, September 18, 2010 Sheet 10 of 39


5 4 3 2 1
5 4 3 2 1

IBEX PEAK-M (GND)


U24I
IBEX PEAK-M (GND)
U24H

AY4 VSS[159] VSS[259] H46
AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26 H5 VSS[0]
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46 AA17 VSS[1] VSS[80] AK38
B15 VSS[164] VSS[264] K7 AA2 VSS[2] VSS[81] AK4
D B19 L18 AA3 AK42 D
VSS[165] VSS[265] VSS[3] VSS[82]
B23 VSS[166] VSS[266] L2 AA33 VSS[4] VSS[83] AK46
B27 VSS[167] VSS[267] L20 AA34 VSS[5] VSS[84] AK8
B31 VSS[168] VSS[268] L26 AB11 VSS[6] VSS[85] AL16
B35 VSS[169] VSS[269] L28 AB14 VSS[7] VSS[86] AL17
B39 VSS[170] VSS[270] L36 AB39 VSS[8] VSS[87] AL19
B7 VSS[171] VSS[271] L48 AB4 VSS[9] VSS[88] AL2
F45 VSS[172] VSS[272] M12 AB43 VSS[10] VSS[89] AL21
BB12 VSS[173] VSS[273] P16 AB5 VSS[11] VSS[90] AL23
BB16 VSS[174] VSS[274] M18 AB7 VSS[12] VSS[91] AL26
BB20 VSS[175] VSS[275] M22 AC19 VSS[13] VSS[92] AL27
BB22 VSS[176] VSS[276] M24 AC2 VSS[14] VSS[93] AL31
BB24 VSS[177] VSS[277] M30 AC21 VSS[15] VSS[94] AL33
BB28 VSS[178] VSS[278] M32 AC24 VSS[16] VSS[95] AL34
BB30 VSS[179] VSS[279] M34 AC33 VSS[17] VSS[96] AL48
BB38 VSS[180] VSS[280] M38 AC34 VSS[18] VSS[97] AM11
BB4 VSS[181] VSS[281] M4 AC48 VSS[19] VSS[98] AM14
BB46 VSS[182] VSS[282] M42 AD10 VSS[20] VSS[99] AM36
BC14 VSS[183] VSS[283] M46 AD11 VSS[21] VSS[100] AM39
BC18 VSS[184] VSS[284] M8 AD12 VSS[22] VSS[101] AM43
BC2 VSS[185] VSS[285] N18 AD13 VSS[23] VSS[102] AM45
BC22 VSS[186] VSS[286] P30 AD19 VSS[24] VSS[103] AM46
BC26 VSS[187] VSS[287] N47 AD24 VSS[25] VSS[104] AM7
BC32 VSS[188] VSS[288] P11 AD26 VSS[26] VSS[105] AN2
BC34 VSS[189] VSS[289] P18 AD27 VSS[27] VSS[106] AN29
BC36 VSS[190] VSS[290] T33 AD33 VSS[28] VSS[107] AN3
BC40 VSS[191] VSS[291] P40 AD34 VSS[29] VSS[108] AN31
BC42 VSS[192] VSS[292] P43 AD36 VSS[30] VSS[109] AP12
BC48 VSS[193] VSS[293] P47 AD37 VSS[31] VSS[110] AP19
BD46 VSS[194] VSS[294] P7 AD38 VSS[32] VSS[111] AP28
C BD5 R2 AD39 AP30 C
VSS[195] VSS[295] VSS[33] VSS[112]
BE22 VSS[196] VSS[296] R48 AD4 VSS[34] VSS[113] AP32
BE26 VSS[197] VSS[297] T12 AD40 VSS[35] VSS[114] AP38
BE40 VSS[198] VSS[298] T31 AD42 VSS[36] VSS[115] AP4
BF10 VSS[199] VSS[299] T37 AD43 VSS[37] VSS[116] AP42
BF12 VSS[200] VSS[300] T4 AD45 VSS[38] VSS[117] AP46
BF16 VSS[201] VSS[301] W 34 AD46 VSS[39] VSS[118] AP8
BF20 VSS[202] VSS[302] T46 AD8 VSS[40] VSS[119] AR2
BF22 VSS[203] VSS[303] T47 AE2 VSS[41] VSS[120] AR48
BF24 VSS[204] VSS[304] T8 AE3 VSS[42] VSS[121] AT11
BF26 VSS[205] VSS[305] V11 AF10 VSS[43] VSS[122] AT13
BF28 VSS[206] VSS[306] V17 AF12 VSS[44] VSS[123] AT18
BD3 VSS[207] VSS[307] V26 AD14 VSS[45] VSS[124] AT22
BF30 VSS[208] VSS[308] V27 AD16 VSS[46] VSS[125] AT26
BF38 VSS[209] VSS[309] V29 AF16 VSS[47] VSS[126] AT28
BF40 VSS[210] VSS[310] V31 AF19 VSS[48] VSS[127] AT30
BF8 VSS[211] VSS[311] V36 AF24 VSS[49] VSS[128] AT32
BG17 VSS[212] VSS[312] V39 AF26 VSS[50] VSS[129] AT34
BG21 VSS[213] VSS[313] V43 AF27 VSS[51] VSS[130] AT39
BG33 VSS[214] VSS[314] V7 AF29 VSS[52] VSS[131] AT42
BG44 VSS[215] VSS[315] W 17 AF31 VSS[53] VSS[132] AT46
BG8 VSS[216] VSS[316] W 19 AF38 VSS[54] VSS[133] AT7
BH11 VSS[217] VSS[317] W2 AF4 VSS[55] VSS[134] AU24
BH15 VSS[218] VSS[318] W 27 AF42 VSS[56] VSS[135] AU30
BH17 VSS[219] VSS[319] W 48 AF46 VSS[57] VSS[136] AV16
BH19 VSS[220] VSS[320] Y12 AF5 VSS[58] VSS[137] AV20
H10 VSS[221] VSS[321] Y38 AF7 VSS[59] VSS[138] AV24
BH27 VSS[222] VSS[322] Y4 AF8 VSS[60] VSS[139] AV30
BH31 VSS[223] VSS[323] Y42 AG19 VSS[61] VSS[140] AV38
BH33 VSS[224] VSS[324] Y46 AG2 VSS[62] VSS[141] AV4
B BH35 Y8 AG31 AV43 B
VSS[225] VSS[325] VSS[63] VSS[142]
BH39 VSS[226] VSS[328] BG29 AG48 VSS[64] VSS[143] AV8
BH43 VSS[227] VSS[329] N24 AH11 VSS[65] VSS[144] AW 14
BH7 VSS[228] VSS[330] AJ3 AH3 VSS[66] VSS[145] AW 18
D3 VSS[229] VSS[331] AD47 AH36 VSS[67] VSS[146] AW 2
D12 VSS[230] VSS[333] B43 AH39 VSS[68] VSS[147] AW 22
D16 VSS[231] VSS[334] BE10 AH40 VSS[69] VSS[148] AW 26
D18 VSS[232] VSS[335] BG41 AH42 VSS[70] VSS[149] AW 28
D22 VSS[233] VSS[337] G14 AH46 VSS[71] VSS[150] AW 32
D24 VSS[234] VSS[338] H16 AH7 VSS[72] VSS[151] AW 34
D26 VSS[235] VSS[340] T36 AJ19 VSS[73] VSS[152] AW 36
D30 VSS[236] VSS[342] BG22 AJ21 VSS[74] VSS[153] AW 40
D32 VSS[237] VSS[343] BG24 AJ24 VSS[75] VSS[154] AW 48
D34 VSS[238] VSS[344] C22 AJ33 VSS[76] VSS[155] AV11
D38 VSS[239] VSS[345] AP13 AJ34 VSS[77] VSS[156] AY12
D42 VSS[240] VSS[346] M14 AK12 VSS[78] VSS[157] AY22
D8 VSS[241] VSS[347] AP3 AK3 VSS[79] VSS[158] AY28
E18 VSS[242] VSS[348] AP1
E26 VSS[243] VSS[349] BE16
G18 VSS[244] VSS[350] BC16
G20 BG28 CougarPoint_Rev_0p7
VSS[245] VSS[351]
G26 VSS[246] VSS[352] BJ28
G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
A H30 A
VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]

CougarPoint_Rev_0p7
352-(&75
4XDQWD&RPSXWHU,QF
Size Document Number Rev

1%
Custom PCH 6/6 (GND) 3A
1A

Date: Saturday, September 18, 2010 Sheet 11 of 39


5 4 3 2 1

www.vinafix.vn
http://laptop-motherboard-schematic.blogspot.com/
5 4 3 2 1

3 M_A_A[15:0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
98
97
96
95
JDIM1A
A0
A1
A2
DQ0
DQ1
DQ2
5
7
15
17
M_A_DQ4
M_A_DQ5
M_A_DQ7
M_A_DQ6
M_A_DQ[63:0] 3
2.48A +1.5VSUS

75
76
81
JDIM1B
VDD1
VDD2
VSS16
VSS17
44
48
49

M_A_A4 A3 DQ3 M_A_DQ1 VDD3 VSS18
92 A4 DQ4 4 82 VDD4 VSS19 54
M_A_A5 91 6 M_A_DQ0 87 55
M_A_A6 A5 DQ5 M_A_DQ3 VDD5 VSS20
90 A6 DQ6 16 88 VDD6 VSS21 60
M_A_A7 86 18 M_A_DQ2 93 61
M_A_A8 A7 DQ7 M_A_DQ9 VDD7 VSS22
89 A8 DQ8 21 94 VDD8 VSS23 65
M_A_A9 85 23 M_A_DQ8 99 66
D M_A_A10 A9 DQ9 M_A_DQ15 VDD9 VSS24 D
107 A10/AP DQ10 33 100 VDD10 VSS25 71
M_A_A11 84 35 M_A_DQ10 105 72
M_A_A12 A11 DQ11 M_A_DQ12 VDD11 VSS26

PC2100 DDR3 SDRAM SO-DIMM


83 A12/BC# DQ12 22 106 VDD12 VSS27 127
M_A_A13 119 24 M_A_DQ13 111 128
M_A_A14 A13 DQ13 M_A_DQ14 VDD13 VSS28
80 A14 DQ14 34 112 VDD14 VSS29 133
M_A_A15 78 36 M_A_DQ11 117 134
A15 DQ15 M_A_DQ21 VDD15 VSS30

PC2100 DDR3 SDRAM SO-DIMM


DQ16 39 118 VDD16 VSS31 138
109 41 M_A_DQ16 123 139
3 M_A_BS#0 BA0 DQ17 VDD17 VSS32
108 51 M_A_DQ19 124 144
3 M_A_BS#1 BA1 DQ18 VDD18 VSS33
79 53 M_A_DQ18 145
3 M_A_BS#2 BA2 DQ19 M_A_DQ20 VSS34
3 M_A_CS#0 114 S0# DQ20 40 +3V 199 VDDSPD VSS35 150
121 42 M_A_DQ17 151
3 M_A_CS#1 S1# DQ21 M_A_DQ23 VSS36
3 M_A_CLKP0 101 CK0 DQ22 50 77 NC1 VSS37 155
103 52 M_A_DQ22 122 156
3 M_A_CLKN0 CK0# DQ23 NC2 VSS38
102 57 M_A_DQ25 R150 10K_4 125 161
3 M_A_CLKP1 CK1 DQ24 M_A_DQ24 +3V NCTEST VSS39
3 M_A_CLKN1 104 CK1# DQ25 59 VSS40 162
73 67 M_A_DQ30 13 PM_EXTTS#0 PM_EXTTS#0 198 167
3 M_A_CKE0 CKE0 DQ26 EVENT# VSS41
74 69 M_A_DQ26 2,13 DDR3_DRAMRST# 30 168
3 M_A_CKE1 CKE1 DQ27 RESET# VSS42
115 56 M_A_DQ28 172
3 M_A_CAS# CAS# DQ28 VSS43
110 58 M_A_DQ29 173
3 M_A_RAS# RAS# DQ29 VSS44
113 68 M_A_DQ31 SMDDR_VREF_DQ0_M1 R74 0_6 +SMDDR_VREF_DQ0 1 178
3 M_A_WE# W E# DQ30 VREF_DQ VSS45
R157 10K_4 DIMM0_SA0 197 70 M_A_DQ27 +SMDDR_VREF_DIMM 126 179
R161 10K_4 DIMM0_SA1 SA0 DQ31 M_A_DQ36 SMDDR_VREF_DQ0_M3 R35 *0_6 VREF_CA VSS46
201 SA1 DQ32 129 5 SMDDR_VREF_DQ0_M3 VSS47 184
8,13 SMB_RUN_CLK SMB_RUN_CLK 202 131 M_A_DQ37 185
SMB_RUN_DAT SCL DQ33 M_A_DQ34 VSS48
8,13 SMB_RUN_DAT 200 SDA DQ34 141 2 VSS1 VSS49 189
143 M_A_DQ38 3 190
DQ35 M_A_DQ32 VSS2 VSS50
116 130 8 195

(204P)
3 M_A_ODT0 ODT0 DQ36 VSS3 VSS51
120 132 M_A_DQ33 SI reseve pad for RF 9 196
3 M_A_ODT1 ODT1 DQ37 VSS4 VSS52
140 M_A_DQ35 13
M_A_DM1 DQ38 M_A_DQ39 VSS5
11 DM0 DQ39 142 14 VSS6
C 28 147 M_A_DQ41 19 C
DM1 DQ40 M_A_DQ45 C234 *2.2U/6.3V_6 VSS7
46 149 20

(204P)
DM2 DQ41 +1.5VSUS VSS8
63 157 M_A_DQ47 25
M_A_DM2 DM3 DQ42 M_A_DQ46 C99 *2.2U/6.3V_6 VSS9
136 DM4 DQ43 159 26 VSS10 VTT1 203 +0.75V_DDR_VTT
153 146 M_A_DQ40 31 204
DM5 DQ44 M_A_DQ44 C436 *2.2U/6.3V_6 VSS11 VTT2
170 DM6 DQ45 148 +1.5V 32 VSS12
187 158 M_A_DQ42 37 205
DM7 DQ46 M_A_DQ43 C437 *2.2U/6.3V_6 VSS13 GND
3 M_A_DQSP[7:0] DQ47 160 38 VSS14 GND 206
M_A_DQSP0 12 163 M_A_DQ49 43
M_A_DQSP1 DQS0 DQ48 M_A_DQ48 VSS15
29 DQS1 DQ49 165
M_A_DQSP2 47 175 M_A_DQ54
M_A_DQSP3 DQS2 DQ50 M_A_DQ55 DDR3-DIMM0_H=5.2_RVS
64 DQS3 DQ51 177
M_A_DQSP4 137 164 M_A_DQ53 DDR-78279-001-RVS-204P
M_A_DQSP5 DQS4 DQ52 M_A_DQ52 DGMK4000125
154 DQS5 DQ53 166
M_A_DQSP6 171 174 M_A_DQ50 IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS)
M_A_DQSP7 DQS6 DQ54 M_A_DQ51
3 M_A_DQSN[7:0] 188 DQS7 DQ55 176
M_A_DQSN0 10 181 M_A_DQ61
M_A_DQSN1 DQS#0 DQ56 M_A_DQ60
27 DQS#1 DQ57 183
M_A_DQSN2 45 191 M_A_DQ62
M_A_DQSN3 DQS#2 DQ58 M_A_DQ63
62 DQS#3 DQ59 193
M_A_DQSN4 135 180 M_A_DQ56
M_A_DQSN5 DQS#4 DQ60 M_A_DQ57
152 DQS#5 DQ61 182
M_A_DQSN6 169 192 M_A_DQ59
M_A_DQSN7 DQS#6 DQ62 M_A_DQ58
186 DQS#7 DQ63 194 +0.75V_DDR_VTT 13,35,38
+1.5VSUS 2,4,10,13,22,35,39
+3VPCU 7,20,28,29,31,37
DDR3-DIMM0_H=5.2_RVS
+3V 2,6,7,8,9,10,13,14,17,20,21,22,23,24,25,27,28,29,30,33,38,39
DDR-78279-001-RVS-204P
+5VPCU 29,31,37
DGMK4000125
IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS)
B B

VREF DQ0 M2 Solution Place these Caps near So-Dimm0. VREF DQ0 M1 Solution
+1.5VSUS +0.75V_DDR_VTT +1.5VSUS

C192 1U/6.3V_4 C338 1U/6.3V_4

C243 1U/6.3V_4 C564 1U/6.3V_4


R78
C223 1U/6.3V_4 C568 1U/6.3V_4 1K/F_4
+1.5VSUS
C142 1U/6.3V_4 C345 1U/6.3V_4 DDR_VTTREF R131 *0_6 SMDDR_VREF_DQ0_M1

C202 10U/6.3VS_6 C561 10U/6.3V_6 R126


del M2 solution C153 10U/6.3VS_6 C325 *10U/6.3V_6 R128
1K/F_4
10K_4

C127 10U/6.3VS_6
+SMDDR_VREF_DIMM R138 *0_6 +SMDDR_VREF_DIMM
4,13,35 DDR_VTTREF
C137 10U/6.3VS_6
C308 0.1U/10V_4
C182 10U/6.3VS_6
C294 2.2U/6.3V_6 R144 C315
C255 10U/6.3VS_6 10K_4 470P/50V_4

A C132 *10U/6.3V_6 +SMDDR_VREF_DQ0 A

C117 10U/6.3V_8 C28 0.1U/10V_4

C114 10U/6.3V_8 C80 2.2U/6.3V_6

+3V 352-(&75
C306 0.1U/10V_4
4XDQWD&RPSXWHU,QF
4/27: layout modify C321 2.2U/6.3V_6 Size Document Number Rev

1%
Custom DDR3 DIMM0-RVS (5.2H) 3A
1A

Date: Saturday, September 18, 2010 Sheet 12 of 39


5 4 3 2 1

www.vinafix.vn
http://laptop-motherboard-schematic.blogspot.com/
5 4 3 2 1

3 M_B_A[15:0]
M_B_A0
M_B_A1
M_B_A2
98
97
96
JDIM2A
A0
A1
DQ0
DQ1
5
7
15
M_B_DQ5
M_B_DQ4
M_B_DQ3
M_B_DQ[63:0] 3
+1.5VSUS

75
76
81
JDIM2B
VDD1
VDD2
VSS16
VSS17
44
48
49

M_B_A3 A2 DQ2 M_B_DQ2 VDD3 VSS18
95 A3 DQ3 17 82 VDD4 VSS19 54
M_B_A4 92 4 M_B_DQ0 87 55
M_B_A5 A4 DQ4 M_B_DQ1 VDD5 VSS20
91 A5 DQ5 6 88 VDD6 VSS21 60
M_B_A6 90 16 M_B_DQ6 93 61
M_B_A7 A6 DQ6 M_B_DQ7 VDD7 VSS22
86 A7 DQ7 18 94 VDD8 VSS23 65
M_B_A8 89 21 M_B_DQ12
D M_B_A9 85
A8 DQ8
23 M_B_DQ13
2.48A 99
100
VDD9 VSS24 66
71 D
M_B_A10 A9 DQ9 M_B_DQ14 VDD10 VSS25
107 A10/AP DQ10 33 105 VDD11 VSS26 72
M_B_A11 M_B_DQ10

PC2100 DDR3 SDRAM SO-DIMM


84 A11 DQ11 35 106 VDD12 VSS27 127
M_B_A12 83 22 M_B_DQ8 111 128
M_B_A13 A12/BC# DQ12 M_B_DQ9 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
M_B_A14 80 34 M_B_DQ11 117 134
M_B_A15 A14 DQ14 M_B_DQ15 VDD15 VSS30
78 A15 DQ15 36 118 VDD16 VSS31 138
M_B_DQ20

PC2100 DDR3 SDRAM SO-DIMM


DQ16 39 123 VDD17 VSS32 139
109 41 M_B_DQ21 124 144
3 M_B_BS#0 BA0 DQ17 VDD18 VSS33
108 51 M_B_DQ18 145
3 M_B_BS#1 BA1 DQ18 M_B_DQ22 VSS34
3 M_B_BS#2 79 BA2 DQ19 53 +3V 199 VDDSPD VSS35 150
114 40 M_B_DQ17 151
3 M_B_CS#0 S0# DQ20 M_B_DQ16 VSS36
3 M_B_CS#1 121 S1# DQ21 42 77 NC1 VSS37 155
101 50 M_B_DQ19 122 156
3 M_B_CLKP0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ23 9/15 SI for EE 125 161
3 M_B_CLKN0 CK0# DQ23 M_B_DQ25 NCTEST VSS39
3 M_B_CLKP1 102 CK1 DQ24 57 VSS40 162
104 59 M_B_DQ29 PM_EXTTS#0 198 167
3 M_B_CLKN1 CK1# DQ25 EVENT# VSS41
73 67 M_B_DQ27 2,12 DDR3_DRAMRST# 30 168
3 M_B_CKE0 CKE0 DQ26 RESET# VSS42
74 69 M_B_DQ26 172
3 M_B_CKE1 CKE1 DQ27 VSS43
115 56 M_B_DQ28 173
3 M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ24 SMDDR_VREF_DQ1_M1 R326 0_6 +SMDDR_VREF_DQ1 1 178
3 M_B_RAS# RAS# DQ29 VREF_DQ VSS45
113 68 M_B_DQ31 +SMDDR_VREF_DIMM 126 179
3 M_B_WE# DIMM1_SA0 W E# DQ30 M_B_DQ30 SMDDR_VREF_DQ1_M3 R322 VREF_CA VSS46
R170 10K_4 197 70 5 SMDDR_VREF_DQ1_M3 *0_6 184
R165 10K_4 DIMM1_SA1 SA0 DQ31 M_B_DQ36 VSS47
+3V 201 SA1 DQ32 129 VSS48 185
8,12 SMB_RUN_CLK 202 131 M_B_DQ37 2 189
SCL DQ33 M_B_DQ35 VSS1 VSS49
8,12 SMB_RUN_DAT 200 SDA DQ34 141 3 VSS2 VSS50 190
143 M_B_DQ34 8 195

(204P)
DQ35 M_B_DQ33 VSS3 VSS51
3 M_B_ODT0 116 ODT0 DQ36 130 9 VSS4 VSS52 196
120 132 M_B_DQ32 13
3 M_B_ODT1 ODT1 DQ37 VSS5
140 M_B_DQ39 14
C M_B_DM1 DQ38 M_B_DQ38 VSS6 C
11 DM0 DQ39 142 19 VSS7
28 147 M_B_DQ44 20
DM1 DQ40 M_B_DQ40 VSS8
46 149 25

(204P)
DM2 DQ41 M_B_DQ42 VSS9
63 DM3 DQ42 157 26 VSS10 VTT1 203 +0.75V_DDR_VTT
M_B_DM2 136 159 M_B_DQ43 31 204
DM4 DQ43 M_B_DQ45 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
170 148 M_B_DQ41 37 205
DM6 DQ45 M_B_DQ46 VSS13 GND
187 DM7 DQ46 158 38 VSS14 GND 206
160 M_B_DQ47 43
3 M_B_DQSP[7:0] DQ47 VSS15
M_B_DQSP0 12 163 M_B_DQ49
M_B_DQSP1 DQS0 DQ48 M_B_DQ48
29 DQS1 DQ49 165
M_B_DQSP2 47 175 M_B_DQ54 DDR3-DIMM1_H=9.2_RVS
M_B_DQSP3 DQS2 DQ50 M_B_DQ55 DDR-AS0A626-UARN-7F-204P
64 DQS3 DQ51 177
M_B_DQSP4 137 164 M_B_DQ52 DGMK4000126
M_B_DQSP5 DQS4 DQ52 M_B_DQ53 IC SOCKET DDRIII SO-DIMM(204P,H9.2,RVS)
154 DQS5 DQ53 166
M_B_DQSP6 171 174 M_B_DQ50
M_B_DQSP7 DQS6 DQ54 M_B_DQ51
3 M_B_DQSN[7:0] 188 DQS7 DQ55 176
M_B_DQSN0 10 181 M_B_DQ61
M_B_DQSN1 DQS#0 DQ56 M_B_DQ56
27 DQS#1 DQ57 183
M_B_DQSN2 45 191 M_B_DQ62 9/15 SI for EE
M_B_DQSN3 DQS#2 DQ58 M_B_DQ63
62 193
M_B_DQSN4 135
DQS#3 DQ59
180 M_B_DQ57 DDR3 Thermal Sensor
M_B_DQSN5 DQS#4 DQ60 M_B_DQ60
152 DQS#5 DQ61 182
M_B_DQSN6 169 192 M_B_DQ59 U7 C322 *0.01U/25V_4
M_B_DQSN7 DQS#6 DQ62 M_B_DQ58
186 DQS#7 DQ63 194
MBCLK2 8 1
8,29 MBCLK2 SCLK VCC +3V
DDR3-DIMM1_H=9.2_RVS MBDATA2 7 2 DDR_THERMDA
8,29 MBDATA2 SDA DXP
DDR-AS0A626-UARN-7F-204P

3
DGMK4000126 PM_EXTTS#0 6 3
B
12 PM_EXTTS#0 ALERT# DXN B
IC SOCKET DDRIII SO-DIMM(204P,H9.2,RVS) C296 2 Q13
+0.75V_DDR_VTT 12,35,38
PM_EXTTS#0_EC 4 5 *2200P/50V_4 *MMBT3904-7-F
+1.5VSUS 2,4,10,12,22,35,39 OVERT# GND
+3VPCU 7,20,28,29,31,37

1
DDR_THERMDC
+3V 2,6,7,8,9,10,12,14,17,20,21,22,23,24,25,27,28,29,30,33,38,39
+3V R141 *10K_4 *G780P81U
+5VPCU 29,31,37

Place these Caps near So-Dimm1.


VREF DQ1 M1 Solution
+1.5VSUS +0.75V_DDR_VTT +SMDDR_VREF_DIMM
+1.5VSUS
C183 1U/6.3V_4 C329 1U/6.3V_4 C310 0.1U/10V_4

C116 1U/6.3V_4 C331 1U/6.3V_4 C276 2.2U/6.3V_6


R337
C164 1U/6.3V_4 C332 1U/6.3V_4 1K/F_4

C159 1U/6.3V_4 C339 1U/6.3V_4 +SMDDR_VREF_DQ1

del M2 solution C150 10U/6.3VS_6 C326 10U/6.3V_6 C459 0.1U/10V_4


4,12,35 DDR_VTTREF R338 *0_6 SMDDR_VREF_DQ1_M1

C232 10U/6.3VS_6 C330 *10U/6.3V_6 C458 2.2U/6.3V_6 R334


1K/F_4
C209 10U/6.3VS_6

A C141 10U/6.3VS_6 +3V A

C193 10U/6.3VS_6 C324 0.1U/10V_4

C203 10U/6.3VS_6 C323 2.2U/6.3V_6

C175 *10U/6.3V_6
352-(&75
C165 10U/6.3V_8 4XDQWD&RPSXWHU,QF
C216 10U/6.3V_8
Size Document Number Rev

1%
Custom DDR3 DIMM1-RVS (9.2H) 3A
1A

Date: Saturday, September 18, 2010 Sheet 13 of 39


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5 4 3 2 1

U16A

+1.8V_DPE_VDD18 AG15
U16G

DP E/F POWER

DPE_VDD18#1
DP A/B POWER

DPA_VDD18#1 AE11 +1.8V_DPA_VDD18


14
AG16 DPE_VDD18#2 DPA_VDD18#2 AF11

2.5GT/s bit rate


AF30 AH30 C_PEG_RXN0 C480 0.1U/10V_4 +1.0V_DPE_VDD10 AG20 AF6 +1.0V_DPB_VDD10
2 PEG_TX0 PCIE_RX0P PCIE_TX0P PEG_RX0 2 DPE_VDD10#1 DPA_VDD10#1
AE31 AG31 C_PEG_RXP0 C481 0.1U/10V_4 AG21 AF7
2 PEG_TX#0 PCIE_RX0N PCIE_TX0N PEG_RX#0 2 DPE_VDD10#2 DPA_VDD10#2
D D

AE29 AG29 C_PEG_RXP1 C157 0.1U/10V_4 AG14 AE1


2 PEG_TX1 PCIE_RX1P PCIE_TX1P C_PEG_RXN1 PEG_RX1 2 DPE_VSSR#1 DPA_VSSR#1
AD28 AF28 C161 0.1U/10V_4 AH14 AE3
2 PEG_TX#1 PCIE_RX1N PCIE_TX1N PEG_RX#1 2 DPE_VSSR#2 DPA_VSSR#2
AM14 DPE_VSSR#3 DPA_VSSR#3 AG1
AM16 DPE_VSSR#4 DPA_VSSR#4 AG6
AD30 AF27 C_PEG_RXP2 C162 0.1U/10V_4 AM18 AH5
2 PEG_TX2 PCIE_RX2P PCIE_TX2P PEG_RX2 2 DPE_VSSR#5 DPA_VSSR#5
AC31 AF26 C_PEG_RXN2 C169 0.1U/10V_4
2 PEG_TX#2 PCIE_RX2N PCIE_TX2N PEG_RX#2 2
+1.0V_VGA
AC29 AD27 C_PEG_RXP3 C156 0.1U/10V_4 +1.8V_DPE_VDD18 AF16 AE13 +1.8V_DPA_VDD18
2 PEG_TX3 PCIE_RX3P PCIE_TX3P C_PEG_RXN3 PEG_RX3 2 DPF_VDD18#1 DPB_VDD18#1
AB28 AD26 C144 0.1U/10V_4 AG17 AF13 1.0V@220mA
2 PEG_TX#3 PCIE_RX3N PCIE_TX3N PEG_RX#3 2 DPF_VDD18#2 DPB_VDD18#2
L43
AB30 AC25 C_PEG_RXP4 C178 0.1U/10V_4 +1.0V_DPB_VDD10
2 PEG_TX4 PCIE_RX4P PCIE_TX4P PEG_RX4 2
AA31 AB25 C_PEG_RXN4 C187 0.1U/10V_4 +1.0V_DPE_VDD10 AF22 AF8
2 PEG_TX#4 PCIE_RX4N PCIE_TX4N PEG_RX#4 2 DPF_VDD10#1 DPB_VDD10#1

PCI EXPRESS INTERFACE


AG22 AF9 0_6
DPF_VDD10#2 DPB_VDD10#2 C486 C479 C487
AA29 Y23 C_PEG_RXP5 C170 0.1U/10V_4 0.1U/10V_4 *10U/6.3V_8 *1U/10V_4
2 PEG_TX5 PCIE_RX5P PCIE_TX5P PEG_RX5 2
Y28 Y24 C_PEG_RXN5 C176 0.1U/10V_4 R72 0_4 AF23 AF10
2 PEG_TX#5 PCIE_RX5N PCIE_TX5N PEG_RX#5 2 DPF_VSSR#1 DPB_VSSR#1
AG23 DPF_VSSR#2 DPB_VSSR#2 AG9
AM20 DPF_VSSR#3 DPB_VSSR#3 AH8
Y30 AB27 C_PEG_RXP6 C189 0.1U/10V_4 AM22 AM6
2 PEG_TX6 PCIE_RX6P PCIE_TX6P C_PEG_RXN6 PEG_RX6 2 DPF_VSSR#4 DPB_VSSR#4
W 31 AB26 C197 0.1U/10V_4 AM24 AM8
2 PEG_TX#6 PCIE_RX6N PCIE_TX6N PEG_RX#6 2 DPF_VSSR#5 DPB_VSSR#5

W 29 Y27 C_PEG_RXP7 C199 0.1U/10V_4


2 PEG_TX7 PCIE_RX7P PCIE_TX7P PEG_RX7 2
V28 Y26 C_PEG_RXN7 C207 0.1U/10V_4
2 PEG_TX#7 PCIE_RX7N PCIE_TX7N PEG_RX#7 2
R327 150/F_4 AF17 AE10 R87 150/F_4
DPEF_CALR DPAB_CALR
C V30 PCIE_RX8P PCIE_TX8P W 24 C
U31 PCIE_RX8N PCIE_TX8N W 23
+1.8V_DPE_VDD18AG18 DP PLL POWER AG8 +1.8V_DPA_VDD18
+1.8V_DPE_VDD18 DPE_PVDD DPA_PVDD +1.8V_DPA_VDD18
AF19 DPE_PVSS DPA_PVSS AG7
U29 PCIE_RX9P PCIE_TX9P V27
T28 PCIE_RX9N PCIE_TX9N U26

+1.8V_DPE_VDD18 +1.8V_DPE_VDD18AG19 AG10 +1.8V_DPA_VDD18 +1.8V_DPA_VDD18


DPF_PVDD DPB_PVDD
T30 PCIE_RX10P PCIE_TX10P U24 AF20 DPF_PVSS DPB_PVSS AG11
R31 PCIE_RX10N PCIE_TX10N U23

R29 T26 Seymour-S3


PCIE_RX11P PCIE_TX11P
P28 PCIE_RX11N PCIE_TX11N T27

P30 PCIE_RX12P PCIE_TX12P T24


N31 PCIE_RX12N PCIE_TX12N T23

N29 PCIE_RX13P PCIE_TX13P P27 (Seymour-S3: LVDS mode 240mA@1.0V)


M28 PCIE_RX13N PCIE_TX13N P26 (Seymour-S3: DP mode 220mA@1.0V)
+1.0V_DPE_VDD10 +1.8V_DPA_VDD18
L16 L23 1.8V(300mA)
M30 P24 +1.0V_DPE_VDD10 +1.8V_DPA_VDD18
PCIE_RX14P PCIE_TX14P +1.0V_VGA +1.8V_VGA
L31 PCIE_RX14N PCIE_TX14N P23
0_6 C148 C149 0_6
C121 C98 C106 0.1U/10V_4 *1U/10V_4 C152
L29 M27 0.1U/10V_4 *1U/10V_4 *10U/6.3V_6 *10U/6.3V_8
PCIE_RX15P PCIE_TX15P
B
K30 PCIE_RX15N PCIE_TX15N N26 B

(Seymour-S3: LVDS mode 300mA@1.8V)


CLOCK
(Seymour-S3: DP mode 300mA@1.8V)
CLK_PCIE_VGA AK30 L17
8 CLK_PCIE_VGA PCIE_REFCLKP
CLK_PCIE_VGA# AK32 +1.8V_DPE_VDD18 +1.8V_VGA
8 CLK_PCIE_VGA# PCIE_REFCLKN
9/6 SI for AMD.
C89 C88 C87 0_6
CALIBRATION 0.1U/10V_4 *1U/10V_4 *10U/6.3V_8
Y22 M72_PCIE_CALRP R107 1.27K/F_4
PCIE_CALRP
10K/F_4 R121 N10 AA22 M72_PCIE_CALRN R84 2K/F_4 +1.0V_VGA
PW RGOOD PCIE_CALRN

PEGX_RST# AL27 PERSTB

Seymour-S3 9/6 SI for AMD.


100MHz (+/-300ppm) input frequency,
0-0.7V single-ended swing 9/6 SI for AMD.
+3V

C76
U5 0.1U/10V_4
A MC74VHC1G08DFT2G A
5

+1.0V_VGA
15,17,35 +1.0V_VGA
2,8,24,27,29,30 PLTRST# 2
4 PEGX_RST# +1.8V_VGA
15,17,39 +1.8V_VGA
8,9 DGPU_HOLD_RST# R65 330_4 DGPU_HIN_RST# 1

R73
352-(&75
3

100K_4 4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom
1% Seymour PCIE_Interface 3A
1A

Date: Saturday, September 18, 2010 Sheet 14 of 39


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5 4 3 2 1

MEM_ID[3:0]
0000
Vendor
Samsung- E die
Type
64*16-800MHZ
Vendor P/N
K4W1G1646E-HC12 T2 AE9
U16B

Seymour-S3
DVCNTL_0/ DVPDATA_18
TXCAP_DPA3P
TXCAM_DPA3N
AF2
AF4 +1.8V_AVDD_Q +A2VDD
15
0001 Hynix- Vega die 64*16-800MHZ H5TQ1G63DFR-12C T20 L9
DVCNTL_1 / NC 1.8V(70mA) 3.3V(65mA)
0010 Hynix- Vega die 128*16-800MHZ H5TQ2G63BFR-12C T17 N9
DVCNTL_2 / NC TX0P_DPA2P
AG3
0011 Samsung- C die 128*16-800MHZ K4W2G1646C-HC12 AE8 DPA AG5 +1.8V_AVDD_Q L14 +A2VDD L10 +3V_DELAY
T3 DVDATA_12 / DVPDATA_16 TX0M_DPA2N +1.8V_VGA
0100 Micron 128*16-800MHZ MT41J128M16HA-125:D T4 AD9
DVDATA_11 / DVPDATA_20
0101 Reserved AC10 AH3 PBY160808T-121Y-N(120,2.5A) *BLM18PG181SN1D(180,1.5A)_6
T10 DVDATA_10 / DVPDATA_22 TX1P_DPA1P
0110 Hynix- Vega die 64*16-900MHZ H5TQ1G63DFR-11C T5 AD7
DVDATA_9 / DVPDATA_12 TX1M_DPA1N
AH1
0111 Samsung- E die 64*16-900MHZ K4W1G1646E-HC11 AC8 C107 C122 C97 C78 C79 C74
T6 DVDATA_8 / DVPDATA_14
1000 Samsung- G die 64*16-900MHZ K4W1G1646G-BC11 AC7 AK3 0.1U/10V_4 1U/10V_4 10U/6.3V_6 *0.1U/10V_4 *1U/10V_4 *10U/6.3V_8
T8 DVDATA_7 / DVPCNTL_0 TX2P_DPA0P
1001 Reserved T7 AB9
DVDATA_6 / DVPDATA_8 TX2M_DPA0N
AK1
1010 Hynix- Vega die 128*16-900MHZ H5TQ2G63BFR-11C T9 AB8
DVDATA_5 / DVPDATA_6
D 1011 Samsung- C die 128*16-900MHZ K4W2G1646C-HC11 +VDDR4 T12 AB7
DVDATA_4 DVPDATA_4 TXCBP_DPB3P
AK5 D
1100 Reserved Memory ID TXCBM_DPB3N
AM3
1101 Reserved R345
DVO
1110 Reserved *10K/F_4 MEM_ID3 AB4 AK6
R346 *10K/F_4 MEM_ID2 DVDATA_3 / DVPDATA_19 TX3P_DPB2P
1111 Reserved AB2
DVDATA_2 / DVPDATA_21 TX3M_DPB2N
AM5
R100 10K/F_4 MEM_ID1 Y8 DPB
R96 *10K/F_4 MEM_ID0 DVDATA_1 / DVPDATA_2
Y7 AJ7
DVDATA_0 / DVPDATA_0 TX4P_DPB1P
AH6
TX4M_DPB1N +VDDD1 +1.8V_A2VDD_Q
PBY160808T-121Y-N(120,2.5A) 1.8V(150mA DPC_VDD18) AK8 1.8V(45mA VDD1DI) 1.8V(2mA)
+1.8V_DPC_VDD18 TX5P_DPB0P
+1.8V_VGA AL7
L44 TX5M_DPB0N +VDDD1 L11 +1.8V_A2VDD_Q L20
+1.8V_VGA +1.8V_VGA
C497 C495 C494 Seymour-S3
10U/6.3V_8 1U/10V_4 0.1U/10V_4 W6 PBY160808T-121Y-N(120,2.5A) *PBY160808T-121Y-N(120,2.5A)
DPC_PVDD / DVPDATA_11
V6
DPC_PVSS / GND Seymour-S3
V4 C77 C75 C86 C130 C129 C113
GPIO15 GPIO20 DVPDATA_3/TXCCP_DPC3P
DVPCNTL_2/TXCCM_DPC3N
U5 0.1U/10V_4 1U/10V_4 10U/6.3V_6 *0.1U/10V_4 *1U/10V_4 *10U/6.3V_8
+1.8V_DPC_VDD18 AC6
DPC_VDD18#1/DVPDAT10
Seymour PWRCNTL0 PWRCNTL1 V-CORE AC5
DPC_VDD18#2/DVPDAT23 DVPDATA_7 / TX0P_DPC2P
W3 Robson-- Install
V2 Seymour- NC
DVPDATA_1 / TX0M_DPC2N
BACO mode -- install
L 0 0 0.9V DVPCNTL_MV1 / TX1P_DPC1P
Y4
AA5 W5
PBY160808T-121Y-N(120,2.5A) DPC_VDD10#1/DVPDAT15 DVPDATA_9 / TX1M_DPC1N
1.1V(110mA DPC_VDD10) AA6
DPC_VDD10#2/DVPDAT17
M 0 1 1V +1.0V_VGA +1.1V_DPC_VDD10 AA3
L22 DVPDATA_13 / TX2P_DPC0P
Y2
C120 C135 C136 DVPCNTL_1 / TX2M_DPC0N
H 1 0 1.1V (Default) 10U/6.3V_8 1U/10V_4 0.1U/10V_4 U1 AA12
DPC_VSSR#1 / DVPCLK VDDR4 / DPCD_CALR
W1
DPC_VSSR#2 / DVPDAT5
U3
DPC_VSSR#3 / GND
TBD 1 1 NA Y6
DPC_VSSR#4 / GND
Access to SCL and SDA is mandatory AA1
DPC_VSSR#5/ DVPCNTL_MV0 DPC
R348 *4.7K_4
on BACO designs for debug purposes R109 *4.7K_4
+3V_DELAY Reserve for DB debug only
T15 R1
SCL
T24 R3
SDA I2C
R328 *150/F_4
C AM26 GPU_CRT_R 22 C
GENERAL PURPOSE I/O R
AK26
GPIO0 RB R329 *150/F_4
16 GPIO0 U6
GPIO1 GPIO_0
16 GPIO1 U10 AL25 GPU_CRT_G 22
GPIO2 GPIO_1 G
16 GPIO2 T10 AJ25
GPUT_DATA GPIO_2 GB R330 *150/F_4
U8
GPUT_CLK GPIO_3_SMBDATA
U7 AH24 GPU_CRT_B 22
GPIO5 GPIO_4_SMBCLK B
16 GPIO5 T9 AG25
R356 *0_4 GPIO_5_AC_BATT BB
29 GPU_PROCHOT T8
GPIO_6 DAC1
EXT_LVDS_BLON T7 AH26 HSYNC_COM_R
GPIO_7_BLON HSYNC GPU_HSYNC_COM 22
16 GPIO8 GPIO8 P10 AJ27 VSYNC_COM_R
GPIO_8_ROMSO VSYNC GPU_VSYNC_COM 22
GPIO9 P4
+3V_DELAY 16 GPIO9 GPIO_9_ROMSI
GPIO10 P2
T18 GPIO_10_ROMSCK
GPIO11 N6 AD22 R71 499/F_4
16 GPIO11 GPIO_11 RSET
R116 *10K/F_4 GPIO24_TRSTB R123 *10K/F_4 GPIO12 N5
16 GPIO12 GPIO_12
GPIO13 N3 AG24 +1.8V_AVDD_Q +1.8V_AVDD_Q
16 GPIO13 GPIO_13 AVDD
R122 *10K/F_4 GPIO25_TDI T13 HDMI_HP2 Y9 AE22
GFX_CORE_CNTRL0 GPIO_14_HPD2 AVSSQ
39 GFX_CORE_CNTRL0 N1
R362 *10K/F_4 GPIO27_TMS T19 OSC_SPREAD GPIO_15_PWRCNTL_0 +VDDD1
M4 AE23 +VDDD1
VGA_ALERT GPIO_16_SSIN VDD1DI
29 VGA_ALERT R6 AD23
R364 *10K/F_4 GPIO28_TDO HPD3 GPIO_17_THERMAL_INT VSS1DI
T14 W10
TEMP_FAIL GPIO_18_HPD3
M2
GPIO_19_CTF Seymour-S3
R361 *10K/F_4 GPIO26_TCK 39 GFX_CORE_CNTRL1 GFX_CORE_CNTRL1 P8 AM12
BB_EN GPIO_20_PWRCNTL_1 R2 / NC
T16 P7 AK12
GPIO22 GPIO_21_BB_EN R2B / NC
16 GPIO22 N8
GPIO_23_CLKREQb GPIO_22_ROMCSB C133 22P/50V_4 EVGA-XTALI
N7 AL11
GPIO_23_CLKREQB G2 / NC
AJ11
G2B / NC

1
R113 10K/F_4 GPIO22 Y3 R336
B2 / NC
AK10
27MHZ 10M_6
For Int Clk 27Mhz
GPIO24_TRSTB L6 AL9
T21 JTAG_TRSTB B2B / NC
GPIO22(ROMCS#) GPIO25_TDI L5
T22 DAC2 is NC on Seymour

2
R360 *10K/F_4 GPIO_23_CLKREQb GPIO26_TCK JTAG_TDI
PD without external VBIOS ROM +3V_DELAY T26 L3
GPIO27_TMS JTAG_TCK C134 22P/50V_4 EVGA-XTALO
T25 L1 AH12
GPIO28_TDO JTAG_TMS C / NC
T27 K4
JTAG_TDO DAC2 Y / NC
AM10
TESTEN AF24 AJ9
T1 TESTEN COMP / NC
R112 10K/F_4 TEMP_FAIL AB13
GENERICA DAC2_VSY
B
W8
GENERICB H2SYNC
AL13 DAC2_VSY 16 9/3 SI for H/W. B
GENERICC W9 AJ13 DAC2_HSY
16 GENERICC GENERICC V2SYNC DAC2_HSY 16
W7
GENERICD
AD10
GENERICE_HPD4 R66 *0_4 +VDDD1
AD19 +VDDD1
VDD2DI / NC R98 *0_4
AC14 AC19
HPD1 VSS2DI / NC
EXT_LVDS_BLON R105 10K/F_4 +1.8V_VGA
1.8V+R6043(249R)=1.8V/3=0.6V AE20 R76 *0_4 +A2VDD
R340 499/F_4 A2VDD / NC
AE17 R88 *0_4 +1.8V_A2VDD_Q +1.8V_A2VDD_Q
R339 249/F_4 +0.6V_M92_VREFG AC16 A2VDDQ / NC
VREFG
If no contact this pin to LVDS need pull low A2VSSQ
AE19

BLM18PG471SN1D(470,1000MA) 1.8V(75mA DPLL_PVDD) C478 0.1U/10V_4 AG13 R333 *715/F_4 Seymour-S3--NC


R2SET / NC
+1.8V_VGA ROBSON--install
L13
+3V_DELAY C100 DDC/AUX
C90 C93 AE6 29 GPUT_CLK GPUT_CLK
10U/6.3V_8 1U/10V_4 0.1U/10V_4 PLL/CLOCK DDC1CLK GPUT_DATA
AE5 29 GPUT_DATA
+1.8V_DPLL_PVDD DDC1DATA
AF14
R89 DPLL_PVDD
AE14 AD2
DPLL_PVSS AUX1P
*10K/F_4 AD4
BLM18PG471SN1D(470,1000MA) AUX1N +3V_DELAY
+1.0V_VGA +1.0V_DPLL_VDDC AD14 AC11
L42 DPLL_VDDC DDC2CLK
AC13
TESTEN C474 C475 C181 DDC2DATA R102 4.7K_4
1.0V(125mA DPLL_VDDC)
10U/6.3V_8 1U/10V_4 0.1U/10V_4 R335 *0_4 EVGA-XTALI AM28 AD13
8 PCH_CLK_27M XTALIN AUX2P R106 4.7K_4
EVGA-XTALO AK28 AD11
XTALOUT AUX2N
AC22
R325 NC#2/XO_IN
AB22
NC#1/XO_IN2 DDCCLK_AUX5P
AE16 Reserve for DB debug only
Ra *10K/F_4 Seymour uninstall Ra AD16
DDCDATA_AUX5N
to meet AF24 N/C
PBY160808T-121Y-N(120,2.5A) 1.8V(20mA TSVDD) AC1 GPU_DDCCLK 22
DDC6CLK
+1.8V_VGA T4 AC3 GPU_DDCDATA 22
L41 DPLUS THERMAL DDC6DATA
T2
DMINUS
AD20
C472 C467 C468 NC/DDCCLK_AUX3P
A AC20 A
NC/DDCDATA_AUX3N
R5
10U/6.3V_8 1U/10V_4 0.1U/10V_4 +1.8V_TSVDD TS_FDO
AD17
TSVDD
AC17
TSVSS

+1.0V_VGA
14,17,35 +1.0V_VGA
+1.8V_VGA
352-(&75
14,17,39 +1.8V_VGA
Seymour-S3
+3V_DELAY
16,17 +3V_DELAY
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom
1% Seymour Main 3A
1A

Date: Saturday, September 18, 2010 Sheet 15 of 39


5 4 3 2 1

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5 4 3 2 1

AA27
AB24
U16E

PCIE_VSS#1 GND#1 A3
A30
U16F

LVDS CONTROL AB11


16
PCIE_VSS#2 GND#2 VARY_BL RECOMMENDED SETTINGS
AB32 AA13 AB12
AC24
PCIE_VSS#3
PCIE_VSS#4
GND#3 / EVDDQ#2
GND#4 AA16
DIGON CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
AC26 AB10 1 = INSTALL 10K RESISTOR
PCIE_VSS#5 GND#5
AC27 AB15 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, X = DESIGN DEPENDANT
PCIE_VSS#6 GND#6 / EVDDQ#3
AD25 AB6 NA = NOT APPLICABLE
PCIE_VSS#7 GND#7 THEY MUST NOT CONFLICT DURING RESET
D
AD32 PCIE_VSS#8 GND#8 AC9 TXCLK_UP_DPF3P AH20 D
AE27 PCIE_VSS#9 GND#9 AD6 TXCLK_UN_DPF3N AJ19
AF32 PCIE_VSS#10 GND#10 AD8
AG27 AE7 AL21 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS
PCIE_VSS#11 GND#11 TXOUT_U0P_DPF2P
AH32 PCIE_VSS#12 GND#12 AG12 TXOUT_U0N_DPF2N AK20
K28 PCIE_VSS#13 GND#13 AH10 Transmitter Power Savings Enable
K32 AH28 AH22 TX_PWRS_ENB GPIO0
L27
PCIE_VSS#14
PCIE_VSS#15
GND#14
GND#15 B10
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N AJ21
0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop) 1
M32 PCIE_VSS#16 GND#16 B12
N25 B14 AL23 PCI Express Transmitter De-emphasis Enable
PCIE_VSS#17 GND#17 TXOUT_U2P_DPF0P TX_DEEMPH_EN GPIO1
N27 B16 AK22
P25
PCIE_VSS#18
PCIE_VSS#19
GND#18
GND#19 B18
TXOUT_U2N_DPF0N 0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled (Default setting for Desktop)
1
P32 PCIE_VSS#20 GND#20 B20 TXOUT_U3P AK24
R27 B22 AJ23 Enable CLKREQ# Power Management
PCIE_VSS#21 GND#21 TXOUT_U3N BIF_GEN2_EN_A GPIO2 0 - CLKREQ# power management capability is disabled
T25 B24
T32
PCIE_VSS#22
PCIE_VSS#23
GND#22
GND#23 B26 1 - CLKREQ# power management capability is enabled 0
U25 B6 LVTMDP
PCIE_VSS#24 GND#24
U27 PCIE_VSS#25 GND#25 B8
V32 C1 AL15 RSVD GPIO8 0
PCIE_VSS#26 GND#26 TXCLK_LP_DPE3P BIF_VGA_DIS GPIO9 VGA ENABLED 0
W 25 PCIE_VSS#27 GND#27 C32 TXCLK_LN_DPE3N AK14
W 26 E28 RSVD GPIO21 0
PCIE_VSS#28 GND#28
W 27 PCIE_VSS#29 GND#29 F10 TXOUT_L0P_DPE2P AH16
Y25 F12 AJ15 BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 0
PCIE_VSS#30 GND#30 TXOUT_L0N_DPE2N
Y32 PCIE_VSS#31 GND#31 F14
F16 AL17 ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 0 0 1
GND#32 TXOUT_L1P_DPE1P
GND#33 F18 TXOUT_L1N_DPE1N AK16
F2 VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0
GND#34
GND#35 F20 TXOUT_L2P_DPE0P AH18
M6 GND#56 GND#36 F22 TXOUT_L2N_DPE0N AJ17 0
N11 F24 RSVD GENERICC 0
GND#57 GND#37 AUD[1] HSYNC AUD[1] AUD[0]
C N12 GND#58 GND#38 F26 TXOUT_L3P AL19 11 C
N13 F6 AK18 AUD[0] VSYNC 0 0 No audio function
GND#59 GND#39 TXOUT_L3N 0 1 Audio for DisplayPort and HDMI if dongle is detected
N16 F8
N18
N21
GND#60
GND#61
GND#62
GND GND#40
GND#41
GND#42
G10
G27
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI
P6 GND#63 GND#43 G31
P9 G8 Seymour-S3
GND#64 GND#44
R12 GND#65 GND#45 H14
R15 GND#66 GND#46 H17
R17 GND#67 GND#47 H2
R20 GND#68 GND#48 H20
T13 GND#69 GND#49 H6
T16 J27
T18
GND#70
GND#71
GND#50
GND#51 J31 +3V_DELAY AMD RESERVED CONFIGURATION STRAPS
T21 GND#72 GND#52 K11
T6 GND#73 GND#53 K2 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
U15 GND#74 GND#54 K22
U17 K6 15 GPIO9
GPIO9 R349 *10K/F_4 THEY MUST NOT CONFLICT DURING RESET
GND#75 GND#55
U20 GND#76 GND#85 T11
U9 R11 GPIO13 R352 *10K/F_4
GND#77 GND#86 15 GPIO13
V13 H2SYNC GENERICC
GND#78 GPIO12 R351 *10K/F_4
V16 GND#79 15 GPIO12
V18 GND#80
Y10 GPIO11 R117 10K/F_4 PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
GND#81 15 GPIO11
Y15 GND#82
Y17 GND#83 VSS_MECH#1 A32 THEY MUST NOT CONFLICT DURING RESET
Y20 GND#84 VSS_MECH#2 AM1
VSS_MECH#3 AM32
GPIO21_BB_EN
B B

Seymour-S3
+3V_DELAY

Power Up/Down Sequence Memory Aperture size


GPIO0 R344 *10K/F_4
GPIO9 GPIO13 GPIO12 GPIO11 15 GPIO0
GPIO1 R95 *10K/F_4
15 GPIO1
BIOSROM ROMIDCFG2 ROMIDCFG1 ROMIDCFG0 GPIO2 R101 *10K/F_4
15 GPIO2
0 128M 0 0 0 15 GPIO8 GPIO8 R359 *10K/F_4

+VGA_CORE VDDC R99 *10K/F_4


0 256M 0 0 1 15 GENERICC
GPIO22 R108 *10K/F_4
15 GPIO22
0 64M 0 1 0 15 GPIO5
GPIO5 R355 10K/F_4
+VGA_CORE VDDCI R331 *10K/F_4
0 32M 0 1 1 15 DAC2_VSY
R332 *10K/F_4
15 DAC2_HSY

+1.5V_VGA VDDR1 0 512M 1 0 0


A 0 1G 1 0 1 15,17 +3V_DELAY
+3V_DELAY A

+3.3V_Delay VDDR3
0 2G 1 1 0
+1.8V_VGA VDDR4 0 4G 1 1 1 352-(&75
+1.8V_VGA VDD_CT
It is a shared pin strap with CONFIG[2:0] if BIOS_ROM_EN is set to 0.
4XDQWD&RPSXWHU,QF
20ms 20ms Size Document Number Rev

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Custom
Seymour GND / LVDS/ Straps 3A
1A

Date: Saturday, September 18, 2010 Sheet 16 of 39


5 4 3 2 1
5 4 3 2 1

+5V
6,7,10,21,22,23,25,28,30,38 +5V
+3V

17
2,6,7,8,9,10,12,13,14,20,21,22,23,24,25,27,28,29,30,33,38,39 +3V
+1.0V_VGA PCIE_VDDR--PCI-E I/O power. 1.8 V ± 5%
14,15,35 +1.0V_VGA
+3V_VGA
39 +3V_VGA
+VGA_CORE
39 +VGA_CORE
U16D
+1.8V_PCIE_VDDR
MEM I/O
1.5V ( DDR3, MVDDQ = 1.5V@2.0A) PCIE 1.8V(500mA) PBY160808T-221Y-N(220,2A)
+1.5V_VGA
H13 AB23 +1.8V_PCIE_VDDR L19
VDDR1#1 PCIE_VDDR#1 +1.8V_VGA
H16 VDDR1#2 PCIE_VDDR#2 AC23
H19 VDDR1#3 PCIE_VDDR#3 AD24
C580 C259 C290 C277 C293 J10 AE24 C191 C125 C131 C109 C108 C179 C110 C139
1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 VDDR1#4 PCIE_VDDR#4 0.1U/10V_4 0.1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3VS_6
D
J23 VDDR1#5 PCIE_VDDR#5 AE25 D
J24 VDDR1#6 PCIE_VDDR#6 AE26
J9 VDDR1#7 PCIE_VDDR#7 AF25
K10 VDDR1#8 PCIE_VDDR#8 AG26
K23 VDDR1#9
K24 +1.0V_VGA
VDDR1#10
K9 VDDR1#11 PCIE_VDDC#1 L23
C278 C295 C275 L11 L24 +1.0V_PCIE_VDDC
VDDR1#12 PCIE_VDDC#2
10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 L12 VDDR1#13 PCIE_VDDC#3 L25 1.0V(2.0A)
L13 L26 +1.0V_PCIE_VDDC L26 0_8
VDDR1#14 PCIE_VDDC#4
L20 VDDR1#15 PCIE_VDDC#5 M22
L21 VDDR1#16 PCIE_VDDC#6 N22
L22 N23 C245 C235 C241 C221 C271 C273 C257 C231
+1.8V_VDD_CT VDDR1#17 PCIE_VDDC#7 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3VS_6
1.8V(110mA VDD_CT) PCIE_VDDC#8 N24
PCIE_VDDC#9 R22
L15 PBY160808T-121Y-N(120,2.5A) +1.8V_VDD_CT T22
+1.8V_VGA LEVEL PCIE_VDDC#10
PCIE_VDDC#11 U22
TRANSLATION V22
C104 C115 C196 C124 C205 PCIE_VDDC#12 +VGA_CORE
AA20 VDD_CT#1 VDDC+VDDCI
Gated 3.3V 10U/6.3VS_6 1U/10V_4 1U/10V_4 1U/10V_4 0.1U/10V_4 AA21 0.85~1.1V(15A peak )( Ripple < 87.2mV)
VDD_CT#2
60mA by AB20 VDD_CT#3 VDDC#1 AA15
+3V_DELAY AB21 CORE N15
VDDC VDD_CT#4 VDDC#2
VDDC#3 N17
+3V_VGA L18 0_6 +3V_DELAY Seymour-S3 R13 C250 C247 C249 C246 C228 C212 C211 C460
VDDC#4

POWER
R16 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3VS_6
VDDC#5
VDD_R3 --IO power for AA17 VDDR3#1 VDDC#6 R18
3.3 V pins (e.g. C188 C198 C185 C103 AA18 I/O Y21
1U/10V_4 1U/10V_4 1U/10V_4 VDDR3#2 VDDC#7
GPIO’s). 3.3 V ± 5% 10U/6.3VS_6 AB17 T12
VDDR3#3 VDDC#8
AB18 VDDR3#4 VDDC#9 T15
VDDC#10 T17
C V12 VDDR4#1 / VDDR5 VDDC#11 T20 C
1.8V(75mA MPV18) +VDDR4 Y12 U13 C230 C225 C233 C258 C224 C204 C206
BLM18PG471SN1D(470,1000MA) VDDR4#2 VDDC#12 1U/10V_4 2.2U/6.3V_4 1U/10V_4 10U/6.3V_8 1U/10V_4 1U/10V_4 1U/10V_4
U12 VDDR4#3 / VDDR5 VDDC#13 U16
MPV18 +1.8V_VGA L24 +VDDR4 U18
+1.8V_VGA VDDC#14
L29 AA11 V21
PBY160808T-121Y-N(120,2.5A) C168 C171 C208 NC#1 / VDDR4 VDDC#15
T11 Y11 DVCLK / VDDR4 VDDC#16 V15
C302 C304 1.8V(170mA VDDR4) 10U/6.3VS_6 1U/10V_4 0.1U/10V_4 V17
1U/10V_4 0.1U/10V_4 VDDC#17
V11 NC#3 / VDDR5 VDDC#18 V20
U11 NC / VDDR5 VDDC#20 Y13
Y16 C201 C217 C210 C186 C118 C195
VDDC#21 1U/10V_4 2.2U/6.3V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4
VDDC#22 Y18
1.8V(90mA SPV18) VDDC#23 /BIF_VDDC R21
VDDC#19/BIF_VDDC U21
L28 PBY160808T-121Y-N(120,2.5A) SPV18 MEM CLK
+1.8V_VGA
L17 VDDRHA
C291 C292 L16 ISOLATED
1U/10V_4 0.1U/10V_4 VSSRHA CORE I/O C70 C68 C119 C462 C461 C71
M13 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6
PLL VDDCI#1
VDDCI#2 M15
+1.8V_PCIE_VDDR AM30 M16
PCIE_PVDD VDDCI#3
VDDCI#4 M17
VDDCI#5 M18
MPV18 L8 M20 Note1.
MPV18 VDDCI#6
VDDCI#7 M21
N20 BIF_VDDC R114 *0_4
39 PX_MODE1 VDDCI#8 +VGA_CORE
1.0V_VGA(100mA SPV10) SPV18 H7
BLM18PG471SN1D(470,1000MA) SPV18
Ra
3

+1.0V_VGA_SPV10 H8
+1.0V_VGA SPV10
Q45 L46
B B
J7 SPVSS
PX_EN 2 C537 C279 C543 0.95V~1.1V(2A VDDCI)
10U/6.3VS_6 0.1U/10V_4 1U/10V_4 +VDDCI L25 0_8
+VGA_CORE
2N7002
BACK BIAS
M11 C267 C253 C248 C218 C219 C262
1

BBP#1 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6


9/9 SI for AMD M12 BBP#2

Seymour-S3
PX_MODE R783 *0_4 PX_MODE1

+5V
+5V
^ƵƉƉŽƌƚKDŽĚĞ +3V +3V
R380
Q15
AO3416
Q27
AO3416
R383 1K_4
R372 1K_4 +1.0V_VGA 1 3 3 1
*10K_4 R366 PX_EN##
PX_EN# BIF_VDDC
100K/F_4

2
3

PX_EN#
Q14 Q29
3

R369 0_4 AO3416 AO3416


39 PX_MODE
3

Q28 2 Q30 2 Q32 C287 C251 C266 C229 C213


2N7002 2N7002 +VGA_CORE 1 3 3 1 22U/6.3VS_8
2 2N7002 +3V 10U/6.3V_6 2.2U/6.3V_4
18 PX_EN 2 Q33 C534 10U/6.3V_6 2.2U/6.3V_4
A 2N7002 A
1

2
3

PX_EN##
5

R376 Q31 0.1U/10V_4


1

8,9,29,35,39 DGPU_PWROK 2
1

5.1K/F_4 2 4 BACO_EN
9/9 SI for AMD PX_MODE 1
2N7002
U17 Note1. 1. No BACO Support :BIF_VDDC shorts with VDDC (Install Ra) 352-(&75
4XDQWD&RPSXWHU,QF
3

TC7SH08FU
1

6,29 EC_PWROK 2. BACO Support: Refer to the BACO reference


Size Document Number Rev
schematics/Application note for detail about BIF_VDDC Rail

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PX_EN = 0, for Normal Operation
PX_EN = 1, for BACO MODE if BACO is Supported (Uninstall Ra) 1%
Custom
Seymour_Power_and_NC 3A
1A

Date: Saturday, September 18, 2010 Sheet 17 of 39


5 4 3 2 1
5 4 3 2 1

19
19

19
VMA_ODT0
VMA_ODT1

VMA_RAS0#
VMA_ODT0
VMA_ODT1

VMA_RAS0#
VMA_RAS1#
VMA_DQ0
VMA_DQ1
VMA_DQ2
VMA_DQ3
K27
J29
H30
H32
U16C

DQA_0
DQA_1
DQA_2
MAA_0
MAA_1
MAA_2
K17
J20
H23
G23
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
18
19 VMA_RAS1# DQA_3 MAA_3
VMA_DQ4 G29 G24 VMA_MA4
VMA_CAS0# VMA_DQ5 DQA_4 MAA_4 VMA_MA5
19 VMA_CAS0# F28 DQA_5 MAA_5 H24
19 VMA_CAS1# VMA_CAS1# VMA_DQ6 F32 J19 VMA_MA6
VMA_DQ7 DQA_6 MAA_6 VMA_MA7
F30 DQA_7 MAA_7 K19

MEMORY INTERFACE
19 VMA_WE0# VMA_WE0# VMA_DQ8 C30 J14 VMA_MA8
VMA_WE1# VMA_DQ9 DQA_8 MAA_8 VMA_MA9
D 19 VMA_WE1# F27 DQA_9 MAA_9 K14 D
VMA_DQ10 A28 J11 VMA_MA10
VMA_CS0# VMA_DQ11 DQA_10 MAA_10 VMA_MA11
19 VMA_CS0# C28 DQA_11 MAA_11 J13
VMA_DQ12 E27 H11 VMA_MA12
VMA_CS1# VMA_DQ13 DQA_12 MAA_12 VMA_BA2
19 VMA_CS1# G26 DQA_13 MAA_13/BA2 G11
VMA_DQ14 D26 J16 VMA_BA0
VMA_CKE0 VMA_DQ15 DQA_14 MAA_14/BA0 VMA_BA1
19 VMA_CKE0 F25 DQA_15 MAA_15/BA1 L15
19 VMA_CKE1 VMA_CKE1 VMA_DQ16 A25
VMA_DQ17 DQA_16 VMA_DM0
C25 DQA_17 DQMA_0 E32
19 VMA_CLK0 VMA_CLK0 VMA_DQ18 E25 E30 VMA_DM1
VMA_CLK0# VMA_DQ19 DQA_18 DQMA_1 VMA_DM2
19 VMA_CLK0# D24 DQA_19 DQMA_2 A21
VMA_DQ20 E23 C21 VMA_DM3
VMA_CLK1 VMA_DQ21 DQA_20 DQMA_3 VMA_DM4
19 VMA_CLK1 F23 DQA_21 DQMA_4 E13
19 VMA_CLK1# VMA_CLK1# VMA_DQ22 D22 D12 VMA_DM5
VMA_DQ23 DQA_22 DQMA_5 VMA_DM6
F21 DQA_23 DQMA_6 E3
VMA_WDQS[7..0] VMA_DQ24 E21 F4 VMA_DM7
19 VMA_WDQS[7..0] DQA_24 DQMA_7
VMA_DQ25 D20
VMA_RDQS[7..0] VMA_DQ26 DQA_25 VMA_RDQS0
19 VMA_RDQS[7..0] F19 DQA_26 RDQSA_0 H28
VMA_DQ27 A19 C27 VMA_RDQS1
VMA_DM[7..0] VMA_DQ28 DQA_27 RDQSA_1 VMA_RDQS2
19 VMA_DM[7..0] D18 DQA_28 RDQSA_2 A23
VMA_DQ29 F17 E19 VMA_RDQS3
VMA_DQ[63..0] VMA_DQ30 DQA_29 RDQSA_3 VMA_RDQS4
19 VMA_DQ[63..0] A17 DQA_30 RDQSA_4 E15
VMA_DQ31 C17 D10 VMA_RDQS5
VMA_MA[13..0] VMA_DQ32 DQA_31 RDQSA_5 VMA_RDQS6
19 VMA_MA[13..0] E17 DQA_32 RDQSA_6 D6
VMA_DQ33 D16 G5 VMA_RDQS7
VMA_DQ34 DQA_33 RDQSA_7
F15 DQA_34
19 VMA_BA0 VMA_BA0 VMA_DQ35 A15 H27 VMA_WDQS0
VMA_BA1 VMA_DQ36 DQA_35 W DQSA_0 VMA_WDQS1
19 VMA_BA1 D14 DQA_36 W DQSA_1 A27
VMA_BA2 VMA_DQ37 F13 C23 VMA_WDQS2
19 VMA_BA2 DQA_37 W DQSA_2
VMA_DQ38 A13 C19 VMA_WDQS3
VMA_DQ39 DQA_38 W DQSA_3 VMA_WDQS4
C C13 DQA_39 W DQSA_4 C15 C
VMA_DQ40 E11 E9 VMA_WDQS5
VMA_DQ41 DQA_40 W DQSA_5 VMA_WDQS6
A11 DQA_41 W DQSA_6 C5
VMA_DQ42 C11 H4 VMA_WDQS7
VMA_DQ43 DQA_42 W DQSA_7
F11 DQA_43
support 1Gbit VMA_DQ44 A9 L18 VMA_ODT0
VMA_DQ45 DQA_44 ODTA0 VMA_ODT1
VRAM ( 64M X 16 ) C9 DQA_45 ODTA1 K16
VMA_DQ46 F9
VMA_DQ47 DQA_46 VMA_CLK0
D8 DQA_47 CLKA0 H26
DIVIDER RESISTORS GDDR5 DDR3 VMA_DQ48 E7 H25 VMA_CLK0# DRAM_RST R171 10_4 DRAM_RST_M
DQA_48 CLKA0B DRAM_RST_M 19
VMA_DQ49 A7 R177 51/F_4
VMA_DQ50 DQA_49 VMA_CLK1
C7 DQA_50 CLKA1 G9
MVREF TO 1.8V (Ra) 40.2R 40.2R VMA_DQ51 F7 H9 VMA_CLK1#
VMA_DQ52 DQA_51 CLKA1B R174 C335
A5 DQA_52
VMA_DQ53 E5 G22 VMA_RAS0#
VMA_DQ54 DQA_53 RASA0B VMA_RAS1# 5.1K/F_4 120P/50V_4
MVREF TO GND (Rb) 100R 100R VMA_DQ55
C3 DQA_54 RASA1B G17
E1 DQA_55
VMA_DQ56 G7 G19 VMA_CAS0#
+1.5V_VGA VMA_DQ57 DQA_56 CASA0B VMA_CAS1#
G6 DQA_57 CASA1B G16
VMA_DQ58 G1
VMA_DQ59 DQA_58 VMA_CS0#
G3 DQA_59 CSA0B_0 H22 9/3 SI for H/W.
PLACE MVREFD DIVIDERS VMA_DQ60 J6 DQA_60 CSA0B_1 J22
R425 AND CAPS CLOSE TO ASIC VMA_DQ61 J1
VMA_DQ62 DQA_61 VMA_CS1#
Ra J3 DQA_62 CSA1B_0 G13
40.2/F_4 VMA_DQ63 J5 K13
DQA_63 CSA1B_1
MVREFD K26 K20 VMA_CKE0
MVREFDA CKEA0 VMA_CKE1
J26 MVREFSA CKEA1 J17
+1.5V_VGA +1.5V_VGA
R415 243/F_4 J25 G25 VMA_WE0#
B
C570 R421 R133 5.1K/F_4 MEM_CALRN0 W EA0B VMA_WE1# B
K7 NC/TESTEN#2 W EA1B H10

0.1U/10V_4
Rb 100/F_4 R431 R132 150/F_4 J8 AB16 PX_EN
Ra K25
MEM_CALRP1/DPC_CALR PX_EN
G14
PX_EN 17
40.2/F_4 R416 243/F_4 MEM_CALRP0 RSVD#2 VMA_MA13
RSVD#3 G20
DRAM_RST L10
MVREFS DRAM_RST
CLKTESTA K8
CLKTESTB CLKTESTA
L7 CLKTESTB
C583 R429
Rb Seymour-S3
0.1U/10V_4 100/F_4
C261 C514
*0.1U/10V_4 *0.1U/10V_4

R129 R353
*51.1/F_4 *51.1/F_4

route 50ohms
single-ended/100ohms diff
and keep short
A +1.5V_VGA A
17,19,22,39 +1.5V_VGA Debug only, for clock observation,
if not needed, DNI

352-(&75
4XDQWD&RPSXWHU,QF
Size Document Number Rev

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Custom
Seymour/MEM_Interface 3A
1A

Date: Saturday, September 18, 2010 Sheet 18 of 39


5 4 3 2 1
5 4 3 2 1

VMA_MA[13..0]

19
18 VMA_MA[13..0]
512MB DDR3
18 VMA_DQ[63..0]
18 VMA_DM[7..0] 18 VMA_WDQS[7..0]
18 VMA_RDQS[7..0]
U10 U19 U9 U20

VREFC_VMA1 M9 E4 VMA_DQ20 VREFC_VMA2 M9 E4 VMA_DQ27 VREFC_VMA3 M9 E4 VMA_DQ38 VREFC_VMA4 M9 E4 VMA_DQ48


VREFD_VMA1 VREFCA DQL0 VMA_DQ18 VREFD_VMA2 VREFCA DQL0 VMA_DQ31 VREFD_VMA3 VREFCA DQL0 VMA_DQ32 VREFD_VMA4 VREFCA DQL0 VMA_DQ52
H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8
F3 VMA_DQ22 F3 VMA_DQ25 F3 VMA_DQ36 F3 VMA_DQ53
VMA_MA0 DQL2 VMA_DQ17 VMA_MA0 DQL2 VMA_DQ29 VMA_MA0 DQL2 VMA_DQ34 VMA_MA0 DQL2 VMA_DQ54
N4 A0 DQL3 F9 N4 A0 DQL3 F9 N4 A0 DQL3 F9 N4 A0 DQL3 F9
VMA_MA1 P8 H4 VMA_DQ23 VMA_MA1 P8 H4 VMA_DQ30 VMA_MA1 P8 H4 VMA_DQ39 VMA_MA1 P8 H4 VMA_DQ49
VMA_MA2 A1 DQL4 VMA_DQ16 VMA_MA2 A1 DQL4 VMA_DQ28 VMA_MA2 A1 DQL4 VMA_DQ33 VMA_MA2 A1 DQL4 VMA_DQ51
P4 A2 DQL5 H9 P4 A2 DQL5 H9 P4 A2 DQL5 H9 P4 A2 DQL5 H9
VMA_MA3 N3 G3 VMA_DQ21 VMA_MA3 N3 G3 VMA_DQ24 VMA_MA3 N3 G3 VMA_DQ37 VMA_MA3 N3 G3 VMA_DQ50
VMA_MA4 A3 DQL6 VMA_DQ19 VMA_MA4 A3 DQL6 VMA_DQ26 VMA_MA4 A3 DQL6 VMA_DQ35 VMA_MA4 A3 DQL6 VMA_DQ55
P9 H8 P9 H8 P9 H8 P9 H8
VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7
P3 P3 P3 P3
D VMA_MA6 A5 VMA_MA6 A5 VMA_MA6 A5 VMA_MA6 A5 D
R9 R9 R9 R9
VMA_MA7 A6 VMA_DQ0 VMA_MA7 A6 VMA_DQ15 VMA_MA7 A6 VMA_DQ43 VMA_MA7 A6 VMA_DQ60
R3 D8 R3 D8 R3 D8 R3 D8
VMA_MA8 A7 DQU0 VMA_DQ5 VMA_MA8 A7 DQU0 VMA_DQ10 VMA_MA8 A7 DQU0 VMA_DQ44 VMA_MA8 A7 DQU0 VMA_DQ58
T9 C4 T9 C4 T9 C4 T9 C4
VMA_MA9 A8 DQU1 VMA_DQ1 VMA_MA9 A8 DQU1 VMA_DQ13 VMA_MA9 A8 DQU1 VMA_DQ40 VMA_MA9 A8 DQU1 VMA_DQ63
R4 C9 R4 C9 R4 C9 R4 C9
VMA_MA10 A9 DQU2 VMA_DQ4 VMA_MA10 A9 DQU2 VMA_DQ9 VMA_MA10 A9 DQU2 VMA_DQ47 VMA_MA10 A9 DQU2 VMA_DQ56
L8 C3 L8 C3 L8 C3 L8 C3
VMA_MA11 A10/AP DQU3 VMA_DQ2 VMA_MA11 A10/AP DQU3 VMA_DQ12 VMA_MA11 A10/AP DQU3 VMA_DQ42 VMA_MA11 A10/AP DQU3 VMA_DQ61
R8 A8 R8 A8 R8 A8 R8 A8
VMA_MA12 A11 DQU4 VMA_DQ7 VMA_MA12 A11 DQU4 VMA_DQ8 VMA_MA12 A11 DQU4 VMA_DQ45 VMA_MA12 A11 DQU4 VMA_DQ57
N8 A12/BC DQU5
A3 N8 A12/BC DQU5
A3 N8 A12/BC DQU5
A3 N8 A12/BC DQU5
A3
VMA_MA13 T4 B9 VMA_DQ3 VMA_MA13 T4 B9 VMA_DQ14 VMA_MA13 T4 B9 VMA_DQ41 VMA_MA13 T4 B9 VMA_DQ62
A13 DQU6 VMA_DQ6 A13 DQU6 VMA_DQ11 A13 DQU6 VMA_DQ46 A13 DQU6 VMA_DQ59
T8 A4 T8 A4 T8 A4 T8 A4
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M8 M8 M8 M8
A15/BA3 +1.5V_VGA A15/BA3 +1.5V_VGA A15/BA3 +1.5V_VGA A15/BA3 +1.5V_VGA

M3 B3 VMA_BA0 M3 B3 VMA_BA0 M3 B3 VMA_BA0 M3 B3


18 VMA_BA0 BA0 VDD#B3 VMA_BA1 BA0 VDD#B3 VMA_BA1 BA0 VDD#B3 VMA_BA1 BA0 VDD#B3
18 VMA_BA1 N9 BA1 VDD#D10 D10 N9 BA1 VDD#D10 D10 N9 BA1 VDD#D10 D10 N9 BA1 VDD#D10 D10
M4 G8 VMA_BA2 M4 G8 VMA_BA2 M4 G8 VMA_BA2 M4 G8
18 VMA_BA2 BA2 VDD#G8 BA2 VDD#G8 BA2 VDD#G8 BA2 VDD#G8
VDD#K3 K3 VDD#K3 K3 VDD#K3 K3 VDD#K3 K3
VDD#K9 K9 VDD#K9 K9 VDD#K9 K9 VDD#K9 K9
VDD#N2 N2 VDD#N2 N2 VDD#N2 N2 VDD#N2 N2
J8 N10 VMA_CLK0 J8 N10 J8 N10 VMA_CLK1 J8 N10
18 VMA_CLK0 CK VDD#N10 VMA_CLK0# CK VDD#N10 18 VMA_CLK1 CK VDD#N10 VMA_CLK1# CK VDD#N10
18 VMA_CLK0# K8 CK VDD#R2 R2 K8 CK VDD#R2 R2 18 VMA_CLK1# K8 CK VDD#R2 R2 K8 CK VDD#R2 R2
K10 R10 VMA_CKE0 K10 R10 K10 R10 VMA_CKE1 K10 R10
18 VMA_CKE0 CKE/CKE0 VDD#R10 +1.5V_VGA CKE/CKE0 VDD#R10 +1.5V_VGA 18 VMA_CKE1 CKE/CKE0 VDD#R10 +1.5V_VGA CKE/CKE0 VDD#R10 +1.5V_VGA

K2 A2 VMA_ODT0 K2 A2 K2 A2 VMA_ODT1 K2 A2
18 VMA_ODT0 ODT/ODT0 VDDQ#A2 VMA_CS0# ODT/ODT0 VDDQ#A2 18 VMA_ODT1 ODT/ODT0 VDDQ#A2 VMA_CS1# ODT/ODT0 VDDQ#A2
18 VMA_CS0# L3 CS /CS0 VDDQ#A9 A9 L3 CS /CS0 VDDQ#A9 A9 18 VMA_CS1# L3 CS /CS0 VDDQ#A9 A9 L3 CS /CS0 VDDQ#A9 A9
J4 C2 VMA_RAS0# J4 C2 J4 C2 VMA_RAS1# J4 C2
18 VMA_RAS0# RAS VDDQ#C2 VMA_CAS0# RAS VDDQ#C2 18 VMA_RAS1# RAS VDDQ#C2 VMA_CAS1# RAS VDDQ#C2
18 VMA_CAS0# K4 CAS VDDQ#C10 C10 K4 CAS VDDQ#C10 C10 18 VMA_CAS1# K4 CAS VDDQ#C10 C10 K4 CAS VDDQ#C10 C10
L4 D3 VMA_WE0# L4 D3 L4 D3 VMA_WE1# L4 D3
18 VMA_WE0# WE VDDQ#D3 WE VDDQ#D3 18 VMA_WE1# WE VDDQ#D3 WE VDDQ#D3
VDDQ#E10 E10 VDDQ#E10 E10 VDDQ#E10 E10 VDDQ#E10 E10
VDDQ#F2 F2 VDDQ#F2 F2 VDDQ#F2 F2 VDDQ#F2 F2
VMA_RDQS2 F4 H3 VMA_RDQS3 F4 H3 VMA_RDQS4 F4 H3 VMA_RDQS6 F4 H3
VMA_RDQS0 DQSL VDDQ#H3 VMA_RDQS1 DQSL VDDQ#H3 VMA_RDQS5 DQSL VDDQ#H3 VMA_RDQS7 DQSL VDDQ#H3
C8 DQSU VDDQ#H10 H10 C8 DQSU VDDQ#H10 H10 C8 DQSU VDDQ#H10 H10 C8 DQSU VDDQ#H10 H10
C C

VMA_DM2 E8 A10 VMA_DM3 E8 A10 VMA_DM4 E8 A10 VMA_DM6 E8 A10


VMA_DM0 DML VSS#A10 VMA_DM1 DML VSS#A10 VMA_DM5 DML VSS#A10 VMA_DM7 DML VSS#A10
D4 DMU VSS#B4 B4 D4 DMU VSS#B4 B4 D4 DMU VSS#B4 B4 D4 DMU VSS#B4 B4
VSS#E2 E2 VSS#E2 E2 VSS#E2 E2 VSS#E2 E2
VSS#G9 G9 VSS#G9 G9 VSS#G9 G9 VSS#G9 G9
VMA_WDQS2 G4 J3 VMA_WDQS3 G4 J3 VMA_WDQS4 G4 J3 VMA_WDQS6 G4 J3
VMA_WDQS0 DQSL VSS#J3 VMA_WDQS1 DQSL VSS#J3 VMA_WDQS5 DQSL VSS#J3 VMA_WDQS7 DQSL VSS#J3
B8 J9 B8 J9 B8 J9 B8 J9
DQSU VSS#J9 DQSU VSS#J9 DQSU VSS#J9 DQSU VSS#J9
M2 M2 M2 M2
VSS#M2 VSS#M2 VSS#M2 VSS#M2
M10 M10 M10 M10
VSS#M10 VSS#M10 VSS#M10 VSS#M10
P2 P2 P2 P2
VSS#P2 DRAM_RST_M T3 VSS#P2 DRAM_RST_M T3 VSS#P2 DRAM_RST_M T3 VSS#P2
18 DRAM_RST_M T3 P10 P10 P10 P10
RESET VSS#P10 RESET VSS#P10 RESET VSS#P10 RESET VSS#P10
T2 T2 T2 T2
VMA_ZQ1 VSS#T2 VMA_ZQ2 VSS#T2 VMA_ZQ3 VSS#T2 VMA_ZQ4 VSS#T2
L9 T10 L9 T10 L9 T10 L9 T10
ZQ/ZQ0 VSS#T10 ZQ/ZQ0 VSS#T10 ZQ/ZQ0 VSS#T10 ZQ/ZQ0 VSS#T10

A1 B2 A1 B2 A1 B2 A1 B2
NC VSSQ#B2 NC VSSQ#B2 NC VSSQ#B2 NC VSSQ#B2
T1 B10 T1 B10 T1 B10 T1 B10
R187 NC VSSQ#B10 R414 NC VSSQ#B10 R166 NC VSSQ#B10 R413 NC VSSQ#B10
Should be 243 A11
NC VSSQ#D2
D2 Should be 243 A11
NC VSSQ#D2
D2 Should be 243 A11
NC VSSQ#D2
D2 Should be 243 A11
NC VSSQ#D2
D2
Ohms +-1% 243/F_4 T11 D9 Ohms +-1% 243/F_4 T11 D9 Ohms +-1% 243/F_4 T11 D9 Ohms +-1% 243/F_4 T11 D9
NC VSSQ#D9 NC VSSQ#D9 NC VSSQ#D9 NC VSSQ#D9
E3 E3 E3 E3
VSSQ#E3 VSSQ#E3 VSSQ#E3 VSSQ#E3
J2 E9 J2 E9 J2 E9 J2 E9
NC/ODT1 VSSQ#E9 NC/ODT1 VSSQ#E9 NC/ODT1 VSSQ#E9 NC/ODT1 VSSQ#E9
L2 F10 L2 F10 L2 F10 L2 F10
NC/CS1 VSSQ#F10 NC/CS1 VSSQ#F10 NC/CS1 VSSQ#F10 NC/CS1 VSSQ#F10
J10 G2 J10 G2 J10 G2 J10 G2
NC/CE1 VSSQ#G2 NC/CE1 VSSQ#G2 NC/CE1 VSSQ#G2 NC/CE1 VSSQ#G2
L10 G10 L10 G10 L10 G10 L10 G10
NC/ZQ1 VSSQ#G10 NC/ZQ1 VSSQ#G10 NC/ZQ1 VSSQ#G10 NC/ZQ1 VSSQ#G10
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12 K4W1G1646E-HC12 K4W1G1646E-HC12 K4W1G1646E-HC12

+1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA


B B

R428 R160 R418 R180 R183 R175 R417 R410


4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4

VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2 VREFC_VMA3 VREFD_VMA3 VREFC_VMA4 VREFD_VMA4

R424 R162 R426 R176 R179 R178 R419 R412


4.99K/F_4 C573 4.99K/F_4 C328 4.99K/F_4 C574 4.99K/F_4 C342 4.99K/F_4 C348 4.99K/F_4 C340 4.99K/F_4 C566 4.99K/F_4 C562
0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4

VMA_CLK0 +1.5V_VGA +1.5V_VGA

R182
56.2/F_4
C565 C362 C361 C360 C359 C567 C569 C349 C555 C551 C575 C316 C578 C320 C548 C546
C357
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
VMA_CLK0_COMM

R184 0.01U/16V_4 +1.5V_VGA +1.5V_VGA QCI PN


56.2/F_4
SAMSUNG AKD5LGGT502
VMA_CLK0#
A VMA_CLK1 C571 C572 C577 C350 C354 C347 C581 C579 C319 C585 C587 C317 C351 C318 C337 C343 A
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
HYNIX AKD5LZGTW00
R167
56.2/F_4
+1.5V_VGA
C333

+1.5V_VGA
VMA_CLK1_COMM
352-(&75
17,18,22,39 +1.5V_VGA
R172 0.01U/16V_4 C586 C582 C356 C358
4XDQWD&RPSXWHU,QF
56.2/F_4 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6

www.vinafix.vn
http://laptop-motherboard-schematic.blogspot.com/ Size Document Number Rev

1%
Custom 3A
VMA_CLK1#
Seymour VRAM(DDR3 BGA96)
Date: Saturday, September 18, 2010 Sheet 19 of 39
5 4 3 2 1
1 2 3 4 5 6 7 8

LID Switch
6 TXLCLKOUT+ TXLCLKOUT+
TXLCLKOUT-
+3V

R29
R30
2.2K_4
2.2K_4
EDIDCLK
EDIDDATA
20
6
6
TXLCLKOUT-
TXLOUT0+ TXLOUT0+ RF C21 C23 SI change to AX type
6 TXLOUT0- TXLOUT0- *10P/50V_4 *10P/50V_4
6 TXLOUT1+ TXLOUT1+
6 TXLOUT1- TXLOUT1-
6 TXLOUT2+ TXLOUT2+
A A
6 TXLOUT2- TXLOUT2-

G_0
6 TXUCLKOUT- TXUCLKOUT- +3VLCD_CON
TXUCLKOUT+ 1
6 TXUCLKOUT+ 2
6 TXUOUT0+ TXUOUT0+ +3V
C72 22P/50V_4 TXUOUT0- EDIDCLK 3
6 TXUOUT0- 4
29 EMU_LID R62 0_4 PN_BLON BLON_CON 6 TXUOUT1+ TXUOUT1+ EDIDDATA
D3 RB500V-40 R68 100K/F_4 TXUOUT1- C22 TXLOUT0- 5
6 TXUOUT1- 6
6 TXUOUT2+ TXUOUT2+ 1000P/50V_4 TXLOUT0+
R59 47K_4 TXUOUT2- 7
+3VPCU 6 TXUOUT2- +3VLCD_CON 8
TXLOUT1-
LVDS_BLON R58 1K/F_4 EDIDCLK TXLOUT1+ 9
LID_EC# 28,29 6 EDIDCLK 10 G_1
D2 *RB500V-40 6 EDIDDATA EDIDDATA
TXLOUT2- 11
12
3

Close to EC 6 LVDS_BLON LVDS_BLON TXLOUT2+


DISP_ON 13
6 DISP_ON 14
DPST_PWM TXLCLKOUT-

C16*0.047U/10V_4

C17*0.047U/10V_4
8 LCD_BK 2 6 DPST_PWM 15
Q4 EMI request TXLCLKOUT+
C55 16
17

2
*DTC144EUA 100P/50V_4 TXUOUT0-
1

TXUOUT0+ 18 G_2
19

1
TXUOUT1- 20
TXUOUT1+ 21
22
TXUOUT2- 23
DISP_ON R64 100K/F_4 TXUOUT2+ 24 G_3
LVDS_BLON R53 100K/F_4 25
TXUCLKOUT- 26
9/15 SI for EE 27
TXUCLKOUT+
B
100mA +3V R51 0_4 +3V_CAM 28
B

0_4 R45 29
25 DIGITAL_D1 30
25 DIGITAL_CLK L6 DIGITAL_CLK_L