Sie sind auf Seite 1von 71

TV

SERVICE MANUAL
DOCUMENTATION TECHNIQUE
TECHNISCHE DOKUMENTATION LCD03B
DOCUMENTAZIONE TECNICA
DOCUMENTACION TECNICA

WARNING : Before servicing this chassis please read the safety recommendations.
ATTENTION : Avant toute intervention sur ce châssis, lire les recommandations de sécurité.
ACHTUNG : Vor jedem Eingriff auf diesem Chassis, die Sicherheitsvorschriften lesen.
ATTENZIONE : Prima di intervenire sullo chassis, leggere le norme di sicurezza.
IMPORTANTE : Antes de cualquier intervención, leer las recomendaciones de seguridad.

Code :357 510 10 - 0304 / 6M -LCDB03B Print.


No copying, translation, modification on other use authorized. All rights reserved worldwide. • Tous droits de reproduction, de traduction, d'adaptation et d'exécution réservés pour tous les pays. • Sämtliche Urheberrechte an diesen Texten und Zeichnungen stehen uns zu. Nachdrucke,
Vervielfältigungen - auch auszugsweise - nur mit unserer vorherigen Zustimmung zulässig. Alle Rechte vorbehalten. • I diritti di riproduzione, di traduzione, e esecuzione sono riservati per tutti i paesi. • Derechos de reproduccion, de traduccion, de adaptacion y de ejecucion reservados para todos los paises.
Do not disconnect modules when they are energized! LIST OF ABBREVIATIONS - LISTE DES ABREVIATIONS - ABKÜRZUNGEN
Repairs on power supply section are to be carried out only with isolating transformer.
LISTA DELLE ABBREVIAZIONI - LISTA DE ABREVIACIONES
Ne pas retirer les modules lorsqu' ils sont sous tension. N'effectuer les travaux de maintenance sur la partie reliée
au secteur (Switch Mode) qu'au travers d'un transformateur d'isolement.
Module nicht bei eingeschaltetem Gerät entfernen! ● AQR_ON DISABLE AQUISITION MODE REGUL. ● IR INFRARED RECEIVER
Servicearbeiten am Netzteil nur unter Verwendung eines Regeltrenntrafos durchführen. ENABLE PWM PULSE ● LED LED DISPLAY
Non scollegare le piastre quando sono alimentate! ● AUDIO_MUTE MUTES AUDIO AMPLFIERS ● LFBH LOW FEEDBACK BLUE HORIZONTAL
Per le riparazioni sulla sezione alimentatore, utilizzare un trasformatore isolatore.
● AV1_8 PIN_8 DETECTOR ● LFBV LOW FEEDBACK BLUE VERTICAL
No desconectar los módulos cuando están activados. Las reparaciones en la sección de alimentación de energía
deben ser ejecutadas solamente con un transformador de separación. ● AV_LINK AV_LINK DATAS VCR/TV ● LFGV LOW FEEDBACK GREEN VERTICAL
● AV_R_ OUT AUDIO RIGHT-OUT ● LFGH LOW FEEDBACK GREEN HORIZONTAL
● AV_L_ OUT AUDIO LEFT-OUT ● LFRV LOW FEEDBACK RED VERTICAL
Indicates critical safety components, and identical components should be used for replacement. Only then can the
operational safety be garanteed. ● AV_R_ IN AUDIO RIGHT-IN ● LFRH LOW FEEDBACK RED HORIZONTAL

Le remplacement des éléments de sécurité (repérés avec le symbole ) par des composants non homologués selon la ● AV_L_ IN AUDIO LEFT-IN ● M_RES# MAIN RESET SIGNAL
Norme CEI 65 entraine la non-conformité de l'appareil. Dans ce cas, la responsabilité du fabricant n'est plus engagée. ● AV_B BLUE SIGNAL FROM AV ● NMI NON MASKABLE INTERRUPT
Wenn Sicherheitsteile (mit dem Symbol gekennzeichnet) nicht durch Original - Ersatzteile ersetzt werden, erlischt die ● AV_G GREEN SIGNAL FROM AV ● PHI2_REF PHI2 REFERENCE SIGNAL
Haftung des Herstellers. ● AV_R RED SIGNAL FROM AV ● PKS PEAK SENSING
La sostituzione dei componenti di sicurezza (evidenziati con il segno ) con componenti non omologati secondo la ● AV_C_ IN CHROMA-IN ● PO POWER ON
norma CEI 65 comporta la non conformitá dell'apparecchio. In tal caso è "esclusa la responsabilità " del costruttore.
● AV_FB FAST BLANK SIGNAL FROM AV SCART ● PWM PULSE WIDTH MODULATION
La sustitución de elementos de seguridad (marcados con el simbolo ) por componentes no homologados segun la
● AV_Y_ IN VIDEO-IN ● RESET RESET TO MICROPROCESSOR
norma CEI 65, provoca la no conformidad del aparato. En ese caso, el fabricante cesa de ser responsable.
● BEAM_INFO BEAM CURRENT INFORMATION ● RF_CVBS DEMODULATED TERRESTRIAL TUNER SIGNAL
● BH BLUE HORIZONTAL DRIVE ● ROTATION OUTPUT OF EARTH FIELD CORRECTION STAGE
MEASUREMENT CONDITIONS - CONDITIONS DE MESURES - MESSBEDINGUNGEN ● BV BLUE VERTICAL DRIVE ● R_OUT RED SIGNAL TO VIDEO AMPLIFIER
CONDIZIONI DI MISURA - CONDICIONES DE MEDIDAS
● BLKCURR CUT OFF CURRENT ● R_TXT RED SIGNAL OUTPUT (TEXT)
RECEIVER : RECEPTEUR : EMPFÄNGER :
On UHF,input level : 1 mV, bar test pattern : En UHF, niveau d'entrée 1 mV mire de barres Bei UHF Eingangspegel 1 mV, Farbbalken : ● B_TXT BLUE SIGNAL OUTPUT (TEXT) ● RH RED HORIZONTAL DRIVE
- PAL, I standard, 100% white. - SECAM, Norm L, Blanc 100%. - PAL, Norm G, Weiss 100%.
● B_OUT BLUE SIGNAL TO VIDEO AMPLIFIER ● RV RED VERTICAL DRIVE
Via the scart socket, input level : 1 Vpp, bar test pattern : Par la prise Péritélévision, niveau d'entrée 1 Vcc, mire de barres . Über die Scartbuchse : Eingangspegel 1 Vss, Farbbalken :
● BREATHING COMPENSATE BREATHING PICTURE SIGNAL ● SIF SOUND IF OUTPUT
Colour, contrast and brightness at mid-position, sound at minimum. Couleur, contraste, lumière à mi-course, son minimum. Farbe, Kontrast, Helligkeit in der Mitte des Bereichs, Ton auf Minimum.
Programme selected : PR 01. Programme affecté PR 01. Zugeordnetes Programm PR 01. ● BSVM BEAM SCAN VELOCITY MODULATION ● SSC_V_GUARD SAFETY DATA GENERATED BY THE
DC voltages measured between the point and earth using a digital Tensions continues relevées par rapport à la masse avec un Gleichspannungen mit einem digitalen Voltmeter zur Masse gemessen. ● CMP COMPONENT INPUT SIGNALS VERTICAL AMPLIFIER TDA8177F
voltmeter. voltmètre numérique.
● CNT1_20V SAFETY SIGNAL TO INSURE A GOOD CONNECTION ● TUBE DETECTION INFORMATION FOR TUBE FORMAT
RICEVITORE : RECEPTOR :
In UHF, livello d'entrata 1 mV, monoscopio barre : En UHF, nivel de entrada 1 mV, mira de barras : BETWEEN SIGNAL BOARD AND POWER BOARD ● +USYS SYSTEM VOLTAGE
- PAL, norma G. bianco 100%. - PAL, norma G, blanco 100%.
(BV001- BL111) ● +/- UA SOUND VOLTAGE
Via SCART, livello d'entrata 1 Vpp, monoscopio barre : Por la toma Peritelevision, nivel de entrada 1 Vpp mira de barra.
Colore, Contrasto, Luminositá media, Suono minimo. Color, Contraste, luz a mitad de carrera, Sonido minimo.
● CNT2_20V SAFETY SIGNAL TO INSURE A GOOD CONNECTION ● +UVERT POSITIVE SUPPLY VERTICAL VOLTAGE
Programma selezionato PR 01. Programa afectado PR 01. BETWEEN SIGNAL BOARD AND POWER BOARD ● -UVERT NEGATIVE SUPPLY VERTICAL VOLTAGE
Tensioni continue rilevate rispetto alla massa con un voltmetro digitale. Tensiones continuas marcadas en relacion a la masa con un voltimetro digital.
(BP500- BP005) ● +UVFB POSITIVE SUPPLY VOLTAGE FOR
● CRT CATHODE RAY TUBE VERTICAL POWER STAGE
● CVBS VIDEO ● +UVIDEO VIDEO VOLTAGE FOR THE CRT BOARD
21 ENGLISH FRANÇAIS DEUTSCH ITALIANO ESPAÑOL
20 ● CVBS_TXT TEXT VIDEO ● U_OUT U TO VIDEO PART
19
18
1 AUDIO "R" AUDIO "D" AUDIO "R" AUDIO "D" AUDIO "D"
● DEFMOD MODULATION VOLTAGE GENERATED ON DFB ● V_OUT V TO VIDEO PART
17
16 2 AUDIO "R" AUDIO "D" AUDIO "R" AUDIO "D" AUDIO "D"
MODULE ● Y_OUT Y TO VIDEO PART
15
14 3 AUDIO "L" AUDIO "G" AUDIO "L" AUDIO "S" AUDIO "I"
● DEGAUSS DEGAUSS SIGNAL ● +UVFB POSITIVE SUPPLY VOLTAGE FOR VERTICAL
13
11
12 4 AUDIO AUDIO AUDIO AUDIO AUDIO
● DPC DYNAMIC PHASE COMPENSATION SIGNAL POWER STAGE
10 5 "BLUE" "BLEU" "BLAU" "BLU" "AZUL"
9
8 ● EFC EARTH FIELD CORRECTION ● 1V8_UC SUPPLIES 1V81H / 1V82H POWER SUPPLY
7 6 AUDIO "L" MONO AUDIO "G" MONO AUDIO "L" MONO AUDIO "S" MONO AUDIO "I" MONO
6 ● EHT EXTREMELY HIGH TENSION UP CONVERTER PART OF SIGNAL BOARD
5 7 "BLUE" "BLEU" "BLAU" BLU AZUL
4
AV "COMMUTAZIONE "CONMUTACION ● EHT INFO HORIZONTAL DEFLECTION PROTECTION ● 3V3_UC 3V3 POWER SUPLY UP CONVERTER PART
3
2
8 SLOW SWITCH COMMUT. LENTE UMSCHALTUNG LENTA" LENTA"
1 ● E.W_DRIVE EAST - WEST DRIVE SIGNAL OF SIGNAL BOARD
9 "GREEN" "VERT" "GRÜN" "VERDE" "VERDE"
● EW_PROT SAFETY SIGNAL FROM DIODE MODULATOR ● 5 V_A / 5V_V 5V POWER SUPPLY SIGNAL BOARD
10 AV LINK AV LINK AV LINK AV LINK AV LINK
NOTE : MAIN ... etc. identifies each ● FB DETEC FAST BLANKING DETECT ● 5V_STBYL / 5V_RP MICROPROCESSOR SUPPLY VOLTAGE
11 "GREEN" "VERT" "GRÜN" "VERDE" "VERDE"
pcb module. ● FB_TXT FAST BLANKING (TEXT) ● 5V_STBY 5V STANDBY
12 NC
NOTE : MAIN ... etc. repères des
13 "RED" "ROUGE" "ROT" "ROSSO" "ROJA"
● FW ADJ. FULL WHITE ADJUSTMENT ● 6V SUPPLIES THE 5V REGULATION AND 3V3 AND
platines constituant l'appareil.
14 NC ● G_OUT GREEN SIGNAL TO VIDEO AMPLIFIER 1V8 REGULATORS ON THE SIGNAL BOARD.
HINWEIS : MAIN ... usw. Kennzeichnung
15 "RED" "ROUGE" "ROT" "ROSSO" "ROJA" ● G_TXT GREEN SIGNAL OUTPUT (TEXT) ● 10 V SUPPLIES THE 8V_V REGULATORS ON SIGNAL
der Platinen, aus denen das "COMMUTAZIONE "CONMUTACION ● GH GREEN HORIZONTAL DRIVE BOARD
Gerät zusammengesetzt ist.
16 FAST SWITCH COMMUT. RAPIDE AUSTASTUNG
RAPIDA" RAPIDA"

17 VIDEO VIDEO VIDEO VIDEO VIDEO ● GV GREEN VERTICAL DRIVE ● 8V 8V SUPPLY SIGNAL BOARD
NOTA : MAIN ... ecc. sigla delle "COMMUTAZIONE "CONMUTACION
18 FAST SWITCH COMMUT. RAPIDE AUSTASTUNG
RAPIDA" RAPIDA" ● H_DRIVE DRIVE SIGNAL FOR HORIZONTAL DEFLECTION ● 7V_STBY 7V STANDBY
piastre dell' apparecchio.
19 VIDEO VIDEO VIDEO VIDEO VIDEO ● HEATER HEATER OUTPUT FROM THE DST TO CRT ● 33V SUPPLY VOLTAGE TUNER
NOTA : MAIN ... etc. marcas de las VIDEO ODER
20 VIDEO OR "SYNC" VIDEO SYNCHRO
SYNCHRO VIDEO O SINCRO VIDEO O SINCRO ● IIC-CL-1 I2C CLOCK BUS 1 ● 20V SUPPLY VOLTAGE HORIZONTAL DRIVER
placas que constituyen el PLUG SCREEN ABSCHIRMUNG INVOLUCRO METAL- BLINDAJE
aparato. 21 BOX BLINDAGE PRISE DES STECKERS LICO DELLA PRESA DEL ENCHUFE ● IIC-CL-2 I2C CLOCK BUS 2 AND BSVM CRT
: INPUT - ENTRÉE - EINGANG - ENTRATA - ENTRADA • : OUTPUT - SORTIE - AUSGANG - USCITA - SALIDA • : EARTH - MASSE - MASSE - MASSA - MASA ● INF_POW_FAIL POWER FAIL INFORMATION
INFORMATION - INFORMATIONS - INFORMATIONEN
INFORMAZIONE - INFORMACIONES

EN Chassis group table


1 - The electronic chassis configuration (modules) and schematic diagram page numbers.
2 - The chassis configuration.

FR Le tableau ci-dessous regroupe :


1 - L’environnement électronique de chaque chassis (modules) et le numéro de page où il est décrit.
2 - La désignation des chassis

DE Die nachstehendeTabelle umfaßt:


1 - Die elektronischen Baugruppen (Module) der Chassis varianten und die Seiten auf der sie beschrieben werden
2 - Die Chassisbezeichnung

IT La tabella qui di seguito contiene:


1 - l’ambiente elettronico di ogni telaio (moduli) e il numero di pagina nella quale è descritto.
2 - La descrizione dei telai

ES El cuadro siguiente agrupa:


1 - El entorno electrónico de cada chasis (módulos) y el número de página donde está descrito.
2 - La designación de los chasis

Chassis LCD03B
Reference Information Desassembly. Service FCB KDB Inverter DC/DC Audio Earphone Main Video
- Mode - - -- Board Board

15LCDM03B 3 6to7 10to15 “ 16to18 23to24 19to20 25 26 27to41 42to58


20LCDM03B 3 6to7 10to15 “ 16to18 23to24 21to22 25 26 27to41 42to58
20LCDB03B 3 8to9 10to15 “ 16to18 - 21to22 25 26 27to41 42to58

LCD03B
First issue 04 / 04 3
BLOCK DIAGRAM - SCHEMA SYNOPTIQUE - BLOCKSCHALTBILD - SCHEMA A BLOCCHI - ESQUEMA DE BLOQUES

15" ,20"
System Block Diagram (EU version) 8 2
Inverter pin 8 pin
pin
2
Control LCD Panel PFC/DC+DC/Audio Board pin
12 pin Board 50 pin* 40 pin** 30 pin**
Power
20 pin Connector

12 pin 50 pin* 40 pin** 30 pin** 20 pin


20" model only* 15" model only**
Keypad/IR Interface
Tuner

Flash
AD Audio Processor Scaller AT49BV8192A Tuner Module
DDC AD9883 TDA7440D PW113
EEPROM
14 pin
Main Board 60 pin golden finger
D-Sub

Audio Input Audio Line Out 60 pin 14 pin


De-Interlace Video
Chipset Decoder
Teltext
PW1230 VPC3230D Video Board SDA555XFL

SCART
S-Video
Composite L/R Audio
Video Input

LCD03B
First issue 10 / 03
BLOCK DIAGRAM - SCHEMA SYNOPTIQUE - BLOCKSCHALTBILD - SCHEMA A BLOCCHI - ESQUEMA DE BLOQUES

20" BI

5
20"BiSonic System Bolck pin
Diagram(EU version) 2
8 pin
Inverter 8
pin pin
2
10 10 5 pin
PFC/DC+DC/Audio Board
pin pin pin
IR LCD Panel
Keypad Board
Board Pow er
EarPhone Jack
12 pin 50 pin 20 pin Connector

12 pin 50 pin 20 pin

Keypad/IR Interface
Main Board Tuner
Flash
AD Audio Processor Scaller AT49BV8192A
DD C AD9883 MSP3412G PW113 Tuner Module
EEPROM
14 pin

80 pin golden finger


D-Sub

Audio Input Audio Line Out 80 pin 14 pin


De-Interlace Video
Chipset Decoder
PW1230 VPC3230D Video Board Teltext
SDA555XFL

SCART
S-Video
Composit e L/R Audio
Video Input
LCD03B
First issue 10 / 03
Disassembly
process

15LCDM03B

Page N°1
15 " LCD TV

Revision 1.0 Page N°2


15 " LCD TV

Revision 1.0 Page N°3


15 " LCD TV

Revision 1.0 Page N°4


15 " LCD TV

PC board

Slider to extract
Power board The AV module

AV module :
video and tuner boards

Revision 1.0 Page N°5


15 " LCD TV

Revision 1.0 Page N°6


15 " LCD TV

Revision 1.0 Page N°7


15 " LCD TV

Revision 1.0 Page N°8


15 " LCD TV

Revision 1.0 Page N°9


15 " LCD TV

Revision 1.0 Page N°10


15 " LCD TV

Revision 1.0 Page N°11


15 " LCD TV

Revision 1.0 Page N°12


Disassembly
process

20LCDM03B

Page N°1
20 " LCD TV

Revision 1.0 Page N°2


20 " LCD TV

Revision 1.0 Page N°3


20 " LCD TV

Revision 1.0 Page N°4


20 " LCD TV

Boards overview
Power board PC board

Inverter board

Earphone board

Power board

Control board
AV module

Revision 1.0 Page N°5


20 " LCD TV

Revision 1.0 Page N°6


20 " LCD TV

Revision 1.0 Page N°7


20 " LCD TV

AV module

Revision 1.0 Page N°8


20 " LCD TV

Revision 1.0 Page N°9


20 " LCD TV

Revision 1.0 Page N°10


20 " LCD TV

Revision 1.0 Page N°11


20 " LCD TV

Revision 1.0 Page N°12


20 " LCD TV

Revision 1.0 Page N°13


SERVICE MODE - MODE SERVICE - SERVICE-MODE - MODO SERVICIO
Overview EN

Sound
Service Mode Operation Manual
Model support: 15” 20” and 20” bi-sonic
Picture
Service Mode
Preferences 1. Press the “menu” button, and then the screen display will
appear “Overview” OSD, below as Figure Overview OSD.
Installation Then press the “info” button and ”1”, ”0”and ”3” buttons
step by step to enter Service Mode. And Figure
Figure Overview OSD Service mode will appear on the screen display.

FR IT

Mode Service
Manuale Procedura Service Mode
Modelli: 15” 20” e 20” bi-colonna
1.Presser la touche “Menu” l’ecran de selection ci-dessus apparait
Service Mode
Prenez la touche “Info”, la touche “1” puis les touches “0” et “3” pour
1. Premere il tasto “menu” per far visualizzare il menu “Sommario”,
acceder au “Mode Service”
vedi pagina OSD.
Poi premere sequenzialmente i tasti “info” , “1”, “0” e “3” per entrare in
Service mode. Il menu di Service mode verrà visualizzata sullo schermo.
Per cambiare pagina premere il tasto “Menu”.
Menu Sommario

DE ES
Manual de operación del Modo Servicio
Anleitung Service Mode Para modelos de : 15”, 20” y 20” bi-columna
Für Modelle: 15“, 20“ und 20“ bi-sonic Modo Servicio
1. Pulsar la tecla “menú”, en la pantalla se mostrará
Service Mode el menú “OVERVIEW (ÍNDICE)”, como se muestra en
1. Drücken sie die „MENU“ – Taste. Es erscheint das „Übersicht“ la figura MENU OVERVIEW (ÍNDICE).
–Menü (siehe Abbildung 1). Drücken sie dann nacheinander die Tasten A continuación, pulsar las teclas “info”, ”1”, ”0” y ”3” una tras otra
„INFO“, „1“, „0“, und „3“. Die erste Seite des Service-Modes wird para entrar en Modo Servicio y se mostrará
angezeigt (siehe Abbildung 2). la primera página del Modo Servicio en la pantalla.

NAVIGATION INSIDE THE SERVICE MODE - DEPLACEMENT DANS LE MODE SERVICE


SUCHE IN SERVICE MODE - OPZIONI NEL SERVICE MODE - BUSQUEDA EN MODO SERVICIO
REMOTE CONTROL - TELECOMMANDE - FERNBEDIENUNG
TELECOMANDO - MANDO A DISTANCIA

Changing page - Changement de page


Seitenwechsel - Cambiare Pagina - Cambio de página

- Press "Menu" button


- Appuyer sur la touche "Menu"
- Taste "Menu"
- Premere " Menu"
- Pulse "Menu"

Choosing a setting from the menu / setting e value


Choix d'un réglage dans un menu / Réglage d'une valeur
Wahl einer einstellung in einem menü / Einstellung eines wertes
Scegliere una Regolazione dal Menu / Selezione di un valore
Eleccion de un Ajuste en un menu / Ajuste de un valor

Color temp P-W P-N P-C V-N V-C


Color temp P-W P-N P-C V-N V-C
Red Drive - + - 123 -
Red Drive - + - 123 -
Green Drive - + - 123 -
Green Drive - + - 123 -
Blue Drive - + - 123 -
Blue Drive - + - 123 -

Red Offset - + - 123 -


Red Offset - + - 123 -
Green Offset - + - 123 -
Green Offset - + - 123 -
Blue Offset - + - 123 -
Blue Offset - + - 123 -
Reset To Default 190247
Reset To Default 190247
Calibration... Tuner 1D Eu 20L0BI
Calibration... Tuner 1D Eu 20L0BI
Auto Turn on on off Ver 09171I
Auto Turn on on off Ver 09171I

Naviagation up Naviagation down

- “Change“ value
- Réglage de la valeur
- Wert “änden“
> VALUE
- “Cambiare“ valore
- “Cambiar“ valor < VALUE

LCD03B
10 First issue 04 / 04
Color temp P-W P-N P-C V-N V-C
Red Drive - + - 123 -
Green Drive - + - 123 -
Blue Drive - + - 123 -
Red Offset - + - 123 -
Green Offset - + - 123 -
Blue Offset - + - 123 -
Reset To Default 190247
Calibration... Tuner 1D Eu 20L0BI
Auto Turn on on off Ver 09171I

Page1 on service mode

EN IT
1. Color Temp: P-N means “Normal” on YpbPr, V-N means “Normal” on 1. Color Temp: P-N significa “Normale” in funzione YPbPr, V-N significa
Video mode. Each item decide different gamma curve. “Normale” in funzione Video. Ogni selezione determina una differente
2. Red drive, Green drive and blue drive means gamma RGB gain. curva di risposta.
Control by scaler 2. Red Drive, Green Drive e Blue Drive significa guadagno gamma
3. Red offset, Green offset and blue offset means gamma RGB offset. RGB. Controllato da una scala.
Control by scaler 3. Red Offset, Green Offset e Blue Offset significa Offset gamma RGB.
4. Reset To Default: press OK will load all default value on User OSD Controllato da una scala.
5. Calibration: press this botton guide to calibrate A/D converter white 4. Reset To Default: premendo OK verranno caricati tutti i valori di
and black level on PC input. Also guide to calibrate A/D converter PbPr Default nel Menu Utente.
offset on YpbPr input 5. Calibration: premere questo tasto guida per calibrare il livello Bianco
6. Auto Turn On: toggle on/off control auto turn on . this function for /Nero del convertitore A/D dell’ingresso PC. Calibra anche l’offset del
factory burn-in sets . Only active on selection PC input then main power convertitore A/D PbPr dell’ingresso YpbPr.
off. 6. Auto Turn On: Commutatore controllo automatico On/Off. Funzione
7. Green lable: Tuner s/w version, time while compiling s/w, model utile per le prove di bruciatura in fabbrica. Attivando On si attiva lo
name, main s/w version. spegnimento automatico in base al segnale di ingresso PC.
7. Caselle in Verde: Versione Software Tuner, Data compilazione
Software, Nome modello, Versione software Main.

FR ES
1. Color Temp: Temperature des couleurs. 1. Color Temp: P-N significa “Normal” en modo YpbPr, V-N significa
P-N correspond à un reglage “Normal” /YpPr “Normal” en modo Video. Cada elemento tiene una curva de gamma
V-N correspond à un reglage “normal” / mode vidéo distinta.
chaque item permet de règler la courbe de gamma. 2. Red drive, Green drive y Blue drive ajustan la ganancia de la gamma
2. Red drive, Green drive and blue drive: green drive et Bleu drive RGB.
correspond aux reglages de gain 3. Red offset, Green offset y Blue offset ajustan el offset de la gamma
du gamma RVB ( controlé par le scaler). RGB.
3. Red offset, green offset et blue offset: correspond aux réglage 4. Reset To Default: Al pulsar OK se cargarán todos los valores por
d’offset du gamma RVB ( controlé par le scaler ). defecto del menú de usuario
4. Reset To Default: Appuyer sur “OK”. 5. Calibration: Pulsando este botón ayuda a calibrar el convertidor A/D
Charger les valeurs par defaut sur le menu OSD. de nivel de blanco y negro
5. Calibration: Appuyer sur “OK” pour valider. para la entrada de PC. También sirve para calibrar el offset del
Etalonne les niveaux blanc et noir du convertisseur A/D de l’ entrée PC convertidor A/D PbPr en la entrada YpbPr
Etalonne egalement les offset Pb/Pr du convertisseur A/D sur l’ entrée 6. Auto Turn On: Selecciona el control del autoencendido. Sólo activo
Ypb Pr en la selección de entrada de PC y desconexión de red.
6. Auto Turn On: Option On/OFF valide le reglage usine, 7. Casillas en verde: versión de software del sintonizador, datos de
le démarrage automatique. Seulement active sur l’entrée PC. compilación del s/w, modelo, versión del s/w principal
7. Green lable Indication dans les fenêtres vertes: Version software
tuner, temps de compilation software , nom du modele, version, version
du software principal.

DE

Seite 1 des Service-Modes


1. Color Temp: P-W steht für „Warm im YPbPr-Mode, P-N steht für
„Neutral“ bei YPbPr-Mode, P-C steht für „Kalt“ im YPbPr,-Mode, V-W
steht für „Warm“ im Video-Mode, V-N steht für „Neutral“ im Video-Mode,
V-C steht für „Kalt“ im Video-Mode. Alle Modi haben unterschiedliche
Gamma-Kennlinien.
2. Red Drive, Green Drive und Blue Drive: Einstellung der RGB-
Verstärkung
3. Red Offset, Green Offset und Blue Offset: Einstellung des RGB-
Offsets
4. Reset to Default: Durch Drücken der “OK”-Taste werden die
Benutzerdaten gelöscht und die Defaultwerte geladen.
5. Calibration: Kalibrieren der Schwarz- und Weißpegel des AD-
Wandlers des PC-Eingangs
6. Auto Turn On: Aktivierung des automatischen Einschalten des
Gerätes über den PC-Eingang. (nur für den Burn-In in der Farbrik
vorgesehen).
7. Grün markierte Felder: Software-Version Tuner, Compiler-Daten,
interne Modellbezeichnung, Version der Hauptsoftware.

LCD03B
First issue 04 / 04
OSD Position
Factory Save...
Auto Adjustment
Video Int Gain - + - 123 -
Colour - + - 123 -
Tuner Set V-Level
Tuner Get V-Level
Set First INstallation NotEnabled...
Tuner Set Factory Programs
Exit

Page2 on service mode

EN IT
8. OSD position: OSD position selection. 8. OSD position: Selezione posizione OSD.
9. Factory Save: press OK save all parameters on service mode. 9. Factory Save: Premere OK per salvare tutti i parametri del service
10. Auto Adjustment: auto adjustment new timing(position ,phase…etc). Mode.
Only active on PC mode. 10. Auto Adjustment: Auto regolazione nuove temporizzazioni
11. Video int Gain: this slider bar used to align brightness spec of Video ( posizione, fase ... etc). Attivo solo in funzione PC.
mode. Larger value bring to brighter. Control by Video decoder VPC3230 11. Video int Gain: Regola il livello di luminosità in funzione Video. Più
12. Colour: adjust color saturation. Same funct ion on User OSD. Control alto è il valore più l’immagine è luminosa. Controllo tramite il Decoder
by Video Video VPC3230.
decoder VPC3230. 12. Colour: Regola la saturazione del colore. Stessa funzione del Menu
13. Tuner Set V-Level: not used utente. Controllo tramite Video Decoder VPC3230.
14. Tuner Get V-Level: not used. 13. Tuner Set V-Level: Non utilizzato.
15. Set First Installation: “Enable” means TV will pop-up installation 14. Tuner Get V-level: Non utilizzato.
OSD at next power-on. 15. Set First Installation: “Enable” significa abilitazione, all’accensione,
16. Tuner Set Factory Programs: not used. del menu di prima installazione.
17. EXIT: exit service mode. 16. Tuner Set factory Programs: Non utilizzato.
17. EXIT: Uscita dal Service Mode.

FR ES
8. OSD position: Selection de la position OSD. 8. OSD position: Selecciona la posición del OSD.
9. Factory Save: pressez la touche “OK” pour sauvegarder tous les 9. Factory Save: Al pulsar OK, se guardan todos los parámetros del
parametres du mode service modo servicio.
10.Auto Adjustment: Actif seulement en mode PC. Auto réglage des 10. Auto Adjustment: Autoajuste de nuevo timing (posición, fase…etc).
nouveaux parametres de temps ( Position, phase..). Sólo activo en modo PC.
11. Video int Gain: Réglage de la lumière en mode vidéo. 11. Video int Gain: Esta barra deslizante se utiliza para ajustar las
Contrôle par le décodeur vidéo VP¨C 3230. especificaciones del brillo en el modo Video. Cuanto mayor sea el valor,
La position élevèe du curseur augmente la lumière. más brillante. Control por el descodificador de Video VPC3230
12. Colour: Régle la saturation de la couleur. 12. Colour: ajusta la saturación del color. Es la misma función que el
13. Tuner Set V-Level:Pas utilisé. menú de usuario. Control por el descodificador de Video VPC3230.
14. Tuner Get V-Level: Pas utilisé. 13. Tuner Set V-Level: no utilizado.
15. Set First Installation: Signifie que la TV à la prochaine mise sous 14. Tuner Get V-Level: no utilizado.
tension affichera le menu d’ installation. 15. Set First Installation: “Enable” significa que la próxima vez que se
16. Tuner Set Factory Programs: Pas utilisé. conecte el TV aparecerá el menú de primera instalación.
17. EXIT: Sortie du mode Service. 16. Tuner Set Factory Programs: no utilizado.
17. EXIT: Salida del Modo Servicio.

DE
Seite 2 des Service-Modes
8. OSD Position: Wahl der Menü-Position auf dem Bildschirm
9. Factory Save: Drücken der „OK“-Taste speichert alle Einstellungen
des Service-Modes ab.
10. Auto Adjustment: Automatischer Abgleich von Timing, Lage, Phase
usw. im PC-Mode
11. Video Int Gain: Helligkeitsvoreinsteller für den Video-Mode.
Steuerung über den Videodecoder VPC3230.
12. Colour: Einstellung der Farbsättigung; gleiche Funktion wie die
Benutzersteuerung. Steuerung über den Videodecoder VPC3230.
13. Tuner Set V-Level: nicht benutzt
14. Tuner Get V-Level: nicht benutzt
15. Set First Installation: „Enable“ lässt beim nächsten Einschalten des
Gerätes nach einer Netztrennung das Installationsmenü erscheinen.
16. Tuner Set Factory Programs: nicht benutzt.
17. Exit: Verlassen des Service-Modes.

LCD03B
First issue 04 / 04
Pw Gamma Automatic
Scale Mode
VPC AGC ON
VPC AGC OFF
HV Lock Sensitivity - + - 123 -
Color Delay - + - 123 -
Audio Gain - + - 123 -
Pb Offset - NotEnabled... + - 123 -
Pr Offset - + - 123 -
Enter PW1230 Adjustment Page...

Page3 on service mode


EN IT
18. PW Gamma: gamma curve selection. “Automatic” means pick-up 18. PW Gamma: Selezione curva gamma. In “Automatic” viene
proper gamma curve automatically when user choose Normal, Warm and selezionata automaticamente la curva gamma ideale, in base alla scelta
Cool. Value change is not recommended. utente Calda, Fredda o Neutra, nella funzione Tonalità . Si consiglia di
19. Scale Mode: screen ratio selection. non cambiare valore.
20. VPC AGC ON: turn on Video decoder “Auto gain control” (analog input 19. Scale Mode: Selezione Rapporto schermo.
level adjustment.). 20. VPC AGC ON: Attiva, nel Decoder Video, il Controllo automatico del
21. VPC AGC OFF: turn off Video decoder “Auto gain control”. Guadagno (Regolazione livello ingresso analogico).
22. HV Lock Sensitivity: Tuner HV sync sensitivity. Value change is not 21. VPC AGC OFF: Disabilita, nel Decoder Video, il Controllo Automatico
recommended. Fake programme be detected or Real programme be del Guadagno.
skipped. 22. HV Lock Sensitivity: Sensibilità Sync HV Tuner. Si consiglia di non
23. Color Delay: Color timing delay which only impact on Video mode. For cambiare valore. Livello soglia per saltare eventuali emittenti con segnale
development only. Value change is not recommended debole.
24. Audio gain: not used. 23. Color Delay: Regola il ritardo colore rispetto al segnale video.
25. Pb offset: adjust Pb offset on YpbPr input. Utilizzato per la fabbrica. Si consiglia di non cambiare valore.
26. Pr offset: adjust Pr offset on YpbPr input. 24. Audio Gain: Non utilizzato.
These 2(25,26) Functions above could be automatically done by 25. Pb offset: Regola l’offset Pb sul segnale YpbPr in ingresso.
“Calibration” page1. 26. Pr offset: Regola l’offset Pr sul segnale YpbPr in ingresso.
27. Enter PW1230 Adjustment page: Deinterlacer parameters control. For Le regolazioni menzionate nei punti 25 e 26 possono essere eseguite
development only. Value change is not recommended. automaticamente come indicato nella riga “Calibration” di pagina 1.
27. Enter PW Adjustment page: Controllo parametric Deinterlacer.
Utilizzato in fabbrica. Si consiglia di non cambiare valore.
FR
18. PW Gamma: Selection de la courbe de gamma “Automatic”
correspont à l’optention de la courbe de gamma appropriée quand ES
l’utilisateur choisit la position froide, neutre, chaude ou le rendu des
couleurs est meilleur. 18. PW Gamma: Selección de la curva de gamma. “Automatic” quiere
il est deconseillé de sélectionner la position “value Change”. decir que recuperará automáticamente la curva ideal de gamma cuando
19. Scale Mode: Selection format d’ecran. el usuario seleccione Normal, Cálido o Frío. No se recomienda cambiar
20. VPC AGC ON:Active le Vidéo décodeur. Sélectionnez “ Auto gain este valor.
Control” ( réglage du niveau d’entrée analogique ). 19. Scale Mode: selecciona la relación de pantalla.
21. VPC AGC OFF:Désactive le Vidéo décodeur. Sélectionnez “ Auto 20. VPC AGC ON: activa el "control automático de ganancia" del
gain Control”. descodificador de video (ajuste del nivel de entrada analógica).
22. HV Lock Sensitivity: Sensibilité de la Synch. HV tuner. 21. VPC AGC OFF: desactiva el "control automático de ganancia" del
Il est imperatif de ne pas modifier sa valeur. descodificador de video.
Le tuner détectera les mauvais progrmmes ou passera les programmes 22. HV Lock Sensitivity: Sensibilidad de los sincronismos HV del
corréctes. sintonizador para la búsqueda de emisoras. No se aconseja cambiar este
23. Color Delay: Réglage du “délai” couleur en mode vidéo. valor. Los canales reales pueden ser ignorados o los falsos
Réglage usine, ne pas modifier. memorizados.
24. Audio gain: Non utilisé. 23. Color Delay: Retardo del color en modo Video. No se recomienda
25. Pb offset: Réglage de l’offset Pb sur l’ entrée Ypb Pr. cambiar este valor
26. Pr offset: Réglage de l’offset Pr sur l’entée Ypb Pr. 24. Audio gain: no utilizado.
Ces 2 réglages ( 25, 26 ) sont automatiquement effectues par 25. Pb offset: ajuste del offset de Pb en la entrada YpbPr.
“calibration” de la page 1 du mode service. 26. Pr offset: ajuste del offset de Pr en la entrada YpbPr.
27. Enter PW1230 Adjustment page: Ne pas modifier. Réglage usine Estas 2 funciones anteriores (25,26) serán hechas automáticamente en
Contrôle les parametres “ Deinterlacer”. “Calibration” de la página 1.
27. Enter PW1230 Adjustment page: control de los parámetros de
Deinterlacer. No se recomienda cambiar este valor.
DE 36. V. Position: ajusta la posición Vertical sobre la entrada PC.
18. PW Gamma: Auswahl der Gamma-Kennlinie: Bei Einstellung
„Automatic“ wird automatisch die jeweilige Kennlinie gewählt, wenn der
Benutzer zwischen Warm, Neutral oder Kalt umschaltet. Eine Änderung
dieser Grundeinstellung ist nicht empfehlenswert.
19. Scale Mode: Wahl des Bildformates
20. VPC AGC ON: Aktiviert die automatische Verstärkungsregelung des
Videodecoders (Anpassung der Pegel der Analogeingänge)
21. VPC AGC OFF: Deaktiviert die automatische Verstärkungsregelung
des Videodecoders.
22. HV Lock Sensitivity: Empfindlichkeit des Synchrondetektors im
Tuner. Eine Änderung dieser Grundeinstellung ist nicht empfehlenswert,
da sonst der Sendersuchlauf falsche Ergebnisse liefern könnte.
23. Color Delay: Einstellung Farbversatz. Eine Änderung dieser
Grundeinstellung ist nicht empfehlenswert.
24 Audio Gain: nicht benutzt
25. Pb Offset: Einstellung des Pb Offsets bei YPbPr.
26. Pr Offset: Einstellung des Pr Offsets bei YPbPr.
Zu 26 und26: Der Abgleich dieser Funktionen kann automatisch mit der
Funktion „Calibration“ auf der Service-Mode Seite 1 durchgeführt werden.
27. Enter PW1230 Adjustment Page: Abgleich der Parameter des
Deinterlacers. Eine Änderung dieser Grundeinstellungen ist nicht
empfehlenswert.

LCDB03B
First issue 04 / 04
Video Format NTSC-M
Scale Mode
RGB Filter
Video Filter
Monitor Sync On Off

Reset All Nvram


Test Pattern - NotEnabled... + - 123 -
H.position - + - 123 -
V.position

Page4 on service mode

EN IT
28. Video Format: select Video standard. Force to “Auto”. 28. Video Format: Seleziona lo standard Video. Forzato su “Auto”.
29. Default Language: set default language. Same function on User 29. Default language: Seleziona la lingua. Stessa funzione del Menu
OSD. Utente.
30. RGB filter: sharpness filter of PC port of scaler. Impact on PC and 30. RGB Filter: Definizione filtro del demoltiplicatore (scaler) della porta
YpbPr input PC. Influisce sugli ingressi PC e YpbPr.
31. Video filter: sharpness filter of Video of scaler. Impact on TV Video 31. Video Filter: Definizione filtro del demoltiplicatore del segnale Video.
and YcbCr. Influisce sui segnali TV Video e YcbCr.
32. Monitor Sync: force to “On”. So that Video format can auto 32. Monitor Sync: Forzato su “On”. In questo modo può essere rilevato
detection. automaticamente il Formato Video.
33. Reset All Nvram: press “OK” will reset all parameters on service 33. Reset All Nvram: Premendo “OK” verranno resettati tutti I
mode, including color temp settings, brightness setting….etc. parametri del Service Mode, inclusi regolazione Temp. Colore,
34. Test Pattern: display test-pattern which generate by scaler. Only Regolazione Luminosità, ... ecc.).
active on PC source. 34. Test Pattern: Attivazione serie di segnali test. Attivo solo con
35. H.Position: adjust horizontal position while PC source in ingresso PC.
36. V.Position: adjust Vertical position while PC source in 35. H. Position: Regola la posizione Orizzontale in ingresso PC.
36. V. Position: Regola la posizione Verticale in ingresso PC.

FR ES
28. Video Format: selectionne le standard Vidéo. Forcer à “Auto”. 28. Video Format: selecciona el estándar de Video. “Auto” fuerza a
29. Default Language: Selectionne la langue par défaut. Même fonction modo automático.
que le réglage utilisateur. 29. Default Language: selecciona el idioma por defecto. Hace la misma
30. RGB filter: Filtre Contour RGB du Port PC. función que el menú "Usuario".
Agit sur les entrées PC et Ypb Pr. 30. RGB filter: filtro de nitidez. Válido para las entradas de PC e YpbPr.
31. Video filter: filtre contour Vidéo. Agit sur les entrées TV Vidéo et 31. Video filter: filtro de nitidez. Válido para las entradas de TV, Video e
Ye bCr. YcbCr.
32. Monitor Sync: Forcé à ON Auto détection du format Vidéo. 32. Monitor Sync: forzado a “On”. El formato de video puede ser
33. Reset All Nvram: Appui sur “OK”. autodetectado.
Reset De tous les parametres du “MODE SERVICE” incluant la 33. Reset All Nvram: pulsando “OK” se borrarán todos los parámetros
tempèrature de couleur, Contour... etc. del Modo Servicio, incluyendo los ajustes de temperatura de color,
34. Test Pattern: Affichage de la mire interne. Actif seulement en mode ajustes de brillo y contraste....., etc.
PC 34. Test Pattern: muestra unas cartas de ajuste generadas
35. H.Position: Réglage Horizontal en mode PC. internamente. Activo solamente en modo PC.
36. V.Position: Réglage Vertical en mode PC. 35. H. Position: ajusta la posición horizontal sobre la entrada PC.
36. V. Position: ajusta la posición Vertical sobre la entrada PC.

DE
28. Video Format: Auswahl des Videostandards. Sollte auf „Auto“
stehen.
29. Default Language: Auswahl der Menüsprache; gleiche Funktion wie
die Benutzersteuerung.
30. RGB Filter: Abgleich des Schärfefilters des Scalers für PC-Mode und
YPbPr.
31. Video Filter: Abgleich des Schärfefilters des Scalers für den Video-
Mode.
32. Monitor Sync: Sollte immer auf „On“ stehen damit das Videoformat
automatisch erkannt wird.
33. Reset All Nvram: Drücken der „OK“-Taste setzt alle Parameter im
Service-Mode ( auch Farbtemparatur, Helligkeit usw.) zurück.
34. Test Pattern: Zeigt ein vom Scaler erzeugtes Testmuster auf dem
Bildschirm. Nur im PC-Mode.
35. H.Position: Horizontallage für PC-Eingang.
36. V.Position: Vertikallage für PC-Eingang.

LCD03B
First issue 04 / 04
Life Time 00034:10 00033:35
Project Code EU20L03B
Panel Resolution 800 X 600
NvRam Ver. OC / 14
HXV Res / HFreq 649 X 548 15,52
HXV Total 864 X 625
Mode Num 55
DCLK 41.0 M

Factory Save... Tuner: 1D

Page5 on service mode


IT
EN
37. Life Time: The left item means the time added by stand by + TV on 37. Life Time: Il contatore a sinistra indica il tempo totale di
The right item display the time of TV-on only. funzionamento in Stand By + apparecchio acceso. Il contatore a destra
38. Project Code: as title indica il tempo totale di funzionamento ad apparecchio acceso (ON).
39. Panel Resolution: as title 38. Project code: Codice progetto.
40. NvRam Ver. Display EEPROM data veriosn. 39. Panel Resolution: Risoluzione pannello.
41. HXV Res / Hfreq: timing information. Resolution and H clock 40. NvRam Ver: Versione EEPROM.
42. HXV Total: timing information. 41. HXV res / Hfreq: Informazione timing. Risoluzione e Clock H.
43. Mode Num: timing information. Sequence of Timing chart. 42. HXV Total: Informazioni timing.
44. DCLK: timing information. Data clock 43. Mode Num: Informazioni Timing. Sequenza carta tempi.
These 4(41,42,43,and 44) items above are for development check only. 44. DCLK: Informazioni Timing. Clock Data.
45. Factory save: save factory parameters. I valori menzionati nei punti 41, 42 43 e 44 sono solo per la fabbrica
46. Green label: display tuner s/w version. 45. Factory save: Parametri memorizzati in fabbrica.
46. Casella verde: Versione software Tuner

FR ES
37. Life Time: 37. Life Time: Los números de la izquierda muestran la suma de las
-Indication de gauche: horas en stand-by + TV encendido. Los de la derecha indican sólo las
indique le temps fonctionnement total du TV: On+ Stand by. horas de TV encendido.
-Indication de droite: 38. Project Code: informativo
Indique le temps de fonctionnement du TV en On seulement. 39. Panel Resolution: informativo
38. Project Code: Info code. 40. NvRam Ver. Indica la versión de la EEPROM.
39. Panel Resolution: Resolution du panneau d’écran. 41. HXV Res / Hfreq: información de timing. Resolución y frecuencia H.
40. NvRam Ver. Version EEPROM. 42. HXV Total: información de timing.
41. HXV Res / Hfreq: Information de temps resolution et Horloge H. 43. Mode Num: información de timing.
42. HXV Total: Information de temps. 44. DCLK: información de timing. Frecuencia del reloj.
43. Mode Num: Information de temps Estas 4 funciones anteriores (41,42,43,y 44) son informativas. Sólo son
44. DCLK: Information de temps. para comprobación.
Data clock. 45. Factory save: memoriza los valores de fábrica.
Ces 4 lignes d’information sont utilisées en développement. 46. Casilla en verde: indica la versión de software del sintonizador.
45. Factory save: Sauvegarde les paramétres usine.
46. Green label: Affiche la version de Software du tuner.

DE
Seite 5 des Service-Modes
37. Life Time: Betriebsstundenzähler, links: Summe Standby-Zeit und
TV-Ein, rechts: nur TV-Ein-Zeit.
38. Project Code:
39. Panel Resolution: Auflösung der LCD-Panels
40. NvRam Ver. : Version EEPROM-Daten
41. HXV Res / HFreq:Timing-Information (Auflösung und H-Clock)
42. HXV Total: Timing Information
43. Mode Num Timing Information
44. DCLK: Timing Information Data Clock
45. Factory Save: Daten des Service-Modes speichern.
46. Grün hinterlegtes Feld: Version Tuner-Software

LCD03B
First issue 04 / 04
CONTROL SCHEMATIC DIAGRAM - SCHEMA DES CIRCUITS COMMANDES - SCHALTBILD BEDIENTEIL - SCHEMA DEI CIRCUITI COMANDI - ESQUEMA DE LOS CIRCUITOS MANDOS

CONTROL 20” BI)

12V R1 R9

10K 1K

Q1
2N3 906 + C1 5 + C1 6 12V
100U 100U
16V 16V

2
J2 R5 C1 J1
G2

R1 0 1000P
7 + C1 0 7 7
TP 1 EAR_MUTE 6

+
5 1 6
4 TP 2 A udio_R 10U 16V 8 100U 16V 1 1
3 TP 3 C9 - R1 2 39
TP 4 Audio_L 51.1KF 4.7 C2
2 2 2
1 TP 5 6 + 1000P 4 4
R6
3 C1 1 5 5
R1 1
12V

+
5
G1

- 100U 16V 3

+
3
10U 16V C3
C4 C6 39 100 0P
51.1KF 2210165091

4
TDA2 822D 0.1U R1 3 D1 D2 D3
R2

TZMC 11
U1 25V K 4.7

TZMC 5V 1

TZMC 5V 1
C7
10K 0.1U R1 4
R8 R7 25V K D4 D5 D6 47K
1K 1K + C1 2 + C1 3

TZMC 5V 1

TZMC1 1

TZMC 5V 1
100U 100U
16V 16V

D7

3
J3
1 Q2
20L1033010 2N3 904
V5S R3 1N4148

2
10K

1
+ C1 4 R1 5
10 TP 6 Q3 100U 10K
G2

10 TP 7 KP D0 2N3904
9 9 16V

2
8 TP 8 KP D1 R4
8 TP 9 KP D2 10K
7 7
6 TP 10 KP D3
6 TP 11 KP D4 V5S
5 5
4 TP 12 KP D5
4 TP 13
3 3
2 TP 14 1 SW5 3 1 SW4 3 1 SW3 3 1 SW2 3 1 SW1 3
2 TP 15 1 SW6 3
G1

1 1

2 5 4 2 5 4 2 5 4 2 5 4
2 5 4
2 5 4
20L 0BI
KEY PA D BOAR
48.M2302.A00
Optical Points
W ednesday , Septem ber 24, 2003

OP1 OP2 OP3 OP4 OP5 OP6 OP7


H1 H2 OP OP OP OP OP OP OP
HOLE -V8 HOLE -V 8

6 2 6 2

7 3 7 3
OP8 OP9 OP10 OP11 OP12 OP13 OP14
8 4 8 4 OP OP OP OP OP OP OP
9 5 9 5
1

LCD03B
First issue 10 / 03
IR PREAMPLIFIER - IR PREAMPLIFICATEUR - IR VORVERSTARKER - PREAMPLICATORE IR

( IR PREAMPLIFIER 20”BI )

IR Sensor P/N :05.04856.010 for the USA


IR Sensor P/N :05.04833.010 for the EU

U1
TSOP4856
R4 R1

33 0 33 0 V5S

VOUT
GND
4

VCC
R G LE D1 R2
GREEN/RED 330

1
2
3
2

1
V5S
+ C1 R3
4.7U 5.1K
J3
25V

2
12 TP 1
12 TP 2 L2
11 11
10 TP 3 L3
10 TP 4 L4
9 9
8 TP 5 KP D0
8 TP 6 KP D1
7 7
6 TP 7 KP D2
6 TP 8 KP D3
5 5
4 TP 9 KP D4
4 TP 10 KP D5
3 3
2 2
1 1
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

20L1033012 V5S
10
9
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
1
10

G2 G1
G2 G1

J2
20L1033010
IR BOARD

H1 H2
HO LE-V 8 HOL E-V8
6 2 6 2

7 3 7 3

8 4 8 4

9 5 9 5
1

Optical Points

OP1 OP2 OP3 OP4 OP5 OP6 OP7


OP OP OP OP OP OP OP

LCD03B
First issue 10 / 03
AUDIO CHANNEL SCHEMATIC DIAGRAM - SCHEMA DES CIRCUITS AUDIO - SCHALTBILD MEHRKANAL AUDIO - SCHEMA DEI CIRCUITI AUDIO - ESQUEMA DE LOS CIRCUITOS AUDIO

(AUDIO 20” BI)

R564
AUD_L 2K
+19V VCC 2
C506 R565
C509 C505 2K
R505 0,1µ
470µ 470µ
47K 25V 25V
25V
IEL) (ELI
R566 ZD557
2K 12V
P_GND IC501
TDA7266
R567
2K
3VCC 13
C510 C504
0.1µ R501 0,22µ
16V 26,1K 16V
4
AUD_L IN1
OUT1+ 1 PWR_GND

R503 C501
10K 1000P
50V
BD501
7
ST-BY
(0805)
(Bead)
CN601
R506 C503
47K 10µ 1
16V BD502
(EL) 9 OUT1- 2 2
S_GND S_GND
BD503 (Bead) 3
C511 S_GND S_GND
0.1µ R502 Vref (Bead) BD504
16V 26,1K 4
12 (Bead)
AUD_R IN2 OUT2+ 15
C508
0.22µ
16V
6
MUTE
R518 Q505 R504
47K 2N3904 10K

C502 OUT2- 14
R507 Q506 10009
10K 2N3904 50V 8
MUTE R516
PW-GBD
20K P_GND
C507 R517
100µ 20K
16V
(el)
S_GND
S_GND Q501 R509
2N3904 47K
+12V
VCC
ZD 501
AUD_L Q502 R511
47K 9.1V
2N3904
R508
S-GND R513 20K
20K
AUD_R
EAR_MUTE R513
47K Q503
2N3904 R510
20K
CN602=>
R515 Q504
CN602 47K 2N3904 R512
20K

R514 S_GND
20K NOTES: 1. Resistor values are in ohm, K = 1,000 ohm, M = 1,1000 000 ohm
2. All resistors are SMD 0603 5% exept where otherwise indicated
S_GND 3. All capacitors are SMD 0603 5% exept where otherwise indicated
4. Represents PCB common ground

LCD03B
First issue 10 / 03
DC - DC CONVERTER SCHEMATIC DIAGRAM - SCHEMA CONVERTISSEUR DC -DC -SCHALTBILD GLEICHSTROMUMFORMER - SCHEMA CONVERTITORE CC - CC
ESQUEMA CONVERTIDOR CC - CC

( DC/DC 15” )

POWER_ON

CN702

CN701
PWR-JACK

LCD03B
First issue 10 / 03
DC - DC CONVERTER SCHEMATIC DIAGRAM - SCHEMA CONVERTISSEUR DC -DC -SCHALTBILD GLEICHSTROMUMFORMER - SCHEMA CONVERTITORE CC - CC
ESQUEMA CONVERTIDOR CC - CC

( DC/DC 20” BI )

Q701
IRFR5305 +5VS
F702 Q707
T 2A Q703 L701 FO59435
69.420D1.111 2N3904 150µ
+19V F701
VCC
T 3A R715
1,8K C705 R729
69.43001.101 R717 220µ C707 47K
UREF

25V R723 0,1µ


C702 3 01K
220µ (EL) 25V
R702
10K R738 UREF 25V
(el) C718 D701 D703
C710 3K 0.1µ RB060L-4D RB060L-4D
R703 4700P 25V
Q704 R725
10K 50V 2N3905 Q708
330 2N3904 R731
C715 47K
1µ R724

C714
R704
20K
16V ZD702
ZD702
1K POWER_ON
R706 2MM 5,1V R730
470P 10K R714 C704
50V +5VS 20K 47µ
(NPD) 16V
2MM 6,1V
1 2 3 4 5 6 7 8
R713 Q702
47K IRFR5305
CT

SCP

1 CN+

1 CN-

1 FBK

1 DTC

1 OUT

GND
C709 Q705 L702

DTC
2N3904 47µ
25V
IC701 TL1451AC +12V
Q709
2 OUT
1 CN+

2 DTC

UREF
2 FBK
2 CN-

R719
SCP

VCC

C708 2N3906
REF

C706 R726
1.8K 0,1µ
220µ 8,66K
16 15 14 13 12 11 10 9
C716
1µ R721 25V
(el)
25V UREF
16V 0
D702 D704 R728 R732
C719 RB060L-4D RB060L-4D 2K 20K
R739 0.1µ
3K 25V
C713 R707 Q706 R727
4700p 20k R710 2N3904 1K
50V 0 12V ZD704
R733 R734
+12V 3K 47K
R705 ZD703 12V
10k
DTC

R708 R709 Q710 R735


10k 47k Q710 2N3904 47K
2N3904

Q712
2N3906 CN702 R737
20K R736
CN703 +5VS ON/OFF LCD_ON 1 2 LCD_BR 20K
BD701
(Bead)
8 R740 +12V 3 4
20K
+15V 7 PWR_GND 5 6

6 LCD_ON +5VS 7 8

C701 5 LCD_BR C717


R741
3K R742
VCC 9 10
PWR_GND
BD702 220µ 220µ
(Bead) 25V 4 ON/OFF 25V 47K 11 12

3 Q713
+19V 13 14
PWR_GND
2 +19V 2N3904 PWR_ON 15 17
CN701=>CN502 1 MUTE
(Bead) L502
18 19
S_GND
R743 L503
BD501 CN701<=CN502
20K
AUDIO_L 20 21
L501 AUDIO_R
(Bead) +19V (Bead) (Bead)
2
1
C564 C562
2 0,1µ 0,1µ 0,1µ
C501 25V 25V 25V
4 470µ 3
25V
BD502 (ELI)
(Bead)
3 NOTES: 1. Resistor values are in ohm, K = 1,000 ohm, M = 1,1000 000 ohm
2. All resistors are SMD 0603 5% exept where otherwise indicated
1 GND 3. All capacitors are SMD 0603 5% exept where otherwise indicated
4. Represents PCB common ground

LCD03B
First issue 10 / 03
INVERTER SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE INVERSEUR - SCHALTBILD INVERTER - SCHEMA INVERTER - ESQUEMA DEL INVERSOR

( INVERTER 15” / 20” )

CN601

CN603

CN604

CN602

LCD03B
First issue 10 / 03
PC BOARD INTERFACE - INTERFACE PC BOARD - SCHALTBILD PC BOARD - SCHEMA DELLA PC BOARD INTERFAZ PC BOARD

( PC BOARD 1/7)

(For EMI)
+5VS +9 V OP5 V J2
7
input output R22 R2 3 OP5 V
7
6 6
1 TP2 R85 600 OHM R1 1K
[P.6]
150 150 1 LI3
C 124 2 TP4 R86 600 OHM R3 1K
DN1 DN2 DN3 0 .1U K 2 RI 3
4 4
[P.6]

2
BAV99 BAV99 BAV9 9 U24 R 110 5 C1 C2
5

2
VCC 75 D11 D13 R6 R7
D9 RED_ IN 3 1 [P.1] 3 10 00P J10 00P J 10K 10K
*2 VR_ IN 3

TZM C5V1

TZM C5V1
TZMC5V1
+ C90 GND 221 0165031
47U MM1031XMR

1 1

1 1
4
16V
R 138 0
VR _GND
[P.1]
16 D12 D14
J3

TZM C5V1

TZM C5V1
6 OP5 V
11 1 R1 TP3 R2 47 C 121
RED_ IN
[P.2]
TP5 7 10 U 16 V C 125

+
GS DA 12 2 G1 TP6 R4 47 C 122 [P.2] 0 .1U K
GREEN_IN

2
TP7 8 10 U 16 V U25 R 115

+
13 3 B1 TP8 R5 47 C 123 [P.2] VCC 75
BLUE_ IN 3 1
TP9 10 U 16 V G REEN_I N [P.1]

+
9 *2 VY_ IN
TP1 0 14 4
TP1 1 10 R8 R9 R10 C3 C4 C5 GND
(For EMI)
GS CL 15 5 MM1031XMR J1

4
75 75 75 47P 47 P 47 P 7 7
50V J 50V J 50V J R 139 0
V Y_GND
[P.1] R87 600 OHM 6 6
D-Sub15 [P.6] Aud io_L_Lin e 1 1
R88 600 OHM
OP5 V [P.6] Audio_ R_Line 2 2
4 4
P C_5V

C 126 C1 30 C1 31 5 5
17

2
TZMC5V1

TZMC5V1
0 .1U K D15 D17

2
U26 R 120 10 00P 10 J 00P J 3 3

TZMC5V1

TZMC5V1
VCC 75
BLUE_ IN 3 1 [P.1] A udio Line out(22 10165031 )
*2 VB_IN

1 1

1 1
D6 D8 GND

TZM C5V1

TZM C5V1
MM1031XMR

4
1

D16 D18
D19 D2 0 R 140 0 [P.1]
VB_GN D

TZMC5V1

TZMC5V1
27 V 27V

2
D5 D7

R 136 1K
RGB_VS
[P.2]
R 137 1K [P.2]
RGB _HS
R14 47 J5
+5VS R13 47 [P.4] V CLK 1 2 VY _I N [P.1]
+5VS [P.4] VVS 3 4 VY_GND [P.1]
0.1U K C6 [P.4] VHS 5 6 VB_ IN [P.1]
U1
+5VS [P.4] V PEN 7 8 VB_ GND [P.1]
D1 C7 0.1U K 1 16 [P.4] VF IELD 9 10 VR _IN [P.1]
C1 + VCC [P.1]
2 V+ GND 15 11 12 V R_GND
2

DN 8 DN 9 1N4148 3 14 UART _RX [P.4] VY0 13 14 RI 1


[P.6]
C1- T1OUT [P.6]

100P J C1 36

C1 37

C1 38

C1 39
BAV99 BAV9 9 C9 C8 0.1U K UAR T_TX VY1

100P

100P

100P
4 C2 + R 1IN 13 VY[0..7 ] 15 16 LI1
3 3 P C_5V D2 5 C2- R1OUT 12 RX RX [P.4] VY2 17 18 RI 2
[P.6]
0 .1U K 6 V- T1IN 11 TXD TXD [P.4] VY3 19 20 LI2
[P.6]
[P.6]

OPE N

OPE N

OPE N
1N4148 7 10 21 22
T2OUT T2IN RI 4
U2 8 9 VY4 23 24 LI4
[P.6]
R2I N R2OUT
1

C1 0 VY5 25 26
R1 5 R1 6 8 1 C1 1 0 .1U K SP 232ECN VY6 27 28 INPUT_DET
[P.3]
VCC A0 VY7 [P.3]
29 30 AV_ DET
4.7K 4.7K 7 2 0 .1U K 31 32 TV_DET
[P.3]
WP A1 [P.4] V UV0 33 34
GS CL 6 3 V UV[0..7 ] V UV1 35 36 SDA [P.4]
SCL A2 V UV2 [P.4]
37 38 SCL
GS DA 5 4 V UV3 39 40
SDA GND [P.3]
41 42 DECOE
AT2 4C02A V UV4 43 44 PORTB3 [P.4]
V UV5 45 46 VIDEO_RESE T [P.4]
V UV6 47 48 AV_SEL [P.4]
V UV7 49 50 CVBS_ SEL
51 52 [P.4]
[P.7] +12 V 53 54 +12V [P.7]
[P.7] +5VS 55 56 +5VS [P.7]
Screw Holes [P.7] VC C 57 58 VC C [P.7]
[P.7] +9 V 59 60 +9 V [P.7]
G F60

GF-60Pin
1

5 9 5 9 5 9 5 9 5 9 Proj ct Code Model N am e


99.M127 5.001 20L03B
4 8 4 8 4 8 4 8 4 8
Tuesday, Sept ember 23, 200
3 7 3 7 3 7 3 7 3 7

2 6 2 6 2 6 2 6 2 6 Optical Points
H1 H2 H3 H4 H5 OP1 OP2 OP3 OP4 OP5 OP6 OP7
OP OP OP OP OP OP OP
HOLE-V8 HOLE- V8 HOLE- V8 HOLE-V8 HOLE- V8

OP8 OP9 OP10 OP1 1 OP1 2 OP1 3 OP1 4 OP15 OP16


OP OP OP OP OP OP OP OP OP

LCD03B
First issue 10 / 03
PC BOARD INTERFACE - INTERFACE PC BOARD - SCHALTBILD PC BOARD - SCHEMA DELLA PC BOARD INTERFAZ PC BOARD

( PC BOARD 2/7)

U2 0 74LVC1 G126 V D33


[P.4] P C_AV 1 5
OE VCC
Trace and
[P.1] 2 R1 7 3 .3K C12 .039 U
RGB_ HS A 16V K Compon ents
3 GND Y 4 R18 47 Close IC
R19 47
C13 3900 P PV DD
U2 1 74LVC1 G126 50V K
1 OE VCC 5
PV DD A VDD VD3 3
[P.1] R GB_VS 2 A
3 4 G VMI D
GND Y
C14

0.1U K

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

5
CN 1 CN2

FIL T
VD

VD
VD
PVD
PVD

VDD
VDD
GND

GND

GND

GND

GND
GND

GND
CLAMP
MIDSCV
[P.4]

VSYNC
HSYNC
COAST
22P 22P
GCOAST
41 20 GBE[0.. 7]
[P.4]
GND GND

4
42 19 A DBE0 1 8 GBE0
[P.1] C15 .047U BA IN VD B0 A DBE1
BLUE_ IN 43 BAI N B1 18 2 RN 1 7 GBE1
50V K 44 17 A DBE2 3 6 GBE2
GND B2 A DBE3 47 GBE3
45 VD B3 16 4 5
46 U3 15 A DBE4 1 8 GBE4
VD AD98 83 KST-11 0 B4 A DBE5
47 GND B5 14 2 RN 2 7 GBE5
[P.1] GREEN_I N
C16 .047U GA IN 48 13 A DBE6 3 6 GBE6
50V K GAI N B6 A DBE7 47 GBE7
49 SOGI N B7 12 4 5
C17 10 00P J SOGI N 50 11
GND VDD [P.4]
50V 51 VD I2C Add r: 0x98 GND 10 GGE[0. .7]
52 9 A DGE0 1 8 GGE0
VD G0 A DGE1
53 GND G1 8 2 RN 3 7 GGE1
[P.1] RED_ IN
C18 .047U R A IN 54 RAI N 7 A DGE2 3 6 GGE2
50V K G2 A DGE3 47 GGE3
55 A0 G3 6 4 5
[P.4] SCL_C PU
R20 0 56 5 A DGE4 1 8 GGE4
[P.4] R21 0 SCL G4 A DGE5
SDA_CP U 57 SDA G5 4 2 RN 4 7 GGE5
GVREF 58 3 A DGE6 3 6 GGE6
REF BYPASS G6 A DGE7 47 GGE7
59 VD G7 2 4 5
60 1

SOGOUT

DATACK
GND GND

1
HSOUT
VSOUT
GND

GND

GND

GND
VDD

VDD
VDD
C1 9 22P 22P

VD

R7
R6
R5
R4
R3
R2
R1
R0
CN 3 CN4
0 .1U K

8
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VCPU3 3 V D33

L1
42 OHM

AV DD

5
CN 5 CN6
22P 22P

1
C3 3 C3 4 C3 5 C36 C37 C38 C39 C40 C41 C42 [P.4]
G RE[0..7 ]

4
ADRE0 1 8 GR E0 + C20
ADRE1 2 RN 5 7 GR E1 10 U
0 .1U K 0 .1U K 0 .1U K 0.1U K 0 .1U K 0 .1U K 0 .1U K 0 .1U K 0.1U K 0 .1U K
ADRE2 3 6 GR E2 16 V

2
ADRE3 4 5 GR E3
ADRE4 1 478 GR E4
ADRE5 2 RN 6 7 GR E5
ADRE6 3 6 GR E6
ADRE7 4 5 GR E7
47 U4 A VDD
+5VS
VD3 3 P VDD 3 2
AD CK L4 30 OHM
GCL K
[P.4] L3
42 OHM VI N VOUT

GND
AD HS R24 47
GFB K
[P.4]

1
C21
C43 C44 C45 C46 C47 C48 C49 C50
AD VS R25 47 [P.4] LD1117-3.3 + C2 2
GVS

1
0 .1U K 47 U
0 .1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K
V D33 16V

2
C25 C26
C27 C23 C24 22 P 22 P
22P J 22P J OPE N OPE N
0.1U K

R26
16
A DSOG

VD3 3 U5 C28
U6 220 P V D33 1K
VCC

[P.4] MV_EN 1 5 14 50V J U7 P VDD


OE VCC CX1 R2 7 47K +5VS
1 1A RCX1 15
2 2 L6 3 2
A 1B D3 R2 8 360 [P.4] 42 OHM VI N VOUT
1Q 13 GHSSOG

GND
3 GND Y 4 3 1R 1Q 4

1
1N4148 C2 9
74LVC1G 126 9 5 LD1117-3.3 + C3 0
2A 2Q

1
10 12 D4 R2 9 1K 0.1U K 47 U
2B 2Q
1
16V

2
11 6 1N4148 + C3 1 R30
2R CX2 C32 1U 47K
RCX2 7
GND

220 P V D33 50V


2

50V J
74LV123PW R3 1 221K F
8

LCD03B
First issue 10 / 03
PC BOARD INTERFACE - INTERFACE PC BOARD - SCHALTBILD PC BOARD - SCHEMA DELLA PC BOARD INTERFAZ PC BOARD

( PC BOARD 3/7)

D[0 ..15]
VCPU 33 [P.4]
VCPU 33 +5VS

U8
C51 3 Q1
L8 42 OHM
O PEN R32 0.1U K +5VS
2N3906
26 13 2 3
[P.4] CE VPP
ROMOE n 28 OE R3 4
[P.4] ROMW En 11 37
[P.4] WE VCC
R3 3 0 12 1 2

1
RES ETn FWPn RP
14 WP

8
D0
47 BYTE D1 29
31 D1 2N3904 10K R35 CN 7
D2
A1
A2
25
24
A0 D3 33
35
D2
D3 R3 6
2N3906 1K
+5VS Q2
22P
A1 D4

1
A3 23 38 D4 1K 2N3906
2 3
A4 A2 D5 D5
22 A3 D6 40 R37 R38

3
A5 21 42 D6
A6 A4 D7 D7 [P.3] Q3
20 A5 D8 44 LED1_SE L 1

1
A7 19 30 D8 2N39 04
A8 A6 D9 D9 R40
18 A7 D1 0 32 1K 10K

2
A9 8 34 D1 0 R42
A1 0 A8 D1 1 D1 1 10 K 1K R39 470
7 A9 D1 2 36 IR RCVR_3V
A1 1 6 39 D1 2
A1 2 A1 0 D1 3 D1 3 R41 [P.4]
5 A1 1 D1 4 41
A1 3 4 43 D1 4
A1 2 D1 5 R43

3
A1 4 3 45 D1 5 10 K
A1 5 A1 3 D1 6 [P.3] Q4
2 A1 4 LED2_SE L 1
A1 6 1 2N3904
A1 7 A15 R44
48 A16 GND 46 1K

2
A1 8 17 27
A1 9 A1 7 GND 10K
16 A18
AT49BV8192A(T)
J6

TP4 7
FC En VCPU 33 L ED1 TP4 9 12
L ED2 TP5 0 11
R4 5 R46 IR RCVR TP5 1 10
C52 K PD0 TP5 3 9
K PD1 TP5 4 8
0 .1U K 7
K PD2 TP5 5

20
3.3K 3.3K U9 K PD[0..6 ] K PD3 TP5 6 6
D0 K PD0 K PD4 TP5 7 5
18 1Y 1 1A 1 2 4

VCC
D1 16 4 K PD1 K PD5 TP5 8
D2 1Y 2 1A 2 K PD2 TP4 8 3
14 1Y 3 1A 3 6 2
D3 12 8 K PD3
VCPU 33 VCPU 33 D4 1Y 4 1A 4 K PD4 1
9 2Y 1 2A 1 11
D5 7 13 K PD5
J8 D6 2Y 2 2A 2 K PD6 K PD6 TP59 20L2 021012
5 2Y 3 2A 3 15
D7 3 17 FAN _DET TP60
2Y 4 2A 4

R47

R48

R49

R50

R51

R52

R53
A2 1 60 A1
A4 2 59 A3 1 CS 0n
60

59

1G CS0 n

GND

5
A6 3 58 A5 19
A7 2G CN 8 CN9
4 57

10K

10K

10K

10K

10K

10K

10K
A9 5 56 A8 74 AHC244 22 P 22 P

10
A1 1 A10
AMP/104549

6 55

4
7 54
A1 2 8 53
A1 4 9 52 A13
10 51 A15 VCPU 33
A1 7 11 50 A16
A1 9 12 49 A18

R54

R55

R56
13 48
14 47
27 ST

15 46 C53
ROMOE n ROMWEn
16 45 0 .1U K
[P.4]

3.3K

3.3K

3.3K
D15 17 44 D7

20
D14 D6 U10
18 43
19 42 D1 3 D8 18 2 AV_DET [P.1]
1Y 1 1A 1

VCC
CONN ML 60P D1.

D5 20 41 D1 2 D9 16 4 INPUT_DET [P.1]
D4 D10 1Y 2 1A 2 R 141 OP EN [P.1]
21 40 14 1Y 3 1A 3 6 TV_DET
22 39 D1 1 D11 12 8
D3 D1 0 D12 1Y 4 1A 4
23 38 9 2Y 1 2A 1 11
D2 24 37 D13 7 13
D9 D1 D14 2Y 2 2A 2
25 36 5 2Y 3 2A 3 15
D8 26 35 D0 D15 3 17
2Y 4 2A 4
27 34
28 33 1 CS0 n
[P.4]
1G

GND
29 32 2G 19
RES ETn 30 31 NMI
74 AHC244

10
[P.4] [P.4]
2

20L 1023060
A [1..19]
[P.4] VCPU 33

C 359
U22 0.1U K
20

D0 3 D1 Q1 2 DECOE
[P.1]
VCC

D1 4 5 PWR_ ON
[P.7]
D2 D2 Q2 [P.3]
7 D3 Q3 6 LED1_SE L
D3 8 D4 Q4 9 LED2_SE L
[P.3]
D4 13 12
D5 D5 Q5
14 D6 Q6 15
D6 17 16
D7 D7 Q7
18 D8 Q8 19

[P.4] CS1 n 11 CL K
GND

R1 26 1
VCPU 33 CLR
10K 74LVC27 3
10

+ C 360
10 U
16 V

LCD03B
First issue 10 / 03
PC BOARD INTERFACE - INTERFACE PC BOARD - SCHALTBILD PC BOARD - SCHEMA DELLA PC BOARD INTERFAZ PC BOARD

( PC BOARD 4/7)

V3 3 V3 3 VCP U33

V3 3 VCP U33

R57

R58
C5 4
0.1U K U1 1

1
Q5 Q6
B SN20 B SN20 C5 5 C5 6

3.3K

3.3K
8 VCC NC 1
7 2 22P J 22P J
WP NC RES ETn
[P.1] SCL 2 3 3 2 SCL_CPU 6 3
SCL NC [P.3] L1 0 70 O HM [P.5]
5 SDA GND 4

1
Q7 Q8 10 6 DCL KR DC LK
BSN20 B SN20 DCLK DC LK
AT24C3 2A DCLKNEG 107
10 8 RVS
RVS
[P.5]
[P.1] SDA_CPU VCPU 33 DVS RH S [P.5]
SDA 2 3 3 2 DH S 109 RH S
A[1..19] 110 RD E
RD E
[P.5]
A1 DEN
A1 19 2 DR[0.. 7]
19 1 A2 [P.3] 103 DR 0
R59 A2 A3 DR0 DR 1 [P.5]
A3 19 0 DR1 102
[P.2] SCL_CP U
VCPU 33 VCPU 33 VCPU3 3 VCP U33 3.3K 18 9 A4 101 DR 2
A4 A5 DR2 DR 3
A5 18 8 DR3 100
[P.2] SDA_CP U 18 7 A6 99 DR 4
A6 DR4

R6 1

R6 2

R1 1

R1 2
R6 0 0 RPTR11 14 2 18 4 A7 98 DR 5
RES ETn TESTEN A7 A8 DR5 DR 6
13 9 RESET A8 18 3 DR6 97
R6 3 100 EXTRSTEN 28 18 2 A9 96 DR 7
EXTRSTEN A9 A1 0 DR7
A1 0 18 1 DG[ 0..7]
[P.1]

3.3K

3.3K

3.3K

3.3K
RX R64 470 RXD 67 18 0 A1 1 95 DG0
[P.1] TXD RXD A1 1 A1 2 DG0 DG1 [P.5]
TXD 68 TXD A1 2 17 9 DG1 94
[P.2] GC LK 31 R65 10K 17 8 A1 3 93 DG2
TP61 GCLK A1 3 A1 4 DG2 DG3
34 GPEN GCOAST 36 GCOAST A1 4 17 7 DG3 92
[P.2] GVS 32 SDA_CPU 20 7 17 6 A1 5 91 DG4
[P.2] GVS [P.2] SCL_CPU PORTA0 A1 5 A1 6 DG4 DG5
GH SSOG 33 GHSSOG 20 6 PORTA1 A1 6 17 5 DG5 90
[P.2] G FBK 35 TP1 2 S DA2 20 5 U1 2C 17 4 A1 7 U 12B 89 DG6
[P.2] GFBK TP1 3 S CL2 PORTA2 A1 7 A1 8 DG6 DG7
GBE[0. .7] 20 4 PORTA3 A1 8 17 3 DG7 88
GBE0 2 [P.3] IR RCVR_3V 20 3 PW113 16 4 A1 9 PW113
GBE0 IR RCVR_3V PORTA4 A1 9 DB [0..7]
GBE1 3 [P.1] TV_DET R 129 470 IN T 20 2 Misc
D[0 ..15] 83 DB0
GBE2 GBE1 R1 30 OPE N GPIOA6 PORTA5 D0 Dis play Port DB0 DB1 [P.5]
4 GBE2 20 1 PORTA6 D0 16 3 DB1 82
GBE3 5 R 128
L CD_BR
R66 10 K PWM_BR 20 0 16 2 D1 [P.3] 81 DB2
GBE4 GBE3 PORTA7 D1 D2 DB2 DB3
6 GBE4 20K D2 16 1 DB3 80
GBE5 7 [P.7] C57 16 0 D3 79 DB4
GBE6 GBE5 2.2U K D3 D4 DB4 DB5
8 GBE6 147 TRST D4 15 9 DB5 78
GBE7 9 16 V 14 6 15 8 D5 77 DB6
[P.2] GBE7 TCK D5 D6 DB6 DB7
GGE[0. .7] 14 5 TMS D6 15 7 DB7 76
GGE0 10 14 4 15 6 D7
GGE1 GGE0 TDI D7 D8 DG R0 DGR[ 0..7]
11 GGE1 14 3 TDO D8 15 5 DGR0 136
GGE2 12 15 4 D9 135 DG R1 [P.5]
GGE3 GGE2 D9 D10 DGR1 DG R2
13 GGE3 D1 0 15 3 DGR2 134
GGE4 14 [P.3] NMI 19 3 15 2 D11 133 DG R3
GGE4 NMI D1 1 DGR3
GGE5 15 GGE5 Trace and Compo nents Close IC D1 2 15 1 D12
DGR4 132 DG R4
GGE6 18 15 0 D13 131 DG R5
GGE7 GGE6 D1 3 D14 DGR5 DG R6
19 GGE7 16 9 XI D1 4 14 9 DGR6 130
[P.2] G RE[0..7] 17 0 14 8 D15 129 DG R7
GR E0 VCP U18 R6 7 1.5M XO D1 5 DGR7
20 GRE0 D GG[0..7 ]
GR E1 21 L11 L1 2 19 5 RDn TP6 2 128 DG G0
GR E2 GRE1 RD WR n TP6 3 DGG0 DG G1 [P.5]
22 GRE2 WR 19 4 DGG1 127
42 OH M

42 OH M

GR E3 23 Y1 19 6 ROM OEn
[P.3] 126 DG G2
GR E4 GRE3 X607 X608 ROMOE [P.3] DGG2 DG G3
24 GRE4 ROMW E 19 7 ROMW En DGG3 125
GR E5 25 19 8 CS 0n
CS0 n
[P.3] 122 DG G4
GR E6 GRE5 C5 8 14 .318MH Z C59 CS0 CS 1n [P.3] DGG4 DG G5
26 GRE6 CS1 19 9 CS1 n DGG5 121
GR E7 27 PW113 U1 2A C60 C61 18 P 18P 120 DG G6
GRE7 Graphics and 50V J 50V J DGG6 DG G7
PW113 DGG7 119
[P.1] VCL K 71 Vid eo Port 0.1U K 0.1U K
D GB[0..7]
[P.1] VCL K DG B0
VVS 74 VVS DGB0 118
[P.1] VH S 75 117 DG B1 [P.5]
[P.1] VH S DGB1 DG B2
VF IELD 69 VFIEL D DGB2 116
[P.1] VPE N 70 115 DG B3
VPEN VCP U33 DGB3 DG B4
VDD PA3

114
V DDPD3

U 12E DGB4
VY0 47 [P.1] V UV[0..7 ] 113 DG B5
VY1 VYUV0 V UV0 DGB5 DG B6
48 VYUV1 39 PORTC0 DGB6 112
VY2 49 V UV1 40 111 DG B7
VY3 VYUV2 V UV2 PORTC1 DGB7
50 VYUV3 41 PORTC2
10 4
12 3
14 0
17 1
20 8

16 7
16 5

13 7
18 5

VY4 51 V UV3 42
29
52
72
86

16
37
65
84

VY5 VYUV4 V UV4 PORTC3


54 VYUV5 43 PORTC4
VY6 55 V UV5 44
0
1
2
3
4
5
6
7
8

1
2
3
4
5
6

VY7 VYUV6 V UV6 PORTC5


VDDPA1_1.8V
VDDPA2_1.8V

56 45
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDDQ3
VDDQ3
VDDQ3
VDDQ3
VDDQ3
VDDQ3
VDDQ3
VDDQ3
VDDQ3

[P.1] VYUV7 V UV7 PORTC6


VY[0..7 ] 46 PORTC7
[P.7] MUTE 57 PORTB0

GPO Port
[P.7] L CD_ON 58
VC C VC C VCP U33 [P.1] PORTB1
VIDEO_RESET 59 PORTB2
U 12D PW113 Power and Ground [P.1] PORTB3 60
[P.2] PORTB3
61
VSSPA2

VSSPA1

MV_EN PORTB4
1

VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

Q9 Q1 0 [P.2] 62
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6

P C_AV PORTB5
R7 1

B SN20 B SN20 [P.1]


R6 9

63
3.3K

AV_SEL PORTB6
[P.1] 64
SCL_CPU CVBS_SE L PORTB7
SCL_5V 2 3 3 2
1
17
38
66
85

30
53
73
87
138
186

105
124
141
172

166

168
1

[P.1] Q1 1 Q1 2
3.3K

B SN20 BSN20 PW11 3

SDA_5V
2 3 3 2 SDA_CPU
VCP U33 VCP U18
[P.1]

C62 C63 C64 C65 C66 C6 7 C6 8 C69 C70 C71 C72 C73 C7 4 C75 C76

0.1U K 0.1U K 0 .1U K 0.1U K 0.1U K 0.1U K 0.1U K 0 .1U K 0.1U K 0.1U K 0 .1U K 0 .1U K 0.1U K 0.1U K 0 .1U K

LCD03B
First issue 10 / 03
PC BOARD INTERFACE - INTERFACE PC BOARD - SCHALTBILD PC BOARD - SCHEMA DELLA PC BOARD INTERFAZ PC BOARD

( PC BOARD 5/7)

[P.4] DC LK R 142 0 DCL K15


15" [P.4] DC LK
RVS
R73 600 OHM DVS TP64
[P.4]
SWAPRGB: [P.4] RH S
RD E
R74 600 OHM DH S
DE N
TP65 R 143 0 DCL K20
15" 20" J2 0
R75 600 OHM 1
Display Data Swap C7 7 C78 C7 9 V33 TP200 2
RGB Or der. 22 P 22P 22P J9 J1 0 3
O PEN OPE N OPE N 4
When SWA PBO=1,
RGB will be BGR. First Pixel 40
39
D BE0
D BE1
TP66
TP67
30
29
D BE0
D BE1
5
6
TP6 8 38 D BE2 TP69 28 D BE2 7
D GB[0..7] DG B0 1 8 DR O0 37 D BE3 TP70 27 D BE3 8
SWAPEO: [P.4] DG B1 2 7 DR O1 36 26 9
47
Display Data Swap DG B2 3 6 DR O2 DB O0 TP7 1 35 D BE4 TP72 25 D BE4 10
DG B3 4 5 DR O3 DB O1 TP7 3 34 D BE5 TP74 24 D BE5 11
Even Odd Pixels. DG B4 1 RN7 8 DR O4 DB O2 TP7 5 33 D BE6 TP76 23 D BE6 12
When SWAPEO=1, DG B5 2
47
7 DR O5 DB O3 TP7 7 32 D BE7 TP78 22 D BE7 13
DG B6 3 6 DR O6 31 21 14
the even and odd pixel DG B7 4 5 DR O7 DB O4 TP7 9 30 DG E0 TP80 20 DG E0 15
data will be swapped RN8 DB O5 TP8 1 29 DG E1 TP82 19 DG E1 16
DB O6 TP8 3 28 DG E2 TP84 18 DG E2 17
at the pac kage pins.

5
8

5
DB O7 TP8 5 27 DG E3 TP86 17 DG E3 18
DGR, DGG, DGB : First Pixels C N11 CN 10 26 16 19
DR, DG, DB : Second Pixels 22 P 22 P DG O0 TP8 7 25 DG E4 TP88 15 DG E4 20
DG O1 TP8 9 24 DG E5 TP90 14 DG E5 21

4
1

4
DG O2 TP9 1 23 DG E6 TP92 13 DG E6 22
DG O3 TP9 3 22 DG E7 TP94 12 DG E7 23
21 11 24
D GG[0..7 ] DG G0 1 8 DG O0 DG O4 TP9 5 20 DR E0 TP96 10 DR E0 25
[P.4] DG G1 2 7 DG O1 DG O5 TP9 7 19 DR E1 TP98 9 DR E1 26
20" DG G2 3 47 6 DG O2 DG O6 TP9 9 18 DR E2 TP10 0 8 DR E2 27
DG G3 4 5 DG O3 DG O7 TP101 17 DR E3 TP10 2 7 DR E3 28
SWAPRGB: DG G4 1 RN9 8 DG O4 16 6 29
DG G5 2 7 DG O5 DR O0 TP103 15 DR E4 TP10 4 5 DR E4 30
Display Data Swap DG G6 3 47 6 DG O6 DR O1 TP105 14 DR E5 TP10 6 4 DR E5 31
RGB Or der. DG G7 4 5 DG O7 DR O2 TP107 13 DR E6 TP10 8 3 DR E6 32
RN 10 DR O3 TP109 12 DR E7 TP11 0 2 DR E7 33
When SWA PBO=1, 11 1 34

5
8

5
RGB will be BGR. DR O4 TP111 10 DCL K2 0 35
C N13 CN 12 DR O5 TP112 9 36
22 P 22 P DR O6 TP113 8 CON3 0P DE N 37
SWAPEO: DR O7 TP114 7 38

4
1

4
Display D ata Swap 6 DVS 39
5 DH S 40
Even Odd Pixels. DCL K15 TP115 4 41
DGR[ 0..7]
When SW APEO=0, DG R0 1 8 DB O0 3 TP20 1 42
[P.4] DG R1 2 7 DB O1 DE N TP116 2 43
DR, DG, DB : First Pixels DG R2 3 47 6 DB O2 1 VC C 44
DG R3 4 5 DB O3 45
DG R4 1 RN 11 8 DB O4 46
DG R5 2 7 DB O5 20K 004904 0 47
DG R6 3 47 6 DB O6 48
DG R7 4 5 DB O7 49
RN 12 50

5
8

5
20L2 04305 0
C N15 CN 14
22 P 22 P
1

4
1

Second Pixel
DB[0 ..7] DB0 1 8 DR E0
[P.4] DB1 2 7 DR E1
DB2 3 47 6 DR E2
DB3 4 5 DR E3
DB4 1 RN 13 8 DR E4
DB5 2 7 DR E5
DB6 3 47 6 DR E6
DB7 4 5 DR E7
RN 14
1

4
1

CN 17 CN 16
22 P 22 P
8

5
8

DG[ 0..7] DG0 1 8 DG E0


[P.4] DG1 2 7 DG E1
DG2 3 47 6 DG E2
DG3 4 5 DG E3
DG4 1 RN 15 8 DG E4
DG5 2 7 DG E5
DG6 3 47 6 DG E6
DG7 4 5 DG E7
RN 16
1

4
1

CN 19 CN 18
22 P 22 P
8

5
8

DR[0. .7] DR 0 1 8 D BE0


[P.4] DR 1 2 7 D BE1
DR 2 3 47 6 D BE2
DR 3 4 5 D BE3
DR 4 1 RN 17 8 D BE4
DR 5 2 7 D BE5
DR 6 3 47 6 D BE6
DR 7 4 5 D BE7
RN 18
1

4
1

CN 21 CN 20
22 P 22 P
8

5
8

LCD03B
First issue 10 / 03
PC BOARD INTERFACE - INTERFACE PC BOARD - SCHALTBILD PC BOARD - SCHEMA DELLA PC BOARD INTERFAZ PC BOARD

( PC BOARD 6/7)

+9 V

R7 6 2 2

1
C8 0 + C8 1
10 U
16 V 0.1U K

2
[P.1] RI 4
C 134 0.47U Z
16 V
[P.1] C8 2 0 .47U Z 1 28
RI 3 16 V R _IN 3 R_IN 4 R77 470
[P.1] C8 3 0 .47U Z 2 27 L_OUT AUD IO_L_OUT [P.7]
RI 2 16 V R _IN 2 LOUT R78 470
[P.1] RI 1
C8 4 0 .47U Z 3 26 R _OUT AUDIO_ R_OUT [P.7]
16 V R _IN 1 U1 3 ROUT C 132
[P.1] LI1
C8 5 0 .47U Z 4 25 R 122 470 10 U 16V
16 V L_IN 1 TDA7440 D AGN D [P.1]

+
1 2 AU DIO_L_Line
[P.1] LI2
C8 6 0 .47U Z 5 24
16 V L_IN 2 Vs R 123 470
[P.1] C8 8 0 .47U Z C8 7 1 [P.1]

+
LI3 6 L_IN 3 CREF 23 2 1 2 AUDIO _R_Line
16 V 10 U 16V
[P.1] C 135 0.47U Z 7 22 SDA_5V [P.4] C 133
LI4 16 V L_IN 4 SDA 10 U 16V
8 21 SCL_5V [P.4] R1 24 R1 25
MUXOUTL SCL 10K 10K
C89 2.2 U Z 9 20
16 V IN_L DIG_GN D
10 MUXOUTR TREBLER 19

C92 2.2 U Z 11 18 C96 C97


16 V IN_R TREBLEL
C95 0.1U K 12 17 5600P K 5600P K
BIN R NC1 50 V 50 V
C99 0.1U K 13 16
BOUTR NC2
R79 14 15
5.6K BIN L BOUTL
C 101 I2C Add r: 0x88
0 .1U K

C1 05 0 .1U K

R8 1
5.6K

LCD03B
First issue 10 / 03
PC BOARD INTERFACE - INTERFACE PC BOARD - SCHALTBILD PC BOARD - SCHEMA DELLA PC BOARD INTERFAZ PC BOARD

( PC BOARD 7/7)

+19 V VCC +5VS +12V +12V +5VS VC C +19 V


J1 1
[P.4] TP11 9 TP120 [P.4]
L CD_ON 1 2 L CD_BR U15 +9V
TP12 1 +12 V 1 3
3 4 VI VO

GND

1
5 6 + C 108 C 110
TP12 2 C 109 7809 ABD2 T 47U
7 8

2
0.33U Z 16 V 0.1U K

2
TP12 3
9 10

11 12
TP12 4 U16 VCPU3 3
13 14 +5VS 3 VI N VOUT 2
[P.3] PWR _ON
TP12 5
15 16

GND

1
[P.4] MUTE
TP12 6 C 112 + C 111 C 113
17 18 LD1117-3. 3 47U

1
[P.6] 0.1U K 16 V 0.1U K
AU DIO_L_OUT 19 20

2
[P.6]
AUDIO_ R_OUT
2072 06021 0
U17 VCPU1 8
3 VI N VOUT 2
C 140 C 141 C 142 C1 43 C1 44 C1 45 C 146 C 147 C 148 C 149 C1 50 C1 51 C 152 C 153

GND

1
220P J 220P J 22 0P J 220P J 220P J 220P J 220P J 220P J 22 0P J 22 0P J 220P J 220P J 220P J 220P J C 115 R83 + C 114 C 116
LM317 M 681F 47U

1
0.1U K 16 V 0.1U K

2
(For EMI) (For EMI)

1
R84
301F + C1 17
10U
16 V

2
RT1 RT2 U18 V33
J12 +12 V
2

VC C 3 2
VI N VOUT
t

t
TP2 3 3 1 TP24 2 1 2 1

GND

1
C 119 + C 118 C 120
LD1117-3. 3 47U

1
0.1U K 16 V 0.1U K

2
LCD03B
First issue 10 / 03
PC BOARD INTERFACE - INTERFACE PC BOARD - SCHALTBILD PC BOARD - SCHEMA DELLA PC BOARD INTERFAZ PC BOARD

( PC BOARD 1/7, 20”BI)

+5VS +9V OP5V RED_ IN R527 NC_R0603 J2


VR _IN
7 7
GREEN_ IN R528 NC_R0603
VY_I N 6 6 600 OHM [P .6 ]
R2 2 R2 3 1 TP 2 R8 5 R1 1K
15 0 15 0 BLU E_IN R529 NC_R0603 1 LI3
VB _IN TP 4 R8 6 R3 1K
2 2 RI 3

2
DN1 DN2 DN3 4 600 OHM
4 R7[P
BAV99 BAV99 BAV99
5 5 C1 C2 R6 .6 ]

2
3 3 3 OP5V D1 1 D1 3

2
D9 3 1000 P J1000 P J
3

TZMC5V1

TZMC5V1
C124

TZMC5V1
+ C9 0 0.1U K 2210165031 10K 10K

2
47U U2 4 R110

1 1

1 1
16V VCC 75

2
RED_ IN 3 *2 1 VR _IN
[P. 1]
D1 2 D1 4
16

J3 GND

TZMC5V1

TZMC5V1
6 MM1031X MR

4
11 1 R1 TP 3 R2 47 C121 2 1 RED_ IN
[P. 2]

2
TP 5 10 U 16V R138 0 [P. 1]

+
7 VR_GND
GSDA 12 2 G1 TP 6 R4 47 C122 2 1 GREEN_ IN
[P. 2]
TP 7 10 U 16V

+
8
13 3 B1 TP 8 R5 47 C123 2 1 BL UE_I N
[P. 2] OP5V
TP 9 10 U 16V

+
9
TP 10 14 4 C125 J1
TP 11 10 R8 R9 R1 0 C3 C4 C5 0.1U K 7 7

2
GSCL 15 5 U2 5 R115 [P. 6] 6 6
75 75 75 47P 47P 47P VCC 75 Audio_L_Line R8 7 600 OHM 1 1
50 V J 50 V J 50 V J GREEN_ IN 3 *2 1 VY_I N
[P. 1]
D-Sub15 Audio _R_Line R8 8 600 OHM 2
GND 2
4 4
83.27R03.036 MM1031X MR [P. 6] C130 C131 5 5

2
PC _5V

D1 5 D1 7
2

2
D2 3 D2 1 R139 0
VY_GND
[P. 1] 1000 P J 1000 P J 3 3
17

TZMC5V1

TZMC5V1

TZMC5V1

TZMC5V1
Audio Line ou t(2210165031)

2
27V 27V OP5V

1 1

1 1
1 1

1 1
C126
D6 D8 0.1U K D1 6 D1 8

2
TZMC5V1

TZMC5V1
D2 0 D2 2 U2 6 R120

TZMC5V1

TZMC5V1
VCC 75
27V 27V BLU E_IN 3 *2 1 VB _IN
[P. 1]

2
2

GND
D5 D7 MM1031X MR

4
R140 0
VB _GND
[P. 1]
R136 1K [P. 2] J5
RG B_VS
R137 1K
RG B_HS
[P. 2] 1 2 VY_I N [P. 1]
[P. 4] VCLK 3 4 VY_GND [P. 1]
R1 4 47 5 6 VB _IN [P. 1]
+5VS R1 3 47 [P. 4] VVS 7 8 VB _GND [P. 1]
+5VS [P. 4] VHS 9 10 VR _IN [P. 1]
U1
0.1U K C6 [P. 4] VPEN 11 12 VR _GND [P. 1]
+5VS [P. 4] VFI EL D 13 14
D1 C7 0.1U K 1 C1+ VCC 16 15 16 RI 1
[P. 6]
2 V+ GND 15 [P .4 ] GV0 17 18 LI1
[P. 6]
2

DN8 DN9 1N4148 UART_R X GV1 [P. 6]

100P

100P

100P
3 14

C136

C137

C138

C139
C1- T1OUT GV[0 ..7] 19 20 RI 2
BAV99 BAV99 C9 C8 0.1U K 4 C2+ R1IN 13 UAR T_TX GV2 21 22 LI2
[P. 6]
3 3 PC _5V D2 5 C2- R1OUT 12 RX RX [P. 4] GV3 23 24 RI 4
[P. 6]
0.1U K 6 11 TX D [P. 4] 25 26 [P. 6]

OPEN

OPEN

OPEN

OPEN
V- T1IN TX D LI4
1N4148 7 10 GV4 27 28
T2OUT T2IN
U2 8 R2IN R2OUT 9 GV5 29 30 INPUT_D ET
[P. 3]
1

C1 0 GV6 31 32 AV_ DET


[P. 3]
R1 5 R1 6 8 VCC A0 1 C1 1 0.1U K SP232 EC N GV7 33 34 TV_DET
[P. 3]
35 36
4.7K 4.7K 7 WP A1 2 0.1U K [P .4 ] BU 0 37 38 SDA [P. 4]
BU [0..7] BU 1 39 40 SC L [P. 4]
GSCL 6 3 BU 2 41 42
SCL A2 BU 3 43 44 DEC OE [P. 3]
GSDA 5 SDA GND 4 45 46 POR TB3 [P. 4]
BU 4 47 48 VIDE O_RESET [P. 4]
AT2 4C02A BU 5 49 50 AV_SEL [P. 4]
BU 6 51 52 CVBS_SEL [P. 4]
BU 7 53 54
[P. 4] 55 56 RY 4 RY[0..7 ] [P .4 ]
RY[0..7 ] RY 0 57 58 RY 5
RY 1 59 60 RY 6
RY 2 61 62 RY 7
RY 3 63 64
65 66
[P .7 ] +12V 67 68 +12V [P .7 ]
S crew Holes 69 70
[P .7 ] +5VS 71 72 +5VS [P .7 ]
73 74
[P .7 ] VCC 75 76 VCC [P .7 ]
77 78
[P .7 ] +9V 79 80 +9V [P .7 ]
GF80
1

5 9 5 9 5 9 5 9 5 9 PC BOA
48.M 2305 .A00 GF-80Pin
4 8 4 8 4 8 4 8 4 8 onday, September 08, 2003
Optical Points
3 7 3 7 3 7 3 7 3 7

2 6 2 6 2 6 2 6 2 6 OP1 OP2 OP3 OP4 OP5 OP6 OP7


OP OP OP OP OP OP OP
H1 H2 H3 H4 H5

HO LE-V 8 HO LE-V 8 HO LE-V 8 HO LE-V 8 HO LE-V 8

OP8 OP9 OP10 OP11 OP12 OP13 OP14 OP15 OP16


OP OP OP OP OP OP OP OP OP

LCD03B
First issue 10 / 03
PC BOARD INTERFACE - INTERFACE PC BOARD - SCHALTBILD PC BOARD - SCHEMA DELLA PC BOARD INTERFAZ PC BOARD

( PC BOARD 2/7, 20”BI)

U2 0 74LVC1 G126 VD33


[P. 4] PC_ AV 1 OE VCC 5
Trac e and
[P. 1] 2 R1 7 3 .3K C1 2 .039U
RG B_HS A 16 V K Components
3 GND Y 4 R1 8 47 Close IC
R1 9 47
C1 3 3900P PV DD
U2 1 74LVC1 G126 50 V K
1 OE VCC 5
PV DD AV DD VD3 3
[P. 1] RG B_VS 2 A
3 4 GVM ID
GND Y C1 4

0.1U K

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

5
CN1 CN2

CLAM P

FIL T

VD D
VD D
VSYN C
HSYN C
VD

VD
VD
PVD
PVD
GND

GND

GND

GND

GND
GND

GND
MIDSCV
[P. 4]

COAST
22P 22P
GCOAS T
41 GND GND 20 GB E[0..7 ]
[P. 4]

4
42 19 AD BE0 1 8 GBE0
VD B0
[P. 1] BLUE _IN C1 5 .047U BA IN 43 BAIN B1 18 AD BE1 2 RN1 7 GBE1
50 V K 44 17 AD BE2 3 6 GBE2
GND B2 AD BE3 47 GBE3
45 VD B3 16 4 5
46 U3 15 AD BE4 1 8 GBE4
VD AD9 883KST-110 B4 AD BE5 RN2 GBE5
47 GND B5 14 2 7
[P. 1] GREEN_ IN C1 6 .047U GA IN 48 GAIN B6 13 AD BE6 3 6 GBE6
50 V K 49 12 AD BE7 4 47 5 GBE7
C1 7 1000 P J SOG IN SOGIN B7
50 GND VDD 11
50V 51 VD I2C Addr: 0x9 8 GND 10 GGE [0..7]
[P. 4]
52 9 AD GE 0 1 8 GGE0
VD G0 AD GE 1
53 GND G1 8 2 RN3 7 GGE1
[P. 1] RED_ IN C1 8 .047U RA IN 54 RAIN G2 7 AD GE 2 3 6 GGE2
50 V K 55 6 AD GE 3 4 47 5 GGE3
A0 G3
[P. 4] SCL _CPU R2 0 0 56 SCL G4 5 AD GE 4 1 8 GGE4
[P. 4] SDA_ CP U R2 1 0 57 SDA G5 4 AD GE 5 2 RN4 7 GGE5
GVR EF 58 3 AD GE 6 3 6 GGE6
REF BYPASS G6 AD GE 7 47 GGE7
59 VD G7 2 4 5

SOGOUT
60 1

DATACK
GND GND

HSOUT

1
VSOUT

VD D

VD D
VD D
GND

GND

GND

GND
C1 9 22P 22P

VD

R7
R6
R5
R4
R3
R2
R1
R0
CN3 CN4
0.1U K

8
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VCPU33 VD3 3

L1
42 OHM

5
CN5 CN6
22P 22P

1
GRE[0. .7]
[P. 4]

4
AD RE 0 1 8 GRE0 + C2 0
AD RE 1 2 RN5 7 GRE1 10 U
AD RE 2 3 6 GRE2 16V

2
AD RE 3 4 5 GRE3
AD RE 4 1 478 GRE4
AD RE 5 2 RN6 7 GRE5
AD RE 6 3 6 GRE6
AD RE 7 4 5 GRE7
47 U4 AV DD
+5VS
A DCK L4 30 OHM
GCL K
[P. 4] L3 3 VIN VOUT 2
42 OHM

GND
A DHS R2 4 47
GFBK
[P. 4]

1
C2 1
ADVS R2 5 47
GVS
[P. 4] LD1117-3. 3 + C2 2

1
0.1U K 47U
VD33 16V

2
C2 5 C2 6
C2 7 C2 3 C2 4 22P 22P
22 P J 22 P J OPEN OPEN
0.1U K

R2 6
16
ADS OG

VD33 U5 C2 8
U6 220P VD3 3 1K
VC C

[P. 4] MV _E N 1 OE VCC 5 CX1 14 50 V J U7 PV DD


1 15 R2 7 47K +5VS
1A RCX1 L6
2 A 2 1B 3 VIN VOUT 2
1Q 13 D3 R2 8 36 0
GHSS OG
[P. 4] 42 OHM

GND
3 GND Y 4 3 1R 1Q 4

1
1N4148 C2 9
74LVC1 G126 9 5 LD1117-3. 3 + C3 0
2A 2Q

1
10 12 D4 R2 9 1K 0.1U K 47U
2B 2Q
1
16V

2
11 6 1N4148 + C3 1 R3 0
2R CX2 C3 2 1U 47K
RCX2 7 48.M 2305 .A00
GND

220P VD3 3 50V


2

50 V J 20L0BI
74LV123PW R3 1 221K F PC BOA RD
8

onday, September 08, 2003

AV DD VD3 3 PV DD

C3 3 C3 4 C3 5 C3 6 C3 7 C3 8 C3 9 C4 0 C4 1 C4 2 C4 3 C4 4 C4 5 C4 6 C4 7 C4 8 C4 9 C5 0

0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K

LCD03B
First issue 10 / 03
PC BOARD INTERFACE - INTERFACE PC BOARD - SCHALTBILD PC BOARD - SCHEMA DELLA PC BOARD INTERFAZ PC BOARD

( PC BOARD 3/7, 20”BI)

D[0..15]
VCPU33 [P. 4]
VCPU33
+5VS
C5 1
OPEN R3 2 U8
0.1U K 3 Q1
L8 42 OHM
+5VS
26 CE VPP 13 2N3906
[P. 4] ROMOEn 28 OE
[P. 4] ROMWEn 11 WE VCC 37 R3 4
[P. 4] RESETn R3 3 0 12
FWPn 14
RP 1 2
WP D0
47 29

8
BYTE D1
A1 D2 31 D1
D2
2N3904 10K R3 5 +5VS Q2 CN7
25 A0 D3 33 1K 2N3906 22P
A2 24 A1 D4 35 D3 R3 6 2N3906
A3 23 38 D4 1K R3 8

1
A4 A2 D5 D5
22 A3 D6 40 LED1_SEL
A5 21 42 D6 R3 7
A6 A4 D7 D7
20 44
A7 19
A5 D8
30 D8 [P. 3] Q3
10K
A8 A6 D9 D9 2N3904 R4 2
18 A7 D10 32 R4 0 1K IRRCVR_3V
A9 8 34 D10 1K
A10 A8 D11 D11
7 A9 D12 36 10K R3 9 47 0
A11 6 39 D12
A12 A10 D13 D13 LED2_SEL
5 41 R4 3
A13 4
A11 D14
43 D14 R4 1 [P .4 ]
A14 3
A12 D15
45 D15 [P. 3] Q4
A15 A13 D16 2N3904 10K
2 A14 R4 4
A16 1 1K
A17 A15 VCPU33
48 A16 GND 46 10K
A18 17 27 J6
A19 A17 GND
16 A18 C5 2 TP 47
LED1 TP 49 12
AT 49BV8192A(T) 0.1U K 11
LED2 TP 50

20
U9 KPD[0..6] IRRC VR TP 51 10
D0 KPD0 KPD0 TP 53 9
18 2

VC C
FCEn D1 1Y1 1A1 KPD1 KPD1 TP 54 8
16 1Y2 1A2 4 7
D2 14 6 KPD2 KPD2 TP 55
R4 5 R4 6 D3 1Y3 1A3 KPD3 KPD3 TP 56 6
12 1Y4 1A4 8 5
D4 9 11 KPD4 KPD4 TP 57
D5 2Y1 2A1 KPD5 KPD5 TP 58 4
7 2Y2 2A2 13 3
D6 5 15 KPD6 KPD6 TP 48
3.3K 3.3K D7 2Y3 2A3 FAN_DET TP 60 2
3 2Y4 2A4 17 1

R4 7

R4 8

R4 9

R5 0

R5 1

R5 2

R5 3
1 CS0n
1G CS0n

GND

5
19 20L2021012
2G CN8 CN9
TP 59

10K

10K

10K

10K

10K

10K

10K
VCPU33 VCPU33 74A HC244 22P 22P

10

4
J8
VCPU33
A2 1 60 A1
A4 2 59 A3
60

59

A6 3 58 A5

R5 4

R5 5

R5 6
4 57 A7 C5 3
A9 5 56 A8 0.1U K
A11 A10

3.3K

3.3K

3.3K
6 55

20
U 10
7 54
A12 8 53 D8 18 2 AV_DET [P. 1]

VC C
1Y1 1A1
A14 9 52 A13 D9 16 4 INPUT_DET [P. 1]
CONN ML 60P D1.27 ST AMP/104549

1Y2 1A2
10 51 A15 D10 14 1Y3 1A3 6 R141 OPEN
TV_DET [P. 1]
A17 11 50 A16 D11 12 8
A19 A18 D12 1Y4 1A4
12 49 9 2Y1 2A1 11
13 48 D13 7 13
D14 2Y2 2A2
14 47 5 2Y3 2A3 15
15 46 D15 3 17 VCPU33
ROMOEn ROMWEn 2Y4 2A4
16 45 [P. 4]
[P. 4] D15 17 44 D7
1G 1 CS0n

GND
D14 18 43 D6 19 VCPU33 R530
2G C361
19 42 D13 R531
D5 20 41 D12 74A HC244 NC_R0603

10
D4 21 40 NC_R0603
22 39 D11 U 27 0.1U K

20
D3 23 38 D10 LCD_ON [P .7 ]
D2 24 37 D8 3 2 MUTE [P. 7]

VC C
D9 D1 D9 D1 Q1 R532 Q 13_N C
25 36 4 D2 Q2 5
D8 26 35 D0 D10 7 D3 Q3 6 VIDEO_RESET [P. 1] NC_R0603
27 34 D11 8 D4 Q4 9 PORTB3 [P. 1] 2N3904 C553

2
28 33 D12 13 D5 Q5 12 MV_EN [P. 2] 2.2U K
29 32 D13 14 D6 Q6 15 PC_AV [P. 2] 16V
RESETn 30 31 NMI D14 17 D7 Q7 16 AV_SEL [P. 1]
D15 18 D8 Q8 19 CVBS_SEL [P. 1]
[P. 4] [P. 4] [P. 4]
2

20L1023060
A[1..19] CS1n 11 CLK

GND
[P. 4] VCPU33
R142 1 CLR
48.M 2305 .A00
10K 74LVC 273
C359 PC BOARD

10
VCPU33 + C 362
10U
16V
0.1U K
U 22
20

D0 3 2 [P. 1]
VC C

D1 Q1 DECOE
D1 4 D2 Q2 5 PWR_ON
[P. 7]
D2 7 D3 Q3 6 LED1_SEL
[P. 3]
D3 8 D4 Q4 9 LED2_SEL
[P. 3]
D4 13 12
D5 D5 Q5
14 D6 Q6 15
D6 17 16
D7 D7 Q7
18 D8 Q8 19
[P. 4]
CS1n 11 CLK
GND

R126 1
VCPU33 CLR
10K 74LVC 273
10

+ C 360
10U
16V

LCD03B
First issue 10 / 03
PC BOARD INTERFACE - INTERFACE PC BOARD - SCHALTBILD PC BOARD - SCHEMA DELLA PC BOARD INTERFAZ PC BOARD

( PC BOARD 4/7, 20”BI)

V33 V33 VCPU33

R5 7

R5 8
V33 VCPU33
C5 4
0.1U K C5 5 C5 6

1
Q5 Q6 U1 1 22 P J 22 P J
BSN 20 BSN 20

3.3K

3.3K
8 VCC A0 1
7 WP A1 2 R ES ETn

DCLK_L
[P. 1] SC L 2 3 3 2 SCL _CPU 6 SCL A2 3
5 SDA GND 4 [P. 3]

1
Q7 Q8 L1 0
BSN 20 BSN 20
AT 24C32AN-10SI-2.7 DCLK 106 DC LK
DC LK
[P .5 ]
107 30 OHM
DCLKNEG
[P. 1] SD A 2 3 3 2 SDA_ CP U VCPU33
DVS 108 RVS
RV S
[P .5 ]
A[1 ..19] DHS 109 RHS
RHS
[P .5 ]
A1 192 A1
DEN 110 RDE
RDE
[P .5 ]
A2 191 A2 [P. 3] DR[0. .7]
R5 9 190 A3 103 DR0
A3 DR0
[P. 2] SCL _CPU VCPU33 VCPU33 VCPU33 VCPU33 3.3K A4 189 A4
DR1 102 DR1 [P .5 ]
188 A5 101 DR2
A5 DR2
[P. 2] SDA _CPU A6 187 A6
DR3 100 DR3

R6 1

R6 2

R1 1

R1 2
R6 0 0 RP TR 11 142 184 A7 99 DR4
R ES ETn TESTEN A7 A8 DR4 DR5
139 RESET A8 183 DR5 98
R6 3 10 0 EXTRSTEN 28 182 A9 97 DR6
EXTRSTEN A9 A10 DR6 DR7
A10 181 DR7 96
[P. 1] R6 4 47 0 RX D A11

3.3K

3.3K

3.3K

3.3K
RX 67 RXD A11 180 DG [0..7]
[P. 1] TX D TX D 68 TXD A12 179 A12
DG0 95 DG0
[P. 2] GCL K 31 GCLK
R6 5 10K
A13 178 A13
DG1 94 DG1 [P .5 ]
TP 61 34 36 177 A14 93 DG2
GPEN GCOAST GCOAS T A14 DG2
[P. 2] GVS 32 GVS
SDA_ CP U 207 PORTA0 A15 176 A15
DG3 92 DG3
[P. 2] GHSS OG 33 GHSSOG
[P. 2] SCL _CPU 206 PORTA1 A16 175 A16
DG4 91 DG4
[P. 2] GFBK 35 GFBK
TP 12 SDA2 205 PORTA2
U 12C
A17 174 A17
DG5 90 DG5
[P. 2] GB E[0..7 ] TP 13 SC L2 204 PORTA3 A18 173 A18 U12B
DG6 89 DG6
GBE0 2 [P. 3] IRRCVR_3V 203 PW11 3 164 A19 88 DG7
GBE0 IRRCVR_3V PORTA4 A19 DG7
GBE1 3 [P. 1] R129 0 IN T 202 Mi sc PW113
GBE1 TV_DET PORTA5 D[0..15] DB [0..7]
GBE2 4 GBE2
[P. 7] L CD_ON R130 OPEN GP IOA6 201 PORTA6 D0 163 D0
DB0 83 DB 0
GBE3 5 [P. 7] R6 6 10K PW M_ BR 200 162 D1 [P. 3] Display Port 82 DB 1 [P .5 ]
GBE3 L CD_BR PORTA7 D1 DB1
GBE4 6 161 D2 81 DB 2
GBE5 GBE4 C5 7 D2 D3 DB2 DB 3
7 GBE5 D3 160 DB3 80
GBE6 8 2.2U K 147 159 D4 79 DB 4
GBE7 GBE6 16V TRST D4 D5 DB4 DB 5
9 GBE7 146 TCK D5 158 DB5 78
[P. 2] GGE [0..7] 145 TMS D6 157 D6
DB6 77 DB 6
GGE0 10 144 156 D7 76 DB 7
GGE1 GGE0 TDI D7 D8 DB7
11 GGE1 143 TDO D8 155 DG R[0 ..7]
GGE2 12 154 D9 136 DG R0
GGE2 D9 DGR0
GGE3 13 GGE3 D10 153 D1 0
DGR1 135 DG R1 [P .5 ]
GGE4 14 GGE4
[P. 3] NM I 193 NMI D11 152 D1 1
DGR2 134 DG R2
GGE5 15 GGE5 Trace an d Components Close IC D12 151 D1 2
DGR3 133 DG R3
GGE6 18 150 D1 3 132 DG R4
GGE7 GGE6 D13 D1 4 DGR4 DG R5
19 GGE7 169 XI D14 149 DGR5 131
[P. 2] GRE[0. .7] 170 XO D15 148 D1 5
DGR6 130 DG R6
GRE0 20 VCPU18 R6 7 1.5M 129 DG R7
GRE1 GRE0 L11 L12 RDn TP 62 DGR7
21 GRE1 RD 195 DGG[0. .7]
GRE2 22 194 WR n TP 63 128 DGG0
GRE2 WR DGG0
42 OH M

42 OH M
GRE3 23 GRE3
Y1
ROMOE 196 ROM OE n [P .3 ] DGG1 127 DGG1 [P .5 ]
GRE4 24 X607 X608 197 126 DGG2
GRE5 GRE4 ROMWE CS 0n ROM WE n[P .3 ] DGG2 DGG3
25 GRE5 CS0 198 CS0 n [P .3 ] DGG3 125
GRE6 26 C5 8 14.318M HZ C5 9 199 CS 1n [P .3 ] 122 DGG4
GRE7 GRE6 PW113 U12A C6 0 C6 1 18P 18P CS1 CS1 n DGG4 DGG5
27 GRE7 DGG5 121
Graphics and 50 V J 50 V J 120 DGG6
PW113 DGG6
[P. 1] 71 Video Port 0.1U K 0.1U K 119 DGG7
VCLK VCLK DGG7
[P. 1] VVS 74 VVS DGB[0. .7]
[P. 1] VHS 75 VHS DGB0 118 DGB0
[P. 1] VFI EL D 69 VFIELD DGB1 117 DGB1 [P .5 ]
[P. 1] VPEN 70 VPEN old net: UV DGB2 116 DGB2
VCPU33 115 DGB3
V DDPA3
VDDPD3

U12E DGB3
GV0 47 VYUV0
[P. 1] BU [0..7] DGB4 114 DGB4
GV1 48 BU 0 39 113 DGB5
GV2 VYUV1 BU 1 PORTC0 DGB5 DGB6
49 VYUV2 40 PORTC1 DGB6 112
GV3 50 BU 2 41 111 DGB7
VYUV3 PORTC2 DGB7
104
123
140
171
208

167
165

137
185

GV4 51 BU 3 42
29
52
72
86

16
37
65
84

GV5 VYUV4 BU 4 PORTC3


54 VYUV5 43 PORTC4
GV6 55 BU 5 44
VYUV6 PORTC5
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36
VDDQ37
VDDQ38

old net: Y GV7 BU 6 L2


VDDPA1_1.8V
VDDPA2_1.8V

56 VYUV7 45 PORTC6
[P. 1] GV[0 ..7]
BU 7 46 PORTC7
42 OHM
[P. 1] RY[0..7 ]
RY 0 57 L5
PORTB0

GPO Port
RY 1 58 42 OHM
VCC VCC VCPU33 RY 2 PORTB1
59 PORTB2
U 12D PW113 Power and Ground RY 3 60 L7
PORTB3
R6 9

RY 4 61 NC _L1206
0
1
2
3
4
5
6
7
8

VSSPA2

VSSPA1

PORTB4
1

Q9 Q10 RY 5 62
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6

PORTB5
R7 1

BSN 20 BSN 20 RY 6 63 C8 0 470P K


PORTB6
3.3K

RY 7 64
SCL _CPU PORTB7
SCL_5V 2 3 3 2
1
17
38
66
85

30
53
73
87
138
186

105
124
141
172

166

168
1

[P. 1] Q11 Q12


3.3K

BSN 20 BSN 20 PW113

2 3 3 2 SDA_ CP U PC BOA RD
SD A_5V EMI solution 20L0BI
[P. 1] 48.M 2305 .A00

VCPU33 VCPU18

C6 2 C6 3 C6 4 C6 5 C6 6 C6 7 C6 8 C6 9 C7 0 C7 1 C7 2 C7 3 C7 4 C7 5 C7 6

0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K

LCD03B
First issue 10 / 03
PC BOARD INTERFACE - INTERFACE PC BOARD - SCHALTBILD PC BOARD - SCHEMA DELLA PC BOARD INTERFAZ PC BOARD

( PC BOARD 5/7, 20”BI)

15"
[P. 4] DC LK
SWAPRGB: [P. 4] DC LK
RV S
R7 3 47 DVS TP 64 15" 20" J20
[P. 4] R7 4 47 DHS TP 65 1
Display Data Swap [P. 4] RHS R7 5 47 DEN V33 TP 20 0 2
RDE
RGB Order. J9 J10 3
C7 7 C7 8 C7 9 4
When SWAPBO=1,
RGB will be BGR.
22P
O PEN
22P
O PEN
22P
O PEN First Pixel 40
39
DBE0
DBE1
TP 66
TP 67
30
29
DBE0
DBE1
5
6
TP 68 38 DBE2 TP 69 28 DBE2 7
DGB[0. .7] DGB0 DR O0 DBE3 TP 70 DBE3
1 8 37 27 8
SWAPEO: [P. 4] DGB1 2 7 DR O1 36 26 9
DGB2 3 47 6 DR O2 DBO0 TP 71 35 DBE4 TP 72 25 DBE4 10
Display Data Swap DGB3 4 5 DR O3 DBO1 TP 73 34 DBE5 TP 74 24 DBE5 11
Even Odd Pixels. DGB4 1 RN7 8 DR O4 DBO2 TP 75 33 DBE6 TP 76 23 DBE6 12
DGB5 2 7 DR O5 DBO3 TP 77 32 DBE7 TP 78 22 DBE7 13
When SWAPEO=1, DGB6 3 47 6 DR O6 31 21 14
the even and odd pixel DGB7 4 5 DR O7 DBO4 TP 79 30 DGE0 TP 80 20 DGE0 15
RN8 DBO5 TP 81 29 DGE1 TP 82 19 DGE1 16
data will be swapped DBO6 TP 83 DGE2 TP 84 DGE2
28 18 17

5
at the package pins .

5
DBO7 TP 85 27 DGE3 TP 86 17 DGE3 18
CN 11 CN 10
DGR, DGG, DGB : First Pixels 22P 22P DGO0 TP 87
26
DGE4 TP 88
16
DGE4
19
25 15 20
DR, DG, DB : Second Pixels DGO1 TP 89 24 DGE5 TP 90 14 DGE5 21

4
1

4
DGO2 TP 91 23 DGE6 TP 92 13 DGE6 22
DGO3 TP 93 22 DGE7 TP 94 12 DGE7 23
DGG[0..7 ] 21 11 24
DGG0 1 8 DGO0 DGO4 TP 95 20 DR E0 TP 96 10 DR E0 25
[P. 4] DGG1 DGO1 DGO5 TP 97 DR E1 TP 98 DR E1
AU 20" DGG2
2
3 47
7
6 DGO2 DGO6 TP 99
19
18 DR E2 TP 10 0
9
8 DR E2
26
27
DGG3 4 5 DGO3 DGO7 TP 10 1 17 DR E3 TP 10 2 7 DR E3 28
RN9
SWAPRGB: DGG4 1 8 DGO4 16 6 29
DGG5 2 7 DGO5 DR O0 TP 10 3 15 DR E4 TP 10 4 5 DR E4 30
Display Data Swap DGG6 3 47 6 DGO6 DR O1 TP 10 5 14 DR E5 TP 10 6 4 DR E5 31
RGB Order. DGG7 4
RN 10
5 DGO7 DR O2 TP 10 7 13 DR E6 TP 10 8 3 DR E6 32
DR O3 TP 10 9 12 DR E7 TP 11 0 2 DR E7 33
When SWAPBO=1, 11 1 34

5
8

5
RGB wi ll be BGR. DR O4 TP 11 1 10 DC LK 35
CN 13 CN 12 DR O5 TP 11 2 9 CON30P(O PEN ) 36
22P 22P DR O6 TP 11 3 8 DEN 37
SWAPEO: DR O7 TP 11 4 7 38

4
1

4
6 DVS 39
Display Data Swap 5 DHS 40
Even Odd Pixels. DG R[0 ..7]
TP 22 6 4 41
DG R0 1 8 DBO0 3 TP 20 1 42
When SWAPEO=0, [P. 4] DG R1 2 7 DBO1 DEN TP 11 6 2 43
DR, DG, DB : First Pixels DG R2 3 47 6 DBO2 1 VCC 44
DG R3 4 5 DBO3 45
DG R4 1 RN 11 8 DBO4 46
20K0049 040(OPEN)
DG R5 2 7 DBO5 47
DG R6 3 47 6 DBO6 48
DG R7 4 5 DBO7 49
RN 12 50

5
8

5
20L2043050
CN 15 CN 14
22P 22P
DC LK TP 11 5
1

4
Second Pixel
1

C 363
DB [0..7] DB 0 DR E0 22 P J
1 8
[P. 4] DB 1 2 7 DR E1
DB 2 3 47 6 DR E2
DB 3 4 5 DR E3
RN 13
DB 4
DB 5
1
2
8
7
DR E4
DR E5 EMI solution,
DB 6 47 DR E6
DB 7
3
4
6
5 DR E7 close to J2 0
RN 14
1

4
1

CN 17 CN 16
22P 22P
8

5
8

DG [0..7] DG0 DGE0


1 8
[P. 4] DG1 2 7 DGE1
DG2 3 47 6 DGE2
DG3 4 5 DGE3
DG4 1 RN 15 8 DGE4
DG5 2 7 DGE5
DG6 3 47 6 DGE6
DG7 4 5 DGE7
RN 16
PC BOA RD
1

4
1

CN 19 CN 18
22P 22P 48.M 2305 .A00
8

5
8

DR[0. .7] DR0 DBE0


1 8
[P. 4] DR1 2 7 DBE1
DR2 3 47 6 DBE2
DR3 4 5 DBE3
DR4 1 RN 17 8 DBE4
DR5 2 7 DBE5
DR6 3 47 6 DBE6
DR7 4 5 DBE7
RN 18
1

4
1

CN 21 CN 20
22P 22P
8

5
8

LCD03B
First issue 10 / 03
PC BOARD INTERFACE - INTERFACE PC BOARD - SCHALTBILD PC BOARD - SCHEMA DELLA PC BOARD INTERFAZ PC BOARD

( PC BOARD 6/7, 20”BI)

NOTE:I2C ADDRESS SELECT


C 502
C 501 3.3P C
3.3P C
R501 10 R502 OPEN VCC
Y 501 C 503
56 P J

18.432M HZ L501
42 OHM

R503 R504
4.7K 4.7K

+ C504 C505 C506


TP501 TP50 2 100 U
16V 470P K 1.5N M
C 507 C 508
56 P J 56 P J

64

63

62

61

60

59

58

57

56

55

54

53

51

52

50
ANA_IN -
XTAL_I N
TP
NC

NC

NC

ANA2_IN+

ANA1_IN+
ADR_SEL

TESTEN
XTAL_OUT
D_CTR_I/O_0

D_CTR_I/O_1
STANDBYQ

AUD_CL_OUT
SCL_5V R505 10 0 1 49
[ P.4] I2C_CLK AVSUP
SD A_5V R506 10 0 2 48 C509 10 U 16V
[ P.4] I2C_SDA AVSS

+
3 I2S_SL MONO_IN 47
C510 C511
4 46 C512 0.1U K
100P K 100P K I2S_WS VREFTOP
5 I2S_DA_OUT SC1_IN_R 45
VCC 6 I2S_DA_IN1 SC1_IN_L 44 C513 330 N Z R507 47 0 RI 1 [P. 1]
C514 330 N Z R508 47 0 LI1 [P. 1]
7 ADR_DA ASG1 43
L502 U501
42 OHM 8 ADR_WS SC2_IN_R 42 C515 330 N Z R509 47 0 RI 2 [P. 1]
C516 330 N Z R510 47 0 LI2 [P. 1]
9 ADR_CL MSP 3412G SC2_IN_L 41

10 DVSUP ASG2 40 C517 330 N Z R511 47 0 RI 3 [P. 1]


C518 330 N Z R512 47 0 LI3 [P. 1]
11 L ow:0x80 39
+ C519 C520 C522 DVSS High:0x84 SC3_IN_R
100 U C 521 12 Open:0x88 38 C523 330 N Z R513 47 0 [P. 1]
220P Z 470P K I2S_DA_IN2 SC3_IN_L RI 4
VCC 16V 1.5N M C524 330 N Z R514 47 0 LI4 [P. 1]
13 NC ASG4 37
R515 14 36
4.7K NC SC4_IN_R C525 C526 C527 C528 C529 C530 C531 C532
15 NC SC4_IN_L 35

330P J

330P J

330P J

330P J

330P J

330P J

330P J

330P J
16 34 C533 0.1U K
RESETQ AGNDC

SC2_OUT_R

SC1_OUT_R
SC2_OUT_L

SC1_OUT_L
C 534 35V

DACM_SUB

+
+ 17 33
DACA_R AHVSS

AHVSU P
22U C535 3.3U

DACM_R

DACM_C

DACM_S
DACM_L

CAPL_M
DACA_L

CAPL_A
VREF2

VREF1
16V

C537
C 536 C538 +9V

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32
R533 NC_R0603 1.5N M 470P K
+
10 U
16V D1 9 1 N 4148
R534 NC_R0603 L503 8_3_VOLT
42 OHM
Voltage decreasing 0.7v
C539 C551 10 U 16V
[P. 1] 10 U 16V LINEOUT_ R R517 NC_R0603

+
AUDIO_R_Line
+

[P. 1] A UDIO _L_Line 10 U 16V LINE OUT_ L R518 NC_R0603 C552 10 U 16V
+

+
[P. 7] AU DIO_R_OUT C540 R519 47 0

[P. 7] A UDIO_L_OUT R520 47 0


C549 C544
R524 R525 C548 C543 C545 R516 10 0
R7 2 0

1000P J

1000P J

1000P J

1000P J

1000P J
R521 10 0 48.M 2305 .A00
20L0BI
10K 10K PC BOARD
R522 10 0 LINE OUT_ L

R523 10 0 LINEOUT_ R
Digital GND Analog GND

LCD03B
First issue 10 / 03
PC BOARD INTERFACE - INTERFACE PC BOARD - SCHALTBILD PC BOARD - SCHEMA DELLA PC BOARD INTERFAZ PC BOARD

( PC BOARD 7/7, 20”BI)

+19V VCC +5VS +12V +12V +5VS VCC +19V


J11
[P. 4]
L CD_ON
TP 11 9
1 2
TP 12 0 L CD_BR [P. 4]
TP 12 1 +12V
3 4

5 6
TP 12 2
7 8 CHAN GE C108 P/N to 79.4761D.3A1
TP 12 3
9 10

11 12 U1 5 +9V
TP 12 4 1 3
13 14 VI VO

GND
[P. 3]
PW R_ON
TP 12 5
15 16 + C 108 C110
[P. 4] TP 12 6 C109 47U
MUTE 17 18 780 9ABD2T

2
0.33U Z 16V 0.1U K
[P. 6]
A UDIO_L_O UT 19 20
[P. 6]
AU DIO_R_OUT
2072060210
U1 6 VCPU33
+5VS 3 2
C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C150 C151 C152 C153 VIN VOUT

GND
220P J 220P J 220P J 220P J 220P J 220P J 220P J 220P J 220P J 220PJ 220PJ 220PJ 220PJ 220PJ C112 + C 111 C113
47U
LD1117-3. 3

1
0.1U K 16V 0.1U K

(For EMI) (For EMI)


U1 7 VCPU18
3 2
VIN VOUT

GND
C115 R8 3 + C 114 C116
681F 47U
LM317 M

1
0.1U K 16V 0.1U K

R8 4
301F + C117
10 U
16V
U1 8 V33
VCC 3 2
VIN VOUT

GND
C119 + C 118 C120
47U
LD1117-3. 3

1
0.1U K 16V 0.1U K

RT1 RT2
J12 +12V
2

TP 23 3 1 TP 24 2 1 2 1

OPEN
NC NC 20L0BI
PC BOA RD
48.M 2305 .A00

LCD03B
First issue 10 / 03
VIDEO SIGNAL PROCSSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( VIDEO BOARD 1/6)

J1
[P.3] V CLK
TP1 1 2 TP2 L23 1000 OHM SD _Y_IN [P.2]
[P.3] VVS
TP3 3 4 TP98 L24 1000 OHM SD_Y_ GND [P.2]
[P.3] VHS
TP5 5 6 TP6 L25 1000 OHM S D_CB_I N [P.2]
[P.3] V PEN
TP7 7 8 TP99 L26 1000 OHM SD_CB_GND [P.2]
[P.2] VF IELD
TP8 9 10 TP9 L27 1000 OHM SD_C R_I N [P.2]
11 12 TP10 0 L28 1000 OHM SD_ CR_GND [P.2]
VY0 TP10 13 14 TP11
RI 1
[P.3] VY[0..7 ]
VY1 TP12 15 16 TP13
LI1
[P.4]
VY2 TP14 17 18 TP15 [P.4]
RI 2
VY3 TP16 19 20 TP17
LI2
[P.4]
21 22 TP18
RI 4
[P.4]
VY4 TP19 23 24 TP20 [P.4]
LI4
VY5 TP21 25 26 TP4 [P.4]
VY6 TP22 27 28 TP23
VY7 TP24 TP25 AV_DET INPUT_DET
29 30
31 32 TP26
TV_DET
[P.4]
V UV0 TP27 33 34
[P.3] VU V[0..7]
V UV1 TP28 35 36 TP29 SD A [P.2 .3]
V UV2 TP30 37 38 TP31 SCL [P.2 .3]
V UV3 TP32 39 40
41 42 TP33 DECO E [P.2 .3]
V UV4 TP34 43 44 TP35 [P.4]
TUNER _ACK
V UV5 TP36 45 46 TP37 VIDEO_RESET [P.2 .3]
V UV6 TP38 47 48 TP39 AV_SEL [P.4]
V UV7 TP40 49 50 TP42 CVBS_SE L [P.2]
51 52
+12 V TP97 53 54 +12 V
+5VS TP43 55 56 +5VS
VC C TP44 57 58 VCC
+9 V TP45 59 60 +9 V

L22
R1 BE AD
0

TEKCON SLOT 60Pin


Screw Holes
Opti cal Points

OP1 OP2 OP3 OP4 OP5 OP6 OP7


OP OP OP OP OP OP OP

1
5 9 5 9 5 9 5 9
OP8 OP9 OP10 OP1 1 OP1 2 OP1 3 OP1 4
OP OP OP OP OP OP OP 4 8 4 8 4 8 4 8

3 7 3 7 3 7 3 7

2 6 2 6 2 6 2 6

H1 H2 H3 H4

HOLE- V8 HOLE-V8 HOLE-V 8 HOLE-V8

LCD03B
First issue 10 / 03
VIDEO SIGNAL PROCSSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( VIDEO BOARD 2/6)

VCC_A

VCC_ A VCC_A V 33D


PIN5 9 PIN6 9 P IN7 6 PIN5 2
(Bypass Group Delay Circuit) C1 C2 C3 C4
C6
C7 C9 C10
C5 0.22U K C8
+9 V 0.1U K 10U Z 0.1U K 15 00P J 390P K 15 00P J 390P K 0.047U K 0.015U K

R63 R64 R 204 47


560 6.8K R 205 47
L1 OPEN
C 255 180 P J
C45
R6 47
SVVS
[P.3]

3
Q1 R8 47
SVH S
[P.3]
2N3904 R61 2.2K 1 R9 47 [P.3]

+
1 2 S VPEN
R10 NC_R0 603
VF IELD
[P.1]
[P.6] CVB S_INPUT
R7 0 0 R6 8 270 C 200
22 U

2
OPE N RN 1
R69 16 V C1 1 C1 2 47
C11 9 R7 8 R66 R62 R65 5 4 DU V0
OPE N OPEN OPEN 470 470 3.3K 3.3P C Y1 3.3P C 6 3 DU V1
7 2 DU V2
8 1 DU V3
20.25MHZ V3 3D V 33D
5 4 DU V4
VC C C2 54 6 3 DU V5
82P J C16 DU V6 [P.3]

C17
7 2 DUV[ 0..7]

2
DU V7

UV0
UV1
UV2
UV3

UV4
UV5

UV7
8 1

UV6
R 255 +

0.047 U K
10 U RN 2
3

470 16 V V3 3D 47

1
1 Q7
R 262
2

2N3904

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1 Q5
S CART_BLNK
2

2N3906 VCC_ A RN3 47

N.C

VS

C0
C1
C2
C3

C4
C5
C6
C7
CLK5

AVO
XTAL2
XTAL1

INTLC
MSY/HS
ASGF

VSTBY

GNDC
[P.5]

GNDSY

VSUPC
VSUPSY
65 40 Y0 5 4 DY 0

FPDAT/VSYA

FSY/HC/HSYA
100 GNDF Y0
3

66 39 Y1 6 3 DY 1
R 230 75 C13 0.68U K VRT Y1 Y2 DY 2
S_C 67 I2CSEL Y2 38 7 2
[P.4] TP4 6 68 37 Y3 8 1 DY 3
ISGND Y3
3

R 231 75 C18 0.68U K 69 36


S_Y VSUPF VSUPY
R 257 10 K 1 Q8 R 259 [P.4] 70 35 RN4 47
2N3904 C 184 C 185 C14 OPE N VOUT GNDY Y4 DY 4
R 258 75
71
72
CI N
VIN1
U1 Y4
Y5
34
33 Y5
5
6
4
3 DY 5
2

[P.3]
10K
330P J 33 0P J C15 0.68U K 73
74
VIN2
VIN3
VPC3230D Y6
Y7
32
31
Y6
Y7
7
8
2
1
DY
DY
6
7 DY[ 0..7]

CVB S_VD
R2 32 0 C19 0.68U K 75 VIN4 I2C : 0X 8E GNDLLC 30

N.C/FFRSTWI N
76 VSUPAI VSUPLLC 29
[P.4] R11 77 28 R12 0
S VCLK
[P.3]
C 186 GNDAI LLC 1 R13 NC_R 0603
78 27

R 1/CR1I N

R 2/CR2I N
B 1/CB1I N

B 2/CB2I N
VREF LLC 2

VSUPCAP
VCC NC_R0 603 68P J

G1/Y1I N

G2/Y2I N

FFRSTW
79 26

GNDCAP
FB1I N VSUPPA

CLK2 0
1

VSUPD

YCOEQ

FFW E
C20

GNDD
80 25

RESQ

VGAV
ASGF

FFRE
FFOE
TEST

FFI E
AISGND GNDPA
3

SDA
SCL
Q4 + C21
R 260 0 1 2N3904 +9 V C22 C23 C25
SCA RT_FB_EN 15 00P J 0.1U K O PEN
10 U 0.047U K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
[P.6] 16 V VPC3 23X D
2

C27 + C26
R 261 10 U
D15 150 0 .1U K 16 V
1

1N414 8 U3
5 R15
VP

SEL TP47 NC_R0 60 3


15 13 L3 5 3.3NH R14 75
[P.6] FBI 1 FBO C2 8 3 30 P J
TT_BLNK 14 FBI 2
[P.5] SCART_BLUE
C 190 0.047U K 2 VIA1 VOA 12 L3 6 3.3NH R 226 75 C34 0.22U K VB1 VC C
L2
VCC_A
L3
[P.6] TEXT_ B
C 191 0.047U K 6 C3 6 3 30 P J R17 10 0 VIDEO_RESET [P.1]
VIA2

1
[P.5] SCA RT_GREEN
C 192 0.047U K 3 VIB1 VOB 11 L3 7 3.3NH R 227 75 C38 0.22U K VG1
BEAD BE AD
[P.6] TEXT_ G
C 193 0.047U K 7 C39 330P J C30 + C29
VIB2

1
0.22U K C33 47U
100P K C31 L4
[P.5] SCAR T_RED
C 194 0.047U K 4 10 L3 8 3.3NH R 228 75 C40 0.22U K VR1 C35 16V + C3 2
VIC1 VOC

2
[P.6] C 195 0.047U K 8 C41 330P J 15 00P J 0.1U K 22U
TEXT_ R VIC2
GND

16 C37 16 V
IOCNR BE AD

2
R1 6 R1 8 R1 9 R22 390P K
TDA8601T R2 R20 100 [P.1]
NC_R0 603

SDA
9

0 R21 100 SCL [P.1]


10 0 100 100

U4
VCC VC C V3 3D
1000 OHM 3 2
VI N VOUT

1
L29 L39 3.3NH R 233 75 C42 0.22U K VB2
S D_CB_I N DECOE Y/C Output

GND
+ C46
[P.1] R2 3 R3 C47 47 U 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K
75 C4 3 3 30 P J 1K L Disable 0.1U K LD1117-3. 3 16 V

2
1000 OHM C49 C50 C51 C5 2 C5 3
L30 H Enable
SD_CB_GN D
[P.1] 1000 OHM

PIN1 0

PIN2 9

PIN3 6

PIN4 5
SD_Y_I N
L31 L40 3.3NH R 234 75 C44 0.22U K VG2 Q2 R5 1K [P.1]
DECOE
2N3904
[P.1] R2 4 R7
75 C1 18 330P J
1000 OHM 10K
L32
SD_Y_ GND
[P.1] 1000 OHM
L33 L41 R 235 75 C48 0.22U K VR2
SD_C R_I N
3.3NH
[P.1] R2 5
75 C5 4 3 30 P J
1000 OHM
L34
SD _CR_GND
[P.1]

LCD03B
First issue 10 / 03
VIDEO SIGNAL PROCSSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( VIDEO BOARD 3/6)

P3P3 V
U5 A U5B P2P5 V U5 C
1 110 19 5 RAMA0 213 25 5 R AMD0
VB0 DB0 Vs s VDD1 RAMA1 MA0 MD0 R AMD1
2 111 49 34 210 25 2

49
43

27
14
VB1 DB1 Vs s VDD2 MA1 MD1

9
3

1
3 113 77 93 RAMA2 207 24 8 R AMD2 U6
VB2 DB2 Vs s VDD3 RAMA3 MA2 MD2 R AMD3
4 VB3 DB3 114 11 2 Vs s VDD4 12 3 204 MA3 MD3 24 5

VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
6 116 13 4 14 0 RAMA4 203 24 2 R AMD4 RAMA11 35 53 RAMD15
VB4 DB4 Vs s VDD5 RAMA5 MA4 MD4 R AMD5 RAMA10 A1 1 DQ1 5 RAMD14
7 VB5 DB5 117 18 7 Vs s VDD6 17 5 206 MA5 MD5 23 9 22 A1 0 DQ1 4 51
8 118 21 9 20 5 RAMA6 209 23 6 R AMD6 RAMA9 34 50 RAMD13
VB6 DB6 Vs s VDD7 RAMA7 MA6 MD6 R AMD7 RAMA8 A9 DQ1 3 RAMD12
9 VB7 DB7 119 25 1 Vs s VDD8 23 5 211 MA7 MD7 23 2 33 A8 DQ1 2 48
P3P3 V RAMA8 214 23 1 R AMD8 RAMA7 32 47 RAMD11
DY[0 ..7] VY[0..7 ] MA8 MD8 A7 DQ1 1
DY 0 15 121 DG0 4 47 5 VY 0 10 14 RAMA9 217 23 4 R AMD9 RAMA6 31 45 RAMD10
[P.2] DY 1 VG0 DG0 DG1 VY 1 [P.1] PVs s PVd d RAMA1 0 MA9 MD9 RAMD10 RAMA5 A6 DQ1 0 RA MD 9
16 VG1 DG1 122 3 6 24 PVs s PVd d 29 215 MA1 0 MD10 23 8 30 A5 DQ9 44
DY 2 17 124 DG2 2 7 VY 2 39 42 RAMA1 1 220 24 1 RAMD11 RAMA4 29 42 RA MD 8
VG2 DG2 PVs s PVd d MA1 1 MD11 A4 DQ8
DY 3 18 125 DG3 1 RN5 8 VY 3 46 54 RAMA1 2 221 24 4 RAMD12 RAMA3 26 13 RA MD 7
DY 4 VG3 DG3 DG4 VY 4 PVs s PVd d RAMA1 3 MA1 2 MD12 RAMD13 RAMA2 A3 DQ7 RA MD 6
20 VG4 DG4 127 4 5 57 PVs s PVd d 64 218 MA1 3 MD13 24 7 25 A2 DQ6 11
DY 5 21 128 DG5 3 47 6 VY 5 65 69 25 0 RAMD14 RAMA1 24 10 RA MD 5
DY 6 VG5 DG5 DG6 VY 6 PVs s PVd d MD14 RAMD15 RAMA0 A1 DQ5 RA MD 4
22 VG6 DG6 129 2 7 74 PVs s PVd d 80 MD15 25 4 23 A0 DQ4 8
DY 7 23 130 DG7 1 RN 6 8 VY 7 85 90 RAMA12 20 7 RA MD 3
VG7 DG7 PVs s PVd d RAMA13 BA0 DQ3 RA MD 2
DUV[0 ..7] V UV[0..7 ] 96 PVs s PVd d 101 21 BA1 DQ2 5
DU V0 30 13 2 DR 0 4 5 V UV0 10 5 109 R26 0 223 22 5 4 5 R RASn 4 RA MD 1
[P.2] DU V1 VR0 DR0 DR 1 [P.1] PVs s PVd d MCLKFB mRASn 33 DQ1
31 VR1 DR1 13 3 3 47 6 V UV1 11 5 PVs s PVd d 120 mCASn 22 6 3 6 R CASn R27 1K 19 CS DQ0 2 RA MD 0
DU V2 32 13 5 DR 2 2 7 V UV2 12 6 131 RC LK R28 0 229 22 7 2 7 RWEn P3P3V RC LK 38
DU V3 VR2 DR2 DR 3 RN 7 8 V UV3 PVs s PVd d MCLK mWEn RN 8 P3P3V CL K
33 VR3 DR3 13 6 1 13 7 PVs s PVd d 143 1 8 37 CKE NC/RFU 40
DU V4 35 13 8 DR 4 4 5 V UV4 14 7 165 PW1230 36
DU V5 VR4 DR4 DR 5 47 V UV5 PVs s PVd d R RASn NC
36 VR5 DR5 13 9 3 6 17 1 PVs s PVd d 180 18 RAS
DU V6 37 14 1 DR 6 2 7 V UV6 18 9 200 R CASn 17
DU V7 VR6 DR6 DR 7 RN 9 8 V UV7 PVs s PVd d RWEn CAS
38 VR7 DR7 14 2 1 19 3 PVs s PVd d 208 16 WE
20 2 PVs s PVd d 216 U5 D
70 OHM 21 2 224 P3P3V 39
[P.2] PVs s PVd d UDQM
11 102 DC LK R29 V CLK [P.1] 22 2 230 R30 10K 48 16 8 15

VSSQ
VSSQ
VSSQ
VSSQ
S VHS SVHS DCL K PVs s PVd d TDO MCUA0 LDQM

VSS
VSS
VSS
[P.2] SVVS 12 103 DVS R31 47 VVS [P.1] 22 8 237 R32 10K 50 16 9
[P.2] SVVS DVS DH S R33 47 [P.1] PVs s PVd d R34 10K TCK MCUA1
S VCLK 13 SVCLK DHS 10 4 VHS 23 3 PVs s PVd d 243 51 TDI MCUA2 17 0
[P.2] S VCLK 25 14 5 DE N R35 47
DECOE [P.1] 24 0 249 R36 10K 52 17 2
PVCLK DEN PVs s PVd d TMS MCUA3

6
12
46
52
28
41
54
[P.2] S VPEN 26 10 6 TP4 8 24 6 256 R37 10K 53 17 3 HY57V641620HGT- 6
[P.2] CREF DENG PVs s PVd d TRSTN MCUA4
SVVS 27 PVVS DENB 10 7 TP4 9 25 3 PVs s MCUA5 17 4 4M*16 SDRAM
[P.2] S VHS 28 10 8 DP EN R38 47 V PEN [P.1] 19 7 AVDD2 R39 0 43 17 6
PVHS DENR DPAVd d R40 0 I2CA1 MCUA6
19 6 DPAVs s DPDVd d 199 44 I2CA2 MCUA7 17 7
19 8 DPDVs s
70 15 6 TP5 0 58 AVDD1 [P.1] SCL R41 0 45 17 8
DGB0 ADR TP5 1 MPDVdd [P.1] R42 0 SCL MCUD0
71 DGB1 ADG 153 59 MPDVs s MPAVd d 60 SDA 47 SDA MCUD1 17 9
72 150 TP5 2 61 18 1 P3P3V
DGB2 ADB MPAVs s A VD25 MCUD2
73 DGB3 ADDVd d 149 40 XTAL I MCUD3 18 2
75 C55 0.01U K 14 8 16 3 18 3
DGB4 ADDVs s ADAVd d Y2 1 0MHZ MCUD4
76 DGB5 VREFI N 16 1 16 4 ADAVs s ADGVd d 166 41 XTAL O MCUD5 18 4
78 DGB6 VREFOUT 16 2 16 7 ADGVs s MCUD6 18 5
79 159 R4 3 27 0 15 1 A VD33 R44 0 56 18 6 C56 C57 C58 C5 9 C60 C6 1 C6 2
DGB7 RSET C63 0.01U K A VD33 AVD33B TEST MCUD7 0.1U K 0 .1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K
COMP 16 0 15 2 AVS33B AVD33G 154
81 15 5 157 R45 2M 55 19 0
DGG0 C64 2 AVS33G AVD33R RESETn MCUCS
82 DGG1 1 10 U 15 8 AVS33R MCUWR 19 1
R4 6 0 16 V P3P3 V
+

83 DGG2 MVE 20 1 MCUCMD 192


84 14 6 R4 7 0 PW1230 C65 C66 18 8
DGG3 CGMS TP5 3 MCURDY
86 DGG4 TESTCL K 14 4
87 18P J 18P J PW1230
DGG5 DI _RESET
88 DGG6
89 DGG7 I2C : 0X64
91 DGR0
92 [P.1] VIDEO_RESET 0 R4 8
DGR1
94 DGR2
95 DGR3
97 DGR4
98 DGR5
99 V 33D P3P3V
DGR6 L5
100 DGR7
P2P5 V
66 L6
DGHS 42 OHM
67 DGVS A VD25

1
68 DGCL K
42 OHM + C67

1
PW1230 C69 C70 C71 10U C68
+ 16V 0.1U K

2
22U 0.1U K 0.01U K

2
16V
P3P3 V
L7
A VD33
P2P5 V 42 OHM VC C U7
P2P5V
C74
C73 3 VI N VOUT 2
0.1U K 0.01U K

GND

1
C7 8 C7 9 C8 0 C81 C8 2 C83 C8 4 C8 5 R49 + C72
0 .1U K 0 .1U K 0 .1U K 0 .1U K 0.1U K 0.1U K 0 .1U K 0 .1U K C7 5 LM317 M 681F 47 U C76
P2P5 V

1
0.1U K 16V 0.1U K

2
P3P3 V L8
AVDD2

1
R50
42 OHM 681F + C77
10U
C8 8 C8 9 C9 0 C91 C9 2 C93 C9 4 C9 5 C96 C97 C98 C99 C1 00 C1 01 C87 16 V
C86

2
0 .1U K 0 .1U K 0 .1U K 0 .1U K 0.1U K 0.1U K 0 .1U K 0 .1U K 0 .1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K
0.1U K 0.01U K

L9
AVDD1
42 OHM
C10 4 C10 5 C10 6 C1 07 C10 8 C1 09 C1 10 C1 11 C11 2 C1 13
0 .1U K 0 .1U K 0 .1U K 0.1U K 0 .1U K 0 .1U K 0 .1U K 0 .1U K 0.1U K 0.1U K C 103
C1 02
0.1U K 0.01U K

LCD03B
First issue 10 / 03
VIDEO SIGNAL PROCSSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( VIDEO BOARD 4/6)

VC C

C 114 R51
J6 0.1U K 68K [P.1]
1000 OHM AV_SEL
C1 17 10U 16V Q3
TP54 5 5 6 6 TP5 5 CVBS_ IN L10 R52 100 2N3904

9
HC405
Bottom View

+
+5VS R53 R55 1K R54 0 CV BS 5
68K 4 [P.2]
3 3 4 4 3 CVB S_VD
TP5 6 R5 6 1K
LI1
[P.1] VI DEO_I N
[P.4]
5 6 74 3

16

6
7
8
1 1 2 2 TP5 7 R5 7 1K [P.1] VCC
RI 1
D1 D2 R60 DN 1
3 4 R58 R59 BAV99 3 AV_SEL OUTPUT
22K 22 K 75 C 115 + C1 16
0.1U K LOW CVBS

TZMC5V1

TZMC5V1
10U
16V HIGH TV
1 2
TZM C5V1 TZMC5V1 1 2 U2 C
VC C
D3 D4 2N3904
C1 89 R3 16
2N3906
J7 0 .1U K 68K
1000 OHM
3 TP58 L11 R3 18 Q305
Y
Bottom View C1 20 10U 16 V 100 2N3904

+
C 127 R3 17 R 311 0 [P.2]
1 O PEN 68K S_Y
. +5VS
G1 TP41 R 319 1K
S1 G1 TP59 DN 2
S1 G1 BAV99
R71
1 3 . 2
G2 75

4
C
1000
2 4 L12
OHM
VC C
G3 221 028900 1 C1 24 10U 16 V

+
C 128
O PEN +5VS C1 22 R72
INPUT_DET DN 3 0 .1U K 68 K
BAV99
R82 R74 Q6
100 2N3904
75 R76 R77 0
S_C
[P.2]
68 K

R80 1K

VCC

Top View (ST) C 130 R8 8 [P.1]


0.1U K 68K
14 2 CVBS_ SEL
+9V L20 42 OHM
R 253 560 C 133 10U R9 0 Q9

16
11
1 16V 100 2N3904
13 + C 125 R94 R95 0 TV 12
U2A
10 U 14 [P.4]
13 VI DEO_I N
16 V 68 K [P.5] S CART_CVBS
74HC4053
+9V R9 7 1K
+9 V

6
7
8
J8
R 249 CVBS_SEL Output
L1 3 1000 OHM
TP6 1 1 2 TP62 22
3 4 TP63 R89 100 LOW CVBS_VD
TP6 4 5 6 TP65 R91 100
7 8 TP66 R73 NC_R0 60 3 HIGH SCART_CVBS
TP67 T UNER_DET
9 10 TUNE R_ACK
11 12 TP68 SCL_TV R 254 + C 126
13 14 TP69 SDA_TV 470 10U
16 V

R98 100 Q2 2
2N3904
Q2 3 R92 68
2N3906 VI DEO_OUT
R2 50 [P.5]
V 33D VC C 1K

[P.1]
R 108

R 107

RI 2
[P.6]
LI2
[P.1]
1

Q1 1 Q1 0
3.3K

3.3K

R109 470
2 3 3 2 [P.5]
SCL S CART_ROUT
R110 470
1

[P.1] SCART_L OUT


[P.5]
Q13 BSN2 0 BSN2 0 Q1 2

2 3 3 2 C 196 C 197 C 198 C 199


SDA
O PEN O PEN OPE N OPE N
[P.1]
BSN 20 BSN 20

LCD03B
First issue 10 / 03
VIDEO SIGNAL PROCSSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( VIDEO BOARD 5/6)

+5VS VC C
DN 6
BAV99
C 140
0.1U K R1 13
[P.4] 68 K
R 163 0
S CART_ROUT
L1 4 1000 OHM
R 164 0 R 114 Q1 4
SCART_L OUT SCAR T_CVBS_I N
C1 43 10U 16V 2N390 4

+
10 0
[P.4] R19 4 R 195 J9 [P.5] R 115 R1 16 47
C 141 C1 42 R1 17 S CART_CVBS
100K 100K TP70 1 75 68 K
10 00P J 10 00P J 2 TP71 R 165 0 [P.5] [P.2]
D5

D6
SCART_ AR_I N
TP72 3
4 TP7 3 R 118 1K
5
TZM C5V1

TZM C5V1

6 TP74 R 166 0 [P.5]


SCA RT_AL_I N
TP75 7 R1 19 1K [P.1]
SCAR T_BLUE_I N SC ART_AL_I N LI4
8 TP76 R 167 0 SCA RT_SWITCH
[P.5] 9 [P.5]
10 CLK_OUT TP7 7 D13 [P.5] D9 TZMC5V1 D10 TZMC5V1
TP78 11 R1 20 1K [P.1]
D7

D8

SCART_G REEN_I N 12.4~14 .1V SCART _AR_I N RI 4


12 DAT A_OUT TP7 9
[P.5] 13 [P.5]
14 R 121 R1 22 D11 TZMC5V1 D12 TZMC5V1
TZMC5V1

TZMC5V1

TP80 15 22K 22K


SCART_RE D_I N TP81 R 168 0
16
S CART_BLNK
[P.5] 17
18

D1 4
R 125 [P.2]
TP82 19
20 TP83 SCART _CVBS_I N +5VS
21 75

TZMC5V1
[P.5] DN 9
BAV99

C 154
1000 OHM O PEN
DN 8 +5VS
L1 6
SCAR T_BLUE_I N S CART_BLUE
[P.2]
C 145 10U 16V

+
BAV9 9 [P.5] R1 26
L1 5
75
VI DEO_OUT
1000 OHM
[P.4]

+5VS

DN 10
BAV99

C 155
1000 OHM O PEN
L1 7
REEN_I
SCART_G
N SCA RT_GREEN
[P.2]
C 147 10U 16V

+
[P.5] R1 32

75

Mode1 Mode2
+5VS
8.6- 12V 0 0 Auto
DN 11
3.5- 8.6V 1 0 16:9 BAV99
+5VS
0-3 .5V 1 1 Manual
C 156
+5VS R 224 R2 25 O PEN
1000 OHM
L1 8 [P.2]
SCART_RE D_I N SCAR T_RED
C 149 10U 16V

+
10K 10K [P.5] R1 38
R21 6 R 217
4.3K 10K 75
4

R21 5 U15 [P.6]


SCART_M ODE1
10K 0V~4. 85V
100K
V+

3 1 R22 0 Q1
SCA RT_SWITCH IN1+ OUT1
2
IN1-
2N3904 SCART_M ODE2 [P.6]
[P.5] 3.49V
5 7 R22 1 100K Q16 R1 27 0 [P.1]
IN2+ OUT2 TV_DET
6 2N3904
1.40V IN2-
10 8 R 222 R2 23
R 245 R21 8 R 219 9 IN3+ OUT3
IN3-
High Active
NC_R0 603

NC_R0 603

6.8K 10K 3.9K


12 14
13 IN4+ OUT4
IN4-
GND

LMV3 24M
11

LCD03B
First issue 10 / 03
VIDEO SIGNAL PROCSSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( VIDEO BOARD 6/6)

+2.5V

+3. 3VDAC
C 168 LANG3 [P.6]
+2. 5VDAC +2. 5VDAC +2. 5V LANG2 [P.6]
C 167 0 .1U K [P.6]

R 189
R 190
R 191
R 192
R 193
0 .1U K LANG1
R 171 R1 72
4.7K 4.7K C 169 C 170 C 171
U1 3 +3. 3VDAC

NC_R 0603

NC_R 0603
1 8 0.1U K +3. 3VDAC 0.1U K 0.1U K
NC VCC

0
2 7
3 NC WP 6 EE_SCL +3. 3VDAC
4 NC SCL 5 EE_SDA U14
GND SDA 1 52 L ANG3
2 P 0.0 P 1.7 51 L ANG2
AT24 C02 P 0.1 P 1.6 LCB
3 50 R1 74 NC_R 0603
R2 39 0 4 P 0.2 P 1.5 49 I N FO R 175 0
R2 40 0 5 P 0.3 P 1.4 48 LIS T R1 76 NC_R 0603 +3. 3V
6 P 0.4 P 1.3 47 I2C_EN R 177 0
7 P 0.5 P 1.2 46 RGB_G AI N R1 78 NC_R 0603
8 P 0.6 P 1.1 45 L ANG1
9 P 0.7 P 1.0 44 R 143 R14 4 R1 45 R1 46
10 VDD 2.5 VDD 3. 3 43 220 68 68 68
11 VSS VSS 42
[P.4] C 172 0.1U K 12 VDD 3.3 VDD 2. 5 41 TT_FSB R1 79 0 FSB Q18
CVBS _INPUT CVBS BLANK/COR
13 40 TT _B R1 80 0 B LUE 2N3904
R 181 14 VDDA 2. 5 B 39 TT _G R1 82 0 GREEN R14 8 47 [P.2]
VSSA G TT_BLNK
NC_R0 603 15 38 TT_ R R1 83 0 RE D
16 P 2.0 R 37 R1 49
17 P 2.1 VDDA 2. 5 36 330
18 P 2.2 VSSA 35 R15 0 10 [P.2]
P 2.3 XTAL 1 TEXT_ B
19 34
20 HS/SSC XTAL 2 33 TT_ RSTn B LUE 2N390 6
21 VS RST- 32 +3.3V Q2 1 R15 1 10 [P.2]
TP8 4 P 3.0 P 4.3 Y3 TEXT_ G
TT_STAR T 22 31 R25 2
P 3.1 P 4.2 2N3906
[P.1] SCL R 243 0 23
P 3.2 VDD 3. 3
30 GREEN
[P.1] R 244 0 24 29 R 184 Q2 0 R15 2 10 [P.2]
SDA P 3.3 VSS TEXT_R
25 28 0 10K
26 P 3.4 P 3.7 27 6MHZ RE D 2N3906
P 3.5 P 3.6 R23 6 Q19
C 177 C1 78

NC_R0 60 3
SDA555 xF L 33P J 33P J
+ C 176
I2C : 0X60 10 U
16 V

+3. 3VDAC
SCA RT_FB_EN
[P.2] SVVS R 185 0 R 157 R1 58 R1 59 C 161

NC_R0 60 3

NC_R0 60 3
0 .1U K U11
[P.2] S VHS R 186 0 16
VDD P0 0
4 LANG1 [P.6]
3.3K 5 LANG2 [P.6]
[P.1] 14 P0 1 6 [P.6]
SCL SCL P0 2 LANG3
[P.1] SDA 15
SDA P0 3
7 SCA RT_FB_EN [P.2]
9
13 P0 4 10 [P.4]
IN T P0 5 T UNER_DET
11 SCART_M ODE1 [P.5]
1 P0 6 12 [P.5]
A0 P0 7 SCART_M ODE2
2
3 A1 8
U9 A2 GND
VCC +3. 3VDAC +3.3V R 160 R1 61 R1 62 PCA9554P W
L19
3 VI N VOUT 2
I2C : 0X48
NC_R 0603

BE AD
GND

+ C 150
C1 51 47U C 152 + C1 53 3.3K 3.3K
0 .1U K 16 V 0 .1U K 10 U
LD1117-3. 3
16 V
1

U1 2
VCC +2. 5VDAC +2.5V
3 2 L21
VI N VOUT
BE AD
GND

R 169 + C 162 + C1 63
C1 64 LM317 M 681F 47 U C1 65 10 U
0 .1U K 16 V 0 .1U K 16 V
1

R1 70
681F + C 166
10U
16 V

+3. 3VDAC

PIN1 1 P IN 30 PIN4 4

C17 3 C17 4 C1 75
0 .1U K 0 .1U K 0.1U K

LCD03B
First issue 10 / 03
VIDEO SIGNAL PROCSSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( VIDEO BOARD 1/6, 20”BI)

J1
1 2 TP 2 L23 1000 OHM SD_Y_I N [P. 2]
[P. 3] VCL K
TP 1 3 4 TP 98 L24 1000 OHM SD_Y_ GN D [P. 2]
5 6 TP 6 L25 1000 OHM SD_CB _IN [P. 2]
[P. 3] VVS
TP 3 7 8 TP 99 L26 1000 OHM SD_CB _GND [P. 2]
[P. 3] VH S
TP 5 9 10 TP 9 L27 1000 OHM SD_ CR_IN [P. 2]
[P. 3] VPEN
TP 7 11 12 TP 10 0 L28 1000 OHM SD _ CR_GND [P. 2]
[P. 2] VFI EL D
TP 8 13 14 Q26
15 16 TP 11
RI 1
[P. 4] +9V
GY 0 TP 10 17 18 TP 13 [P. 4] 2N3906
2 3 [P. 4]
LI1 AV_SEL
[P. 3] GY[0.. 7]
GY 1 TP 12 19 20 TP 15
RI 2
[P. 4] R320
GY 2 TP 14 21 22 TP 17
LI2
[P. 4]
GY 3 TP 16 23 24 TP 18
RI 4
[P. 5]

1
25 26 TP 20
LI4
[P. 5]
GY 4 TP 19 27 28 TP 4
10K
GY 5 TP 21 29 30 TP 23
INPUT_D ET
[P. 2] R322
GY 6 TP 22 31 32 TP 25 AV_ DET R1 0 1K
GY 7 TP 24 33 34 TP 26
TV_DET
[P. 4] R334
35 36
BU 0 TP 27 37 38 TP 29 SDA [P .2.3] R321

3
[P. 3] BU [0..7] BU 1 TP 28 39 40 TP 31 SC L [P .2.3]
BU 2 TP 30 41 42 AV_ SEL_I N 1 Q17 10K
BU 3 TP 32 43 44 TP 33 DEC OE [P .2.3] 2N3904
45 46 TP 35 T UNER_ACK (old net: TT_ST ART) [P. 4] 1K
R194

2
BU 4 TP 34 47 48 TP 37 VIDE O_RESET
BU 5 TP 36 49 50 TP 39 AV_ SEL_I N [P .2.3] 10K
BU 6 TP 38 51 52 TP 42 YC _SEL_I N
BU 7 TP 40 53 54
55 56 TP 10 5 RV 4
[P. 3] RV [0..7] RV 0 TP 10 1 57 58 TP 10 6 RV 5
RV 1 TP 10 2 59 60 TP 10 7 RV 6
RV 2 TP 10 3 TP 10 8 RV 7 +9V Q24
61 62
RV 3 TP 10 4 63 64 [P. 3] 2N3906
2 3 [P. 2]
RV [0..7] CVBS_SEL
65 66 R195
+12V TP 97 67 68 +12V
69 70

1
+5VS TP 43 71 72 +5VS
73 74 10K
VCC TP 44 75 76 VCC R196 R335
77 78 1K
+9V TP 45 79 80 +9V
2050044080 10K
R197

3
YC _SEL_I N 1 Q25
2N3904
R198
1K

2
10K

L22
TEKCON SLOT 80Pin BEAD

S crew Holes
20L0BI
VIDEO BOARD
48.M 2306 .A00
1

5 9 5 9 5 9 5 9

4 8 4 8 4 8 4 8
Optical Points
3 7 3 7 3 7 3 7

2 6 2 6 2 6 2 6 OP1 OP2 OP3 OP4 OP5 OP6 OP7


OP OP OP OP OP OP OP
H1 H2 H3 H4

HO LE-V 8 HO LE-V 8 HO LE-V 8 HO LE-V 8

OP8 OP9 OP10 OP11 OP12 OP13 OP14


OP OP OP OP OP OP OP

LCD03B
First issue 10 / 03
VIDEO SIGNAL PROCSSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( VIDEO BOARD 2/6, 20”BI)

VCC VCC _A

R6 3 VC C_ A VC C_ A V33 D
R6 4 PI N5 9 PI N69 PIN76 PI N5 2
6.8K C6
C1 C2 C3 C4 C5 0.22U K C7 C8 C9 C1 0
56 0 0.1U K 10 U Z 0.1U K 1500 P J 390P K 1500 P J 390P K 0.047U K 0.015U K
L1 NC _L1206
C199 180P J
C4 5
Q1 R204 47
2N3904 R336 2.2K R205 47

+
[P. 6] CVBS_INPU T R7 0 0 R6 8 27 0
22 U
C200 R6 47
SVVS
[P. 3]
R6 9 R331 R6 2 NC_C0603 16V R8 47 [P. 3]
SVHS
C119 R330 R9 47
SVPE N
[P. 3]
R1 0 NC_R0603
VFIELD
[P. 1]
47 0 47 0 RN1

NC_C0603

NC_R0603

NC_R0603
R6 5 C1 1 C1 2 47
3.3K 5 4 DU V0
C191 3.3P C Y1 3.3P C 6 3 DU V1
7 2 DU V2
82 PJ 8 1 DU V3
20.25 MH Z V33 D V33 D
5 4 DU V4
6 3 DU V5

C1 7
C1 6 7 2 DU V6
DUV [0..7]
[P. 3]

UV 0
UV 1
UV 2
UV 3

UV 4
UV 5

UV 7
[P. 4] DU V7

UV 6
8 1
R230 75 C1 3 0 .68U K
S_ C +
10 U RN2

0.047U K
R231 75 C1 8 0 .68U K 16V V33 D 47
S_Y
[P. 4] C184 C185

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VCC
330P J 330PJ VC C_ A RN3 47

XTAL 2
XTAL 1

CLK 5

MSY/H S

GNDS Y
ASG F

N.C

VS

C0
C1
C2
C3

C4
C5
C6
C7
AVO
INTLC
VSTBY

GNDC
VSUPC
VSUPSY
65 40 Y0 5 4 DY 0

FPDAT/VSYA

FSY/HC/HSYA
GNDF Y0
[P. 4] 66 VRT Y1 39 Y1 6 3 DY 1
R342 R232 0 C1 9 0 .68U K 67 38 Y2 7 2 DY 2
CVBS_V D I2CSEL Y2
47 0 TP 46 68 37 Y3 8 1 DY 3
R1 1 ISGND Y3
69 VSUPF VSUPY 36
Q29 NC _R0603 70 35 RN4 47
C 186 VOUT GNDY Y4 DY 4
[P. 5] 68 PJ
71
72
CI N
VIN1
U1 Y4
Y5
34
33 Y5
5
6
4
3 DY 5
[P. 3]
SCART _BLN K
R343
Q30
2N3906
2N3904 C1 5 0 .68U K 73
74
VIN2
VIN3
VPC3230D Y6
Y7
32
31
Y6
Y7
7
8
2
1
DY
DY
6
7 DY[0..7 ]
75 VIN4 I2C : 0X8E GNDLLC 30

N.C/FFRSTWI N
R341 76 29
VSUPAI VSUPLLC
77 GNDAI LLC1 28 R1 2 0
SVC LK
[P .3 ]
NC_R0603 78 27 R1 3 NC_R0603

R1/CR1I N

R2/CR2I N
B1/CB1I N

B2/CB2I N

GNDCA P
VREF LLC2

VSUPCAP
G1/Y1I N

G2/Y2I N
75

FFRSTW
79 26

YCOE Q
FB1I N VSUPPA

VSUPD

CLK20
ASG F
Q28 C2 0

GNDD

FFR E
80 25

FFWE
RESQ

VGAV

FFOE
TEST

FFI E
SD A
AISGND GNDPA

SC L
10K + C2 1
R340 C2 2 C2 3 C2 5
R339 2N3904 10 U 0.047U K 1500 P J 0.1U K 22 P J

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
16V VPC 323XD

VCC
10K

Q27 R1 5
SCART _F B_EN R338 0 NC _R0603
+9V
2N3904

R337 VCC VC C_ A
L2 L3
C2 7 + C2 6 R1 7 10 0 VIDE O_RESET [P. 1]
10 U
0.1U K 16V BEAD BEAD
1

D1 5 15 0 U3 C3 0 + C2 9
5 0.22U K C3 3 47U
L4
VP

SEL TP 47 C3 5 100P K 16V C3 1 + C3 2


1N4148 15 13 L35 R1 4 75 1500 PJ 0.1U K 22U
FBI 1 FBO
[P. 6] TT_BLNK 14 FBI 2 3.3NH
C2 8 330PJ C3 7 16V
BEAD
390P K
[P. 5] SCART _BLU E 1U Z C193 2 VIA1 VOA 12 L36 R226 75 C3 4 0 .22U K VB1 R2 0 10 0 SDA [P. 1]
[P. 6] TEX T_ B 1U Z C194 6 VIA2 3.3NH
C3 6 330PJ R2 1 10 0 SC L [P. 1]
[P. 5] SCART_GREE N 1U Z C195 3 VIB1 VOB 11 L37 R227 75 C3 8 0 .22U K VG1
[P. 6] TEX T_ G 1U Z C196 7 VIB2 3.3NH
C3 9 330PJ
U4
[P. 5] SC AR T_ RE D 1U Z C197 4 VIC1 VOC 10 L38 R228 75 C4 0 0 .22U K VR 1 VCC VCC V33 D
[P. 6] TE XT _R 1U Z C198 8 C4 1 330PJ 3 2

VB2
VIC2 3.3NH VI N VOUT
GND

IOCNR 16 DECO EY/C Output

GND
R1 6 R1 8 R1 9 R2 2 + C4 6
L Disable C4 7
TDA8601T R2 L29 1000 OHM 3.3NH R3 47 U 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K
NC_R0603

R233 75 C4 2 0 .22U K 1K 0.1U K 16V


SD_CB _IN LD1117-3. 3
0
[P. 1] R2 3 L39 H Enabl e C4 9 C5 0 C5 1 C5 2 C5 3

1
10 0 10 0 10 0 C4 3 330P J

[P. 1] 1000 OHM


VG2

PI N1 0

PI N2 9

PI N3 6

PI N4 5
SD_CB _GND L30 75 Q2 R5 1K
DEC OE
[P. 1]
2N3904
1000 OHM 3.3NH R7
SD_Y_I N L31 L40 R234 75 C4 4 0 .22U K 20L0BI
R2 4 10K
[P. 1] C118 330PJ
VIDEO BOARD
48.M 2306 .A00
[P. 1] 1000 OHM
VR 2

SD_Y_ GN D L32 75

[P. 1] 1000 OHM 3.3NH


SD_ CR_I N L33 L41 R235 75 C4 8 0 .22U K
R2 5
C5 4 330P J

[P. 1] 1000 OHM


SD _ CR_GND L34 75

LCD03B
First issue 10 / 03
VIDEO SIGNAL PROCSSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( VIDEO BOARD 3/6, 20”BI)

P3P3V
U5 A BU [0..7] U5 B U5C
P2P5V
1 VB0 DB0 110 DB 0 4 5 BU 0 [P. 1] 19 Vss VDD1 5 RAM A0 213 MA0 MD0 255 RAM D0
2 111 DB 1 3 47 6 BU 1 49 34 RAM A1 210 252 RAM D1

49
43

27
14
VB1 DB1 Vss VDD2 MA1 MD1

9
3

1
3 113 DB 2 2 7 BU 2 77 93 RAM A2 207 248 RAM D2 U6
VB2 DB2 DB 3 RN 10 8 BU 3 Vss VDD3 RAM A3 MA2 MD2 RAM D3
4 114 1 112 123 204 245

VD D
VD D
VD D
VB3 DB3 Vss VDD4 MA3 MD3

VDDQ
VDDQ
VDDQ
VDDQ
6 116 DB 4 4 5 BU 4 134 140 RAM A4 203 242 RAM D4 RA MA11 35 53 RAMD 15
VB4 DB4 DB 5 47 BU 5 Vss VDD5 RAM A5 MA4 MD4 RAM D5 RA MA10 A11 DQ15 RAMD 14
7 VB5 DB5 117 3 6 187 Vss VDD6 175 206 MA5 MD5 239 22 A10 DQ14 51
8 118 DB 6 2 7 BU 6 219 205 RAM A6 209 236 RAM D6 RAM A9 34 50 RAMD 13
VB6 DB6 DB 7 RN 11 8 BU 7 Vss VDD7 RAM A7 MA6 MD6 RAM D7 RAM A8 A9 DQ13 RAMD 12
9 VB7 DB7 119 1 251 Vss VDD8 235 211 MA7 MD7 232 33 A8 DQ12 48
P3P3V RAM A8 214 231 RAM D8 RAM A7 32 47 RAMD 11
DY[0..7 ] GY[0.. 7] MA8 MD8 A7 DQ11
DY 0 15 121 DG0 4 5 GY 0 10 14 RAM A9 217 234 RAM D9 RAM A6 31 45 RAMD 10
VG0 DG0 PVss PVdd MA9 MD9 A6 DQ10
[P. 2] DY 1 16 VG1 DG1 122 DG1 3 OPEN 6 GY 1 [P. 1] 24 PVss PVdd 29 RA MA10 215 MA10 MD10 238 RAMD 10 RAM A5 30 A5 DQ9 44 RAM D9
DY 2 17 124 DG2 2 7 GY 2 39 42 RA MA11 220 241 RAMD 11 RAM A4 29 42 RAM D8
DY 3 VG2 DG2 DG3 RN 5 8 GY 3 PVss PVdd RA MA12 MA11 MD11 RAMD 12 RAM A3 A4 DQ8 RAM D7
18 VG3 DG3 125 1 46 PVss PVdd 54 221 MA12 MD12 244 26 A3 DQ7 13
DY 4 20 127 DG4 4 5 GY 4 57 64 RA MA13 218 247 RAMD 13 RAM A2 25 11 RAM D6
DY 5 VG4 DG4 DG5 OPEN 6 GY 5 PVss PVdd MA13 MD13 RAMD 14 RAM A1 A2 DQ6 RAM D5
21 VG5 DG5 128 3 65 PVss PVdd 69 MD14 250 24 A1 DQ5 10
DY 6 22 129 DG6 2 7 GY 6 74 80 254 RAMD 15 RAM A0 23 8 RAM D4
DY 7 VG6 DG6 DG7 RN 6 8 GY 7 PVss PVdd MD15 RA MA12 A0 DQ4 RAM D3
23 VG7 DG7 130 1 85 PVss PVdd 90 20 BA0 DQ3 7
96 101 RA MA13 21 5 RAM D2
DU V[0..7 ] RV [0..7] PVss PVdd BA1 DQ2
DU V0 30 132 DR0 4 5 RV 0 105 109 R2 6 0 223 225 4 5 RR ASn 4 RAM D1
VR0 DR0 PVss PVdd MCLKFB mRASn 33 DQ1
[P. 2] DU V1 31 VR1 DR1 133 DR1 3 OPEN 6 RV 1 [P. 1] 115 PVss PVdd 120 mCASn 226 3 6 RC ASn R2 7 1K 19 CS DQ0 2 RAM D0
DU V2 32 135 DR2 2 7 RV 2 126 131 RC LK R2 8 0 229 227 2 7 RW En P3P3V RC LK 38
DU V3 VR2 DR2 DR3 RN 7 8 RV 3 PVss PVdd MCLK mWEn RN 8 P3P3V CLK
33 VR3 DR3 136 1 137 PVss PVdd 143 1 8 37 CKE NC/RFU 40
DU V4 35 138 DR4 4 5 RV 4 147 165 PW1230 36
DU V5 VR4 DR4 DR5 OPEN 6 RV 5 PVss PVdd RR ASn NC
36 VR5 DR5 139 3 171 PVss PVdd 180 18 RAS
DU V6 37 141 DR6 2 7 RV 6 189 200 RC ASn 17
DU V7 VR6 DR6 DR7 RN 9 8 RV 7 PVss PVdd RW En CAS
38 VR7 DR7 142 1 193 PVss PVdd 208 16 WE
202 PVss PVdd 216 U5D
212 224 P3P3V 39
PVss PVdd UDQM
[P. 2] 11 102 DC LK R2 9 0 VCLK [P. 1] 222 230 R3 0 10K 48 168 15

VSSQ
VSSQ
VSSQ
VSSQ
SVHS SVHS DCLK PVss PVdd TDO MCUA0 LDQM

VSS
VSS
VSS
[P. 2] SVVS 12 SVVS DVS 103 DVS R3 1 47 VVS [P. 1] 228 PVss PVdd 237 R3 2 10K 50 TCK MCUA1 169
[P. 2] SVC LK 13 SVCLK DHS 104 DHS R3 3 47 VHS [P. 1] 233 PVss PVdd 243 R3 4 10K 51 TDI MCUA2 170
[P. 2] SVC LK 25 PVCLK DEN 145 DEN R3 5 47
DEC OE[P. 1] 240 PVss PVdd 249 R3 6 10K 52 TMS MCUA3 172

6
12
46
52
28
41
54
[P. 2] SVPE N 26 CREF DEN G 106 TP 48 246 PVss PVdd 256 R3 7 10K 53 TRSTN MCUA4 173 HY 57 V641620HGT -6
[P. 2] SVVS 27 PVVS DEN B 107 TP 49 253 PVss MCUA5 174 4M*1 6 SDRAM
[P. 2] SVHS 28 PVHS DEN R 108 D PEN R3 8 47 VPEN [P. 1] DPAVdd 197 AV DD2 R3 9 0 43 I2CA1 MCUA6 176
196 199 R4 0 0 44 177
DPAVss DPDVdd I2CA2 MCUA7
198 DPDVss
70 DGB0 ADR 156 TP 50
MPDVdd 58 AV DD1 [P. 1] SCL R4 1 0 45 SCL MCUD0 178
71 DGB1 ADG 153 TP 51 59 MPDVss MPAVdd 60 [P. 1] SDA R4 2 0 47 SDA MCUD1 179
72 150 TP 52 61 181 P3P3V
DGB2 ADB MPAVss AV D2 5 MCUD2
73 DGB3 ADDVdd 149 40 XTALI MCUD3 182
75 C5 5 0 .01U K 148 163 183
DGB4 ADDVss ADAVdd Y2 10M HZ MCUD4
76 DGB5 VREFIN 161 164 ADAVss ADGVdd 166 41 XTALO MCUD5 184
78 DGB6 VREFOUT 162 167 ADGVss MCUD6 185
79 159 R4 3 27 0 151 AV D3 3 R4 4 0 56 186 C5 6 C5 7 C5 8 C5 9 C6 0 C6 1 C6 2
DGB7 RSET C6 3 0 .01U K AV D3 3 AVD33B TEST MCUD7 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K
COMP 160 152 AVS33B AVD33G 154
81 155 157 R4 5 2M 55 190
DGG0 C6 4 2 AVS33G AVD33R RESETn MCUCS
82 DGG1 1 1 0U 158 AVS33R MCUWR 191
R4 6 0 16V P3P3V
+

83 DGG2 MVE 201 MCUCMD 192


84 146 R4 7 0 PW1230 C6 5 C6 6 188
DGG3 CGMS TP 53 MCURDY
86 DGG4 TESTCLK 144
87 18 P J 18 P J PW1230
DGG5 DI_RE SET
88 DGG6
89 DGG7 I2C : 0X64
91
OPTI ON
DGR0
92 DGR1
[P. 1] VIDE O_RESET 0 R4 8
94 DG0 47 1 RN8 12 RV 0
DGR2 DG1 RV 1
95 DGR3 2 7
97 DG2 3 6 RV 2
DGR4 DG3 RV 3
98 DGR5 4 5
99 V33 D P3P3V
DGR6 RN8 13 L5
100 DG4 47 1 RV 4
DGR7 DG5 RV 5
2 7
66 DG6 3 6 RV 6
DGHS DG7 RV 7 42 OHM
67 DGVS 4 5

1
68 DGCLK DR0 47 1 RN8 14 GY 0 P2P5V + C6 7
L6 10U C6 8
PW1230 DR1 2 7 GY 1
DR2 3 6 GY 2 AV D2 5 16V 0.1U K

2
DR3 4 5 GY 3
42 OHM

1
C6 9 C7 0 C7 1
DR4 47 1 RN8 15 GY 4 +
DR5 2 7 GY 5
DR6 3 6 GY 6 22U 0.1U K 0.01U K

2
DR7 4 5 GY 7 16V
P3P3V VCC U7
L7
P2P5V
Chan ge color space from AV D3 3 3 VIN VOUT 2

GN D
42 OHM
RGB8 88 to YUV 444

1
C7 4 R4 9 + C7 2
C7 3 C7 5 LM317 M 681F 47U C7 6

1
0.1U K 0.01U K 0.1U K 16V 0.1U K

2
P2P5V

1
P2P5V R5 0
681F + C7 7
L8 10U
C7 8 C7 9 C8 0 C8 1 C8 2 C8 3 C8 4 C8 5 AV DD2 16V
20L0BI

2
0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K
42 OHM 48.M 2306 .A00
P3P3V C8 7 VIDEO BOARD
C8 6 W ednesday, September 17, 2003
0.1U K 0.01U K

C8 8 C8 9 C9 0 C9 1 C9 2 C9 3 C9 4 C9 5 C9 6 C9 7 C9 8 C9 9 C 100 C 101 L9
0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K AV DD1
42 OHM
C103
C 102
0.1U K 0.01U K

C 104 C 105 C 106 C 107 C 108 C 109 C 110 C 111 C 112 C 113
0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K 0.1U K

LCD03B
First issue 10 / 03
VIDEO SIGNAL PROCSSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( VIDEO BOARD 4/6, 20”BI)

VCC +9V AV_SEL OUTPUT


C 114
LO W CVBS
R5 1
0.1U K 68K HIGH TV
C115 + C 116
R5 2 Q3 10 U 0.1U K
J6 10 0 2N3904 16V AV_SEL [P. 1]
1000 OHM R5 3 R5 4 0
TP 54 5 6 TP 55 CVB S_IN L10 68K
5 6
Bott om View C117 10 U 16V

+
+5VS R5 5 1K

3 4 TP 56 R5 6 1K [P. 1]

16
3 4 LI1 U2C

9
5 6 3 CVBS 5
4 CVBS_V D
1 1 2 2 TP 57 R5 7 1K
DN1 RI 1
[P. 1] [P. 4] VIDEO_I N 3
[P .2 ]
R5 8 R5 9 D1 D2 R6 0 BAV99 74HC 4053

6
7
8
3 4
2210018561 75 3 1 2

TZMC5V1

TZMC5V1
22K 22K
2N3904
1 2 2N3906
TZ MC 5V1 TZ MC 5V1

D3 D4

J7
1000 OHM
3 TP 58 L11 VCC
Y
Bott om View C120 10 U 16V

+
+5VS
1 R316 C 189
. DN2 68K 0.1U K
G1 TP 41 BAV99
S1 G1 G1 TP 59 R7 1 R323 Q305
S1 10 0 2N3904 [P. 2]
75 R317 R311 0
S_Y
1 3 . 2 68K
G2
R318 1K
C 4

2 4 1000 OHM VCC


L12
G3 2210289001 C124 10 U 16V

+
R7 2 C 122
+5VS 68K 0.1U K
INPUT_D ET DN3
BAV99 R7 4 Q6
R8 2 10 0 2N3904 [P. 2]
R7 6 R7 7 0
75 68K S_ C

R8 0 1K

+9V
1000 OHM
L42 VCC
CVBS_SEL Output
C128 C129 R253
+ 56 0 C 130 R8 8 LO W CVBS_VD
0.1U K 0.1U K 68K Q9
10 U 2N3904 [P. 1] HIGH SCART_CVBS
16V C133 10 U 16V R9 0
+

16

11
CVBS_SEL
10 0
+9V R9 4 R9 5 0 TV 12 U2 A
14 VIDEO_I N
R345 22 68K [P. 5] SCART _CVBS 13 74HC 4053
+9V
J8
R254
47 0
13.2 2032.092 R9 7 1K

6
7
8
TP 61 1 2 TP 62 L13 1000 OHM C1902 110 U 16V
TP 63 R8 9 10 0
+

3 4
TP 64 5 6 TP 65 R9 1 10 0 R344 10 0 Q22 [P. 5]
7 8 TP 66 R7 3 NC_R0603 2N3904 R9 2 68
T UNER_ DE T VIDEO_ OU T
9 10 T UNER_ACK
[P. 6] Q23
TP 10 9 11 12 TP 68 SCL _TV [P. 1] 2N3906
TP 11 0 13 14 TP 69 SDA _TV R251
1K

2060201207

RI 2
[P .1 ]
R333
NC_R0603
SC ART _LOUT LI2
[P .1 ]
R332
NC_R0603 VCC V33 D
SCART_R OU T R109 47 0 [P. 5]
R110 47 0 SCART_R OU T
R107

R108

SC ART _LOUT
[P. 5]
1

C203 C204
Top View (ST) Q10 Q11 C201 C202
20L0BI
3.3K

3.3K

NC_C0603 NC_C0603 VIDEO BOARD


14 2 48.M 2306 .A00
2 3 3 2 SC L
[P. 1] NC_C0603 NC_C0603
W ednesday, September 24, 2003
1

13 1 Q12 BSN20 BSN20 Q13

2 3 3 2 SDA
[P. 1]

BSN20 BSN20

LCD03B
First issue 10 / 03
VIDEO SIGNAL PROCSSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( VIDEO BOARD 5/6, 20”BI)

J9 +5VS VCC
[P. 4]
R324 0 TP 70 1 [P. 5] DN6
SCART_R OU T
2 TP 71 R326 0 SC ART _AR_I N BAV99
R325 0 TP 72 3 C 140
SC ART _LOUT
4 TP 73 0.1U K R113
[P. 4] C141 C142 5 [P. 5] 68K
1000 P J 6 TP 74 R327 0 SCART_AL_I N
1000 P J SCART _BLUE_ IN TP 75 7 L14 1000 OHM
D5 TP 76 R328 0

D6
8 SCART_S WI TC H R114 Q14
[P. 5] SCART_CVBS_ IN
9 C143 10 U 16V 10 0 2N3904 [P .2 ]

+
10 CL K_OU T TP 77 D1 3 [P. 5] [P. 5] R115 R116 0
TP 78 SCART _CVBS
TZMC5V1

TZMC5V1
SC ART_GREEN_I N 11 12.4~14. 1V R117
12 DA TA _OUT TP 79 75 68K
[P. 5] 13
14
SCART_ RED_IN TP 80 15 L43 R118 1K
16 TP 81 SCART _BLN K
D7

D8

[P. 5] 17 D1 6 1000 OHM

D1 4
18 TZ MC 5V1 R125 [P. 2]
TP 82 19
TP 83
TZMC5V1

TZMC5V1

20 SCART_CVBS_ IN SCART_AL_I N
R119 1K
LI4
[P. 1]
21 75

TZMC5V1
[P. 5] [P. 5]
D9 TZ MC 5V1 D1 0 T ZM C 5V1
2210285001
SC ART _AR_I N
R120 1K
RI 4
[P. 1]
[P. 5]
R121 R122 D1 1 T ZM C 5V1 D1 2 T ZM C 5V1
22K 22K
DN8 +5VS
1 2

BAV99
3

L15 +5VS
VIDEO_ OU T DN9
1000 OHM BAV99
[P. 4]
C 205
0.1U K

1000 OHM
SCART _BLUE_ IN
L16
SCART _BLU E
[P .2 ]
[P. 5] R126

75

Mode 1 Mode 2
8.6-12V 0 0 Auto +5VS

DN 10
3.5-8.6V 1 0 16:9

2
BAV99
0-3.5V 1 1 Manua l +5VS C 206
3 0.1U K

+5VS R224 R225


1000 OHM

1
SC ART_GREEN_I N
L17
SCART_GR EEN
[P .2 ]
10K 10K [P .5 ] R132
R216 R217
4.3K 10K 75
4

R215 U1 5 SC ART_ MO DE 1 [P. 6]


10K 0V ~4.85V
V+

3 1 R220 100K Q15


SCART_S WI TC H IN1+ OUT1
2 IN1-
2N3904 SC ART_ MO DE 2 [P. 6]
+5VS
[P. 5] 3.4 9V
5 IN2+ OUT2 7 R221 100K Q16 R127 0 TV_DET [P. 1] DN 11
6 2N3904
IN2-

2
1.4 0V BAV99
R222 R223 C 207
R245 R218 R219
10
9
IN3+ OUT3 8
High Active 3 0.1U K
6.8K 10K 3.9K IN3-
12 IN4+ OUT4 14
13 NC_R0603 NC_R0603 1000 OHM
IN4-

1
SCAR T_ RED_IN L18
SC AR T_ RE D
[P .2 ]
GND

[P. 5] R138
LMV3 24M
11

75

20L0BI
VIDEO BOARD
48.M 2306 .A00
W ednesday, September 24, 2003

LCD03B
First issue 10 / 03
VIDEO SIGNAL PROCSSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( VIDEO BOARD 6/6, 20”BI)

+2. 5V

+3.3VDA C
C168 LAN G3 [P. 6]
+2.5VDA C +2.5VDA C +2. 5V LAN G2 [P. 6]
C 167 0.1U K [P. 6]

R189
R190
R191
R192
R193
0.1U K LAN G1
R171 R172
4.7K 4.7K C169 C170 C171
U1 3 +3.3VDA C

NC_R0603
NC_R0603
1 8 0.1U K +3.3VDA C 0.1U K 0.1U K
NC VCC

0
2 NC WP 7 V er P114V004
3 6 EE _SCL R237 NC_R0603 +3.3VDA C
NC SCL EE _SDA R238 NC_R0603 U1 4
4 GND SDA 5
1 52 LA NG 3
P0.0 P1.7 LA NG 2
AT 24C02 2 P0.1 P1.6 51
Ve r P115 3 P0.2 P1.5 50 LC B R174 NC_R0603
R239 0 4 49 IN FO R175 0
R240 0 P0.3 P1.4 LIST R176 NC_R0603
5 P0.4 P1.3 48
6 47 I2C_ EN R177 0
P0.5 P1.2 RG B_GAIN R178 NC_R0603
7 P0.6 P1.1 46
8 45 LA NG 1
P0.7 P1.0
9 VDD 2.5 VDD 3.3 44
10 VSS VSS 43
11 VDD 3.3 VDD 2.5 42
[P. 4] CVBS_INPUT C172 0.1U K 12 CVBS BLANK/COR 41 TT_FSB R179 0 FS B
R181 13 40 TT_ B R180 0 BLUE
VDDA 2.5 B TT _G R182 0 GRE EN
14 VSSA G 39
15 38 TT_R R183 0 RED
P2.0 R +3. 3V
16 P2.1 VDDA 2.5 37
NC_R0603 17 36
P2.2 VSSA
18 P2.3 XTAL1 35
19 HS/SSC XTAL2 34
20 33 TT_ RSTn R143 R144 R145 R146
VS RST- +3. 3V 22 0 68 68 68
21 P3.0 P4.3 32 Y3
TP 84 22 31 R252
P3.1 P4.2 FS B Q18
23 P3.2 VDD 3.3 30
R241 NC_R0603 24 29 R184 2N3904
P3.3 VSS
25 P3.4 P3.7 28 10K 6M HZ
R148 47 TT_BLNK [P. 2]
V er P114V004 26 P3.5 P3.6 27 0
[P. 1] SCL R236 R149 R150 10 TEX T_ B [P. 2]
[P. 1] R242 NC_R0603 SDA555x FL C 177 C 178 33 0 R151 10 [P. 2]
SDA TEX T_ G

NC_R0603
+ C176 33 P J 33 P J R152 10 [P. 2]
TE XT _R
I2C : 0X60 10 U
Ve r P115 16V RED 2N3906
R243 0 Q19
R244 0
GRE EN 2N3906
Q20

BLUE 2N3906
Q21

[P. 2] SVVS R185 0

[P. 2] SVHS R186 0

+3.3VDA C

R157 R158 R159 C161

NC_R0603
NC_R0603
0.1U K U1 1
16 VDD P00 4 LAN G1 [P .6 ]
3.3K
P01 5 LAN G2 [P .6 ]
[P. 1] SCL 14 SCL P02 6 LAN G3 [P .6 ]
[P. 1] SDA 15 SDA P03 7 SCART _F B_EN
P04 9
U9 13 INT P05 10 T UNER_ DE T [P .4 ]
VCC +3.3VDA C +3. 3V
P06 11 SC ART_ MO DE 1 [P .5 ]
3 VIN VOUT 2 L19 1 A0 P07 12 SC ART_ MO DE 2 [P .5 ]
1

BEAD 2 A1
GND

+ C 150 3 8
C 151 47U C 152 + C 153 A2 GND
0.1U K 16V 0.1U K 10U R160 R161 R162
LD1117-3. 3 PCA9554P W
1

16V
I2C : 0X48

NC_R0603
20L0BI
VIDEO BOARD 3.3K 3.3K
48.M 2306 .A00
W ednesday, September 24, 2003
U1 2
VCC +2.5VDA C +2. 5V
3 2 L21
VIN VOUT
BEAD
GND

R169 + C 162 + C 163


C 164 681F 47U C 165 10U
LM317 M
1

0.1U K 16V 0.1U K 16V

R170
681F + C 166
10U
16V

+3.3VDA C

PI N1 1 PI N3 0 PI N4 4

C 173 C 174 C 175


0.1U K 0.1U K 0.1U K

LCD03B
First issue 10 / 03
BLOCK DIAGRAM - SCHEMA SYNOPTIQUE - BLOCKSCHALTBILD - SCHEMA A BLOCCHI - INTEGRATED CIRCUITS BLOCK DIAGRAM
ESQUEMA DE BLOQUES
15”, 20" PortC PortB PortA A D CS
(7:0) (7:0) (7:0) JTAG Debugger (19:1) (15:0) (1:0) NMI TxD RxD

IR 2-Wire 16-Bit Processor ROM Wtchdog Interrupt


GPIO PWM Decoder Serial Microprocessor RAM Interface Timers Controller UART

Connector
Power

Tuner

Tuner Module
Processor On-
Memory Screen
Interface Display

14 pin

14 pin
pin

pin
2

VYUV
(7:0)
Microprocessor BUS
Memory
YUV Buffer DRGB
PFC/DC+DC/Audio Board

to Graphic (23:0)
OSD Color Color

SDA555XFL
RGB or Video Color
Scaler and LooKup Space

Teltext
Port Pixel Matrix
Gain Tables Expander DRGB
YPbPr Processing (23:0)

L/R Audio
to

60 pin golden finger

Input
RGB
20 pin

20 pin

GRGB Display
(23:0) Timing DVS,DHS
DEN,DCLK

60 pin
MCLK DCLK UCLK Generator
GVS Reset
GHS

Composite
GCLK Sync

Video
Auto Image PLL
VVS
Decoder
Optimisation
Power On
Reset
and PW113 Image Processor
And Timer
VHS Oscillator Internal Block Diagram

Video Board
VCLK
AT49BV8192A

GREF GFBK Reset X1 X0


EEPROM
pin

S-Video
8

Flash

VPC3230D
Decoder
Video
30 pin**
30 pin**
pin

PW113
Scaller
15" model only**
8

SCART
Inverter

Main Board

De-Interlace
40 pin**

40 pin**

PW1230
Chipset
LCD Panel

Input Unit Memory Unit Display Unit


Film-Mode Display
Premary Detection Timing Digital
20" model only*

Video Port (3:2&2:2)


Motion Output
ITU-R BT 601
50 pin*

50 pin*

Detection Previous Timing


& Video I-Channel Deinterlacer
Premary
Audio Processor

Noise I-Channel Picture


TDA7440D

Secondary Video Reduction Up


Video Port (l/P) P-Channel
Unit Scaler
ITU-R BT 6656 P-Channel
Audio Line Out

Down RGB
Scaler
Digital Video
Graphic Port Enhancement YUV
24-Bit
System Block Diagram (EU version)

AD9883

CSC
AD

Audio Input

Two-Wire
Interface Proramming Unit VSync/ Analog
Color Blue
Keypad/IR Interface

HSync DACs Output


Control

Lut Screen
Board

PW1230 Timing
Digital
Interna Block Diagram Output
Data
DDC

D-Sub
12 pin

12 pin
15" ,20"

LCD03B LCD03B
4 First issue 04 / 04 First issue 04 / 04 63
INTEGRATED CIRCUITS BLOCK DIAGRAM INFORMATION - INFORMATIONS - INFORMATIONEN
INFORMAZIONE - INFORMACIONES

A { 16 to A20 }

A { 0 to 15 }
SDA55XX

D { 0 to 7 }

PSEN
Analog / MUX

ALE

WR
RD
ADC ADC EN Chassis group table
1 - The electronic chassis configuration (modules) and schematic diagram page numbers.
Slicer 2 - The chassis configuration.
Memory
RAM Extension Acquisition
256x8 STACK PROGRAM ROM
128x8 128K x8 Acquisition Interface FR Le tableau ci-dessous regroupe :
WDT
ADC
Interface
1 - L’environnement électronique de chaque chassis (modules) et le numéro de page où il est décrit.
Memory
Extension / Unit XRAM 2 - La désignation des chassis
Capture Control SRAM
Peripheral Counter 0
BUS 16K x8bit
BUS CORE
PWM Arbiter
Interface
Counter 1
P { 0 to 04}

Interrupt DE Die nachstehendeTabelle umfaßt:


Port Logic Contoller Caracter 1 - Die elektronischen Baugruppen (Module) der Chassis varianten und die Seiten auf der sie beschrieben werden
ROM
UART
2 - Die Chassisbezeichnung
16K x8bit
RAM / ROM Interface
H
SFRs V
CLOCK & Display Logic
Sync IT La tabella qui di seguito contiene:
System
DISPLAY GENERATOR 1 - l’ambiente elettronico di ogni telaio (moduli) e il numero di pagina nella quale è descritto.
CLUT BLANK / COR 2 - La descrizione dei telai
Display
REGs
FIFO

DAC's
ES El cuadro siguiente agrupa:
R G B 1 - El entorno electrónico de cada chasis (módulos) y el número de página donde está descrito.
2 - La designación de los chasis

31...34 Chassis LCD03B


71
CIN Y Y
37...40 Reference Information Desassembly. Service FCB KDB Inverter DC/DC Audio Earphone Main Video
72 Analog Adaptive Color Mixer 2D Scaler Output Y OUT
VIN1 Front-end Comb Decoder Formatter 41...44 - Mode - - -- Board Board
PIP
73 Filter 47...50 CrCb
VIN2 NTSC Cr Cr Panorama ITU-R 656 15LCDM03B 3 6to7 10to15 “ 16to18 23to24 19to20 25 26 27to41 42to58
74 OUT
PAL Mode ITU-R 601 20LCDM03B 3 6to7 10to15 “ 16to18 23to24 21to22 25 26 27to41 42to58
VIN3 18 20LCDB03B 3 8to9 10to15 “ 16to18 - 21to22 25 26 27to41 42to58
75 AGC NTSC SECAM Peacking YCOE
VIN4 2 x ADC PAL Cb Cb Contrast Memory
Saturation Brightness 19...23 FIFO
70 Control
VOUT Tint CNTL

Y/G
VPC3230 27,28
1..3 Analog Processing Y LLClock
RGB/
Component U/B I2 C Bus Sync
YCrCb Cr 56
Matrix + H Sync
79 Front-End
FB Contrast Clock 57
V/R
Saturation Cb Generation V Sync
RGB/ 4..6 Clock
4 x ADC FB Brightness 54
FB Gen.
YCrCb Tint AVO
62 63 13,14

20.25 MHz I2C Bus

AD9883A
54 8 70...77
R AIN CLAMP A/D R OUTA

48 8 2...9
G AIN CLAMP A/D G OUTA

43 8 12...19
B AIN CLAMP A/D B OUTA

37
MIDSCV
30 67
HSYNC DTACK
29 SYNC 66
CO AST PROCESSING HSOUT
38 AND CLOCK 64
CLAMP VSOUT
33
GENERATIO N 65
FILT SOGOUT
58 REF
56 REF
SCL BYPASS
57 SERIAL REGISTER
SD A AND
A0
55
POWER MANAGEMENT AD9883A

LCD03B LCD03B
64 First issue 04 / 04 First issue 04 / 04 3
Couv_1&4_EU_ITC222 12/12/03 16:11 Page 1 (1,1)

This technical documentation is for use by maintenance technicians only


Documentation technique exclusivement destinée aux professionnels de la maintenance
Diese Angaben und Hinweise sind ausschließlich für den Service des Fachhändlers bestimmt
Documentazione tecnica destinata esclusivamente ai tecnici dell'assistenza
Documentación técnica destinada exclusivamente a los profesionales de mantenimiento

TV

SERVICE MANUAL
DOCUMENTATION TECHNIQUE
Thomson multimedia
Scandinavia AB
Florettgatan 29 C
TECHNISCHE DOKUMENTATION ITC222
S-25467 Helsingborg (Sweden)
Tel. : 042 25 75 00 DOCUMENTAZIONE TECNICA
DOCUMENTACION TECNICA

Thomson multimedia
Sales UK Limited
30 Tower View
Kings Hill, West Malling
Kent ME19 4NQ (England)
Tel. : 44 (0) 173 252 0920

Thomson multimedia
Sales Germany GmbH & Co oHG
Karl-Wiechert-Allee 74
30625 Hannover

Thomson
Consumer Electronics Poland
ul.Gen.L. Okulickiego 7/9
05-500 Piaseczno (Varsovie)
Tel. : (22) 757 10 80

30 000 000 - Siège : 46, quai Alphonse Le Gallo 92100 Boulogne France - RCS Nanterre B 322 019 464
Thomson multimedia
Sales France Thomson multimedia
46, quai Alphonse Le Gallo Czech s.r.o.
92648 Boulogne cedex ul. Dopravaku - dum Genius 1
Tel. : 01 41 86 60 00 Dolni Chabry
Minitel : 3616 ou 3623 TCEDS CZ - 18400 Prague 8
Internet : http://www.thomson.fr Tel. : (2) 688 67 70 Thomson multimedia
Hungary KFT
Lajos u. 78. II.em.
H-1036 Budapest
Thomson multimedia Tel. : 00 36 14 5334/80
Switzerland
Seewenweg 5
CH-4153 Reinach
Tel. : (61) 716 96 60

Thomson multimedia Thomson multimedia


Sales Portugal Sales Italy S.p.A.
Avenida da Boavista, 3521 Via Leonardo da Vinci,43
4106 Porto 20090 Trezzano sul naviglio (Milano)
Tel. : (2) 26 18 76 41 Tel. : (02) 48 414 111

Thomson multimedia
Sales Spain
Avenida Isla Graciosa, 1
Edificio Áncora
Parque Empresarial La Marina
28700 San Sebastián de los Reyes (Madrid)
Tel. : (91) 384 14 19
Thomson multimedia Sales Europe - S.A. au capital de

WARNING : Before servicing this chassis please read the safety recommendations.
ATTENTION : Avant toute intervention sur ce châssis, lire les recommandations de sécurité.
ACHTUNG : Vor jedem Eingriff auf diesem Chassis, die Sicherheitsvorschriften lesen.
ATTENZIONE : Prima di intervenire sullo chassis, leggere le norme di sicurezza.
IMPORTANTE : Antes de cualquier intervención, leer las recomendaciones de seguridad.
The description and characteristics given here are of informative significance only, and non committal. To keep up the high quality of our products, we reserve the right to
make any changes or improvement without previous notice. • Les descriptions et caractéristiques figurant sur ce document sont données à titre d'information et non
d'engagement. En effet, soucieux de la qualité de nos produits, nous nous réservons le droit d'effectuer, sans préavis, toute modification ou amélioration. • Die
Beschreibungen und Daten in dieser Anleitung dienen nur zur Information und sind nicht bindend. Um die Qualität unserer Produkte ständig zu verbessern, behalten wir uns Code : 357 388 00 - 1203 / 6M - ITC222 - Print.
das Recht auf Änderungen vor. • Le descrizioni e le caratteristiche date su questo documento sono fornite a semplice titolo informativo e senza impegno. Ci riserviamo il
diritto di eseguire, senza preavviso, qualsiasi modifica o miglioramento. • Las descripciones y características que figuran en este documento se dan a título de información y No copying, translation, modification on other use authorized. All rights reserved worldwide. • Tous droits de reproduction, de traduction, d'adaptation et d'exécution réservés pour tous les pays. • Sämtliche Urheberrechte an diesen Texten und Zeichnungen stehen uns zu. Nachdrucke,
no de compromiso. En efecto, en bien de la calidad de nuestros productos, nos reservamos el derecho de efectuar, sin previo aviso, cualquier modificación o mejora. Vervielfältigungen - auch auszugsweise - nur mit unserer vorherigen Zustimmung zulässig. Alle Rechte vorbehalten. • I diritti di riproduzione, di traduzione, e esecuzione sono riservati per tutti i paesi. • Derechos de reproduccion, de traduccion, de adaptacion y de ejecucion reservados para todos los paises.

Das könnte Ihnen auch gefallen